JP3468505B2 - I / O circuit of semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit, and more particularly to a timing margin from an input / output terminal of a semiconductor device to a latch circuit provided immediately before a 3-state output buffer. The present invention relates to an input / output circuit which is improved to improve operating speed, power consumption, and reliability.

[0002]

2. Description of the Related Art A conventional input / output circuit of this type is used especially for an input / output circuit connected to an input / output terminal of a semiconductor device.

This input / output circuit is generally an input buffer for inputting data supplied from the outside and giving it to the internal circuit, and an output buffer for inputting data output from the internal circuit and outputting it to the external circuit. Further, the output buffer has three output states of a high level (hereinafter, referred to as H level), a low level (hereinafter, referred to as L level) whose output state is a logical level, and a high impedance state in an undefined state. Some have a function as a buffer, and the input end of the input buffer and the output end of the output buffer are commonly connected to one input / output terminal.

That is, one input / output terminal is used to set a 3-state output buffer in a high impedance state at the time of data input, and at the time of data output, the 3-state output buffer outputs a binary signal of H level or L level. The input terminal and the output terminal are also used.

Further, although the input / output circuit mediates the exchange of data with the external circuit as described above, it also has a role of preventing unnecessary noise from the outside and protecting the inside of the semiconductor device from electrostatic voltage breakdown. I have it.

Such an input / output circuit is usually built in the semiconductor device at the time of manufacturing, and it is required to have a continuous data input / output function as a function. Low power consumption and high reliability are also required.

An example disclosed in order to meet this demand is described in Japanese Patent Application Laid-Open No. 60-170094. Referring to FIG. 10 showing the configuration of the input / output circuit described in this publication, this conventional input / output circuit has an input / output terminal 100.
And an input / output switching control signal (read enable) from the input buffer 101 to which a signal is externally supplied to this terminal through the input terminal and the output of the input buffer 101 and the data N1 to be output from the internal circuit to the outside. Signal) output signal DI of the input buffer 101 in response to the L level of OE
Selector 102 for selecting the output data N1 of the internal circuit at H level, a latch 103 for holding the selected signal SD, and a 3-state output circuit for outputting the output signal of the latch 103 to the input / output terminal 100. Output buffer 1
It is composed of 04.

This input / output circuit has an input / output terminal 100.
The data input to the input buffer 101 and the selector 1
The data latched in the latch 103 via 0 and 02 are output at the same time when the operation state of the input / output combined terminal 100 is switched to the output operation, that is, the data input to the input / output combined terminal 100 until immediately before is output. This prevents unnecessary changes in the input / output terminals.

Referring to FIG. 11 which shows a timing chart for explaining the operation of the above-mentioned conventional input / output circuit, the output data N1 of the internal circuit is the data D0 while the input / output circuit is in the input state. , And the read enable signal OE given to the selector 102 and the output buffer 104 of three states is set to L level for 6 clock periods, for example, to set the state of the input / output circuit to the input state, and then During the period, the output is returned to the H level.

When the read enable signal OE is at L level and the 3-state output buffer 104 is in a high impedance state, the input / output terminal 100 after one clock.
Data D1, D2, D3, D4 are input to the input terminal and are selected by the selector 102 via the input buffer 101. The latch 103 sequentially latches and holds the selected signal SD at the next rising edge of the internal clock signal.

When the read enable signal OE is inverted and becomes H level, the selector 102 selectively outputs the output data N1 (D5, D6) of the internal circuit.
The latch 103 latches and holds 5 and D6 at the next rising edge of the internal clock signal. This held data D
5, 5 are output to the input / output terminal 100 via the 3-state output buffer 104.

In the figure, a high impedance period for one clock is provided before and after the data strings D1, D2, D3, D4. This high impedance period is generally called a turnaround time, etc. Simultaneous activation of 3-state output buffer and external data,
That is, it is generally defined as a specification for avoiding bus fight (for example, PCI, SDRAM
etc).

[0013]

The above-mentioned conventional input / output circuit is apparent from a comparison with FIG. 2 showing a configuration of a first embodiment of the present invention described later and FIG. 7 showing a timing chart thereof. In addition, in response to the read enable signal OE, the data externally input to the input / output terminal is selected by the selector and led to the subsequent latch circuit.

Therefore, while the input / output terminal is functioning as an input terminal, the latch circuit also operates according to the change of the input data, and as a result, useless power is consumed. . In addition, useless power consumption causes an increase in noise components, leading to a decrease in reliability.

Further, since the input data is directly derived to the selector via the input buffer, the timing margin from the input / output terminal to the latch subsequent to the selector is determined by the selector delay and the input buffer. There is also a problem that extra wiring delay up to the selector is required.

The object of the present invention is made in view of the above-mentioned conventional drawbacks. By selecting and latching necessary data from a continuous data string input to an input / output terminal, the input / output terminal can be used. (EN) It is intended to improve a timing margin from a terminal to a latch subsequent to a selector to provide an extremely good input / output circuit with higher speed, lower power consumption and higher reliability.

[0017]

A feature of the input / output circuit of the present invention is that a selector for selectively deriving external input data or output data of an internal circuit to a 3-state output buffer via an output side holding means. And an input / output circuit for controlling the selection operation of the selector and the output operation of the output buffer of the three states with a predetermined control signal, the selection operation of the selector and the output operation of the output buffer of the three states are different from each other. A control signal generating means for controlling with two control signals is further provided, and the three-state output buffer is in an input state in which the three-state output buffer is in a high impedance state by one of the two different control signals. And a continuous data string input as the external input data to the input / output terminal of the input buffer When selected by a selector and held by the output side holding means, the selector control signal of the selector is generated only at the same clock timing as the last data output timing of the continuous data string to generate only the final data. By holding the output side holding means, the number of operations of the output side holding means during the input operation is suppressed.

Further, when deriving the external input data to the output side holding means, an input side holding means may be further provided between the input buffer connected to the input / output terminal and the selector.

Further, the control signal generating means sets the selector control signal and the 3-state output buffer to a high impedance or output state in response to a first control signal input from the outside in synchronization with an internal clock signal. The generation period of the selector control signal is included in the period in which the read enable signal is activated to the high impedance state while being generated together with the enable signal.

Furthermore, the control signal generating means is pre-located in the 3-state output buffer by generating the selector control signal at least two cycles before the activation period of the read enable signal ends. In response to the selector control signal, the output side holding means latches the last data of the continuous data string externally input to the input / output terminal of the 3-state output buffer, and latches the data. The final data can also be output to the input / output terminal.

The selector selects the output data of the internal circuit and holds it in the output side holding means when the predetermined write request signal and the selector control signal are at a high level, and the output buffer of the three states. To the input / output terminal via the input / output terminal, and when the selector control signal is at the high level and the write request signal is at the low level, the input side holding provided between the input buffer connected to the input / output terminal and the selector is held. When the write request signal and the selector control signal are both at the low level, the output data of the input side holding means held by the output side holding means is changed to the high level by the selector control signal. You can also keep it until you do.

Further, the output side holding means responds to the high level of the selector control signal to hold the last data and outputs the output data of the internal circuit in response to the high level of the write request signal. It is also possible to keep holding until it is selected by the selector and read.

Another feature of the input / output circuit of the semiconductor device of the present invention is that it has one input / output terminal and output data of the internal circuit.
Is output to the I / O terminal and a predetermined control signal is output.
3-state output that outputs high impedance
Force buffer and the input in the high impedance state.
Input buffer for inputting specified data from output shared terminal
And the output of the input buffer is synchronized with the internal clock signal
And first holding means for temporarily holding the first holding means and the first holding hand
The output of the stage is received at the first input end and at the second input end
Receives the output data of the internal circuit, and further receives a first control end
The child has a write request signal given to an external control circuit.
Set value of the specified mode setting signal at active level
m for the clock cycle period specified by m (m is a real number)
Because it becomes a level and selectively outputs the m data strings
Receive the write enable signal from the external control circuit.
Selector and the output selected by the selector.
The sync data is held temporarily and the held data is
Output to the output buffer and
Second holding means for returning to the input end of No. 3, and the external control circuit
If the read request signal given to the
At a predetermined setting value n (n is a real number) of the mode setting signal
Active level for a specified clock cycle period
The data output timing control signal becomes
Of the data output timing control signal.
1 clock cycle from the transition timing to the active level
Clock delay and the data output timing control signal
At least 3 clock cycles longer than the active level period
The read enable signal that remains active for as long as
Is generated and the 3-state output buffer is
The read enable signal.
1 clock from the transition timing of the signal to the active level
Cycle delay and the activation of the read enable signal.
And the first input / output terminal and the first
The delay is further delayed by one clock cycle via the holding means.
Nth of the n data strings output to the selector
1 clock cycle at the same clock timing as the eye data
Also outputs a selector control signal that turns active level only
To control the second control terminal of the selector to control the n-th
First control signal generating means for selectively outputting only eye data
And each of the above n data strings are continuously input
The active level of the selector control signal
In response to the selection, the selector selects only the nth data.
The number of changes in the output of the second holding means by performing selective control.
It is to have a current consumption control function to the first n minutes.

Further, the first control signal generating means includes third, fourth and fifth holding means connected in cascade for inputting the data output timing control signal in synchronization with the internal clock signal. third, the negative logical oR means taking a logical output signal and the data output timing control signals of the fourth and fifth holding means, for holding and synchronizing the output of the NOR means to said internal clock signal A means for generating the read enable signal , which comprises a sixth holding means, a logical product means for taking the logic of the polarity inversion output of the output of the third holding means and the output of the fourth holding means, and this logical product. Selector control signal comprising seventh holding means for holding the output of the means in synchronization with the internal clock signal
And a generating unit of

Further, the synchronizing means of the first and second holding means are controlled by the first clock control means and the second clock control means instead of the internal clock signal, and the first control is performed. Second control signal generating means is provided in place of the signal generating means, and the second control signal generating means outputs the data output timing control signal together with the read enable signal and the selector control signal for two cycles of the internal clock signal. The first clock control means further comprises an eighth holding means for holding the latch control signal in synchronization with the internal clock signal and an output signal of the eighth holding means. And a logical product means for extracting an internal clock signal, wherein the second clock control means includes the write enable signal and The internal clock signal is composed of a logical sum means for taking the logic of the selector control signal, a ninth holding means for holding the output signal of the logical sum means in synchronization with the internal clock signal, and an output signal of the ninth holding means. It can also be configured with a logical product means for extracting.

Furthermore, one set of each of the second control signal generating means, the first clock control means and the second clock control means allows the second holding corresponding to the plurality of input / output terminals. Select in front of the means
Motor and said second holding means and the output buffer of the three-state may be a common control, respectively.

Further, the first and second holding means operate only at the rising timing of the control clock signal output from the first clock control means and the second clock control means, and other than the above. It is also possible to suppress the holding operation during the internal clock signal period and suppress the current amount due to the holding operation in response to the internal clock signal.

Furthermore, only the output signal of said first and said second holding means, an input signal of <br/> selector prefix of the second holding means, a selected one of the two signals The three-state output buffer that outputs the signal can also be used as the floating prevention means of the input / output terminal.

[0029]

[0030] Furthermore, the selector is, the data string input to the input-output terminals can be input directly without the first holding means.

[0031] It is also possible to form the control circuit and the data generating circuit is also one or either be formed on the same chip including only included in the same chip.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a system configuration diagram to which the first embodiment of the present invention is applied. Referring to FIG. 1, a system using the input / output circuit of the present invention includes an input / output circuit 11 of the present invention and a write request signal WR (Write Request) which is a control signal generated by a predetermined signal generation circuit (not shown). ), A read request signal RD (Read Request), and a mode setting signal M
If the value of the mode setting signal MD is n (n is a real number) in response to the H level of the write request signal WR as a control signal, the internal clock signal n is input.
Write enable signal WE that is set to H level during the cycle period
(Write Enable) and read request signal RD
The value of the mode setting signal MD is n in response to the H level of the signal.
If so, the data output timing control signal N2 which is set to H level for n cycle periods of the internal clock signal and this signal
A control circuit 12 that generates and outputs a data string control signal N3 that is shifted by a cycle, and a data generation circuit 13 that inputs the data string control signal N3 and generates and outputs n continuous data strings N4. Input / output circuit 11
On the other hand, the write enable signal WE , the data output timing control signal N2, the data string N4, and the output data N1 of the internal circuit are applied as input signals.

These may be formed on the same chip or may be formed on different chips. Also, only one of them may be formed as a separate chip.

On the other hand, referring to FIG. 2 showing the block diagram of the configuration of the input / output circuit 11 of the present invention, the internal clock signal C is generated in response to the data output timing control signal N2.
The read enable signal OE for controlling the 3-state output buffer is generated at the same clock timing as the output timing of the last data of the data string N4 input in LK synchronization, and the internal clock signal is generated in response to the write enable signal WE. A control signal generator 116, which is a first control signal generating unit that also generates a selector control signal SEL for the selecting unit in synchronization with CLK, and an input / output terminal 10 for receiving input signals from the data string N4 and other external circuits.
a and an input buffer 111 that receives an input signal from the data string N4 input to this terminal 10a or an external circuit
And a latch 112 which is a first holding means for holding an input signal via the input buffer 111 in synchronization with a predetermined internal clock CLK, and data held by the latch 112 and output data N1 of the internal circuit. Between the selector 113 which is the selecting means, the latch 114 which is the second holding means which holds the selection data output from the selector 113 in synchronization with the internal clock CLK, and the latch 114 and the input / output terminal 10a. It is composed of a 3-state buffer 115 which is connected and whose output state is controlled to high impedance by the read enable signal OE.

Further, referring to FIG. 3 showing the configuration of control signal generator 116, the third, fourth and fourth cascade-connected control signal generators 116 input the data output timing control signal N2 in synchronization with the internal clock CLK. Latches 1161, 1162, 1163 which are fifth holding means and these latches 11
61, 1162, 1163 output signals M3, M4, M5
And a data output timing control signal N2. A NOR circuit 1164 which is a logical sum means and a latch 1165 which is a sixth holding means for holding the output of the NOR circuit 1164 in synchronization with the internal clock CLK. Output M3 of the read enable signal OE and an inverter circuit 1166 for inverting the polarity of the output of the latch 1161.
AND circuit 1167 which is a logical product means for taking the logic of B and the output M4 of the latch 1162 and this AND circuit 1167
Of the selector control signal SEL, which is composed of a latch 1168 which is a seventh holding means for holding the output M2 of the above in synchronization with the internal clock CLK.

Referring to FIG. 4 showing the truth table of its operation, the selector 113 outputs the output SD when the write enable signal WE and the selector control signal SEL which are input signals are "0" and "0", respectively. The output DO of the latch 114 is selectively output, the output SD selectively outputs the output DI of the latch 112 when "0" or "1", and the output SD selects the output data N1 of the internal circuit when "1" or "0". Output. The combination of "1" and "1" is a prohibited condition. Here, "0" indicates L level and "1" indicates H level.

Referring to FIG. 1, the relationship among the input / output circuit 11, the control circuit 12, and the data generating circuit 13 is that the control of the input / output circuit 11 according to the present invention depends on the data output control timing signal N2 from the control circuit 12. Timing control of the data string N4 of the data generation circuit 13 is also performed by the data string control signal N3 input from the control circuit 12, and when the data string control signal N3 is at the H level, the data generation circuit 13 changes the data string N4. Output. Further, the output data string N4 of the data generating circuit 13 is the input / output circuit 1 of the present invention.
The data output control timing signal N2 is input to the I / O terminal 10 of FIG. Furthermore, the input / output circuit 11, the control circuit 12, and the data generation circuit 13 all have the common point that they operate in synchronization with the rising of the internal clock signal CLK.

That is, the control circuit 12 detects the H level of the read request signal RD, and if the data value of the mode setting signal MD is "4" as a result of the detection, the data output control timing signal N2 is set to 4. If the data value of the mode setting signal MD is "2", the data output control timing signal N2 is set to the H level during the cycle period,
To level.

When the H level of the write request signal WR is detected, if the data value of the mode setting signal MD is "4", the write enable signal WE is set to the H level for the "4" cycle period, and the data value of the mode setting signal MD is set. Is "2", the write enable signal WE is set to H level for two cycle periods.

On the other hand, the data string control signal N3 output from the control circuit 12 is generated by shifting the data output control timing signal N2 output from the control circuit 12 by one cycle.

The control circuit 12 and the data generation circuit 13 which perform the above-mentioned operations can be easily realized by those skilled in the art, and since they are not directly related to the configuration of the present invention, their detailed configuration will be omitted. .

Next, the operation of the system shown in FIG. 1 will be described. Referring to FIG. 1 and FIG. 5 showing a timing chart for explaining the operation thereof and FIG. 2 as needed, the mode setting signal MD outputs the data value “4” and the write request signal WR outputs the L level. It is assumed that At this time, when the read request signal RD becomes H level, the data value of the mode setting signal MD is "4", so the control circuit 1
From 2, the data output control timing signal N2 is output as H level for four cycle periods in synchronization with the falling timing of the write request signal RD.

At this time, the data string control signal N3 is similarly output as H level for four cycle periods with the data output control timing signal N2 shifted by one cycle.

When the data output control timing signal N2 becomes H level, the input / output circuit 11 enters the input state. When the data string control signal N3 becomes H level for 4 cycle periods, the data generating circuit 13 shifts by 1 cycle from the rising timing of the data string control signal N3 in response to the data string control signal N3 at H level for 4 cycle periods. Data D1, D2 for 4 cycle period from timing
D3 and D4 are output as a data string N4.

The input / output circuit 11 inputs the data D1, D2, D3, D4 from the input / output terminal 10 into the input buffer 111 of FIG.

Next, when the data string control signal N3 becomes L level after four cycles have elapsed, the data generation circuit 13 also responds to the L level timing, and the data D1, D2, and D1 after one cycle from the L level timing. The output of D3 and D4 is terminated, and the potential of the input / output terminal 10 of the input / output circuit 11 is in a high impedance state for a period of two cycles from the end timing. During this time, the mode setting signal M
It is assumed that D has its data value reset to "2", for example.

On the other hand, the data output control timing signal N2
The input / output circuit 11 enters the output state in response to the change to L level, and starts outputting predetermined data to the input / output combined terminal 10.

When the write request signal WR becomes H level while the input / output circuit 11 is in the output state, the control circuit 12 outputs the write enable signal WE at a timing one clock after the rising timing of the H level. However, the data of the mode setting signal MD at that time is "2".
Therefore, the write enable signal WE is output as the H level for the 2 cycle period.

When the write enable signal WE becomes H level while the input / output circuit 11 is in the output state, the input / output circuit 11 outputs the output data N of the internal circuit at a timing one clock after the rising timing of this H level.
1 is output via the I / O terminal 10.

When the input / output circuit 11 is in the input state, the data D1, D2, D at the input / output combined terminal 10 is used.
3, the high impedance period before and after the D4 input period is generally referred to as the turnaround time as described above, but the three-state of FIG. 2 to which the input / output combined terminal 10 (10a in FIG. 2) is connected. Output buffer 11
5 is generally defined as a standard for avoiding simultaneous activation of output signals and input data, that is, bus fight.

The high impedance period after data input in this embodiment is two cycles, which is longer than the one cycle in the conventional example, by one cycle. This is because the output signal DO of the latch 114 in FIG. This is because the change (D0 → D4) and the rise of the read enable signal OE have a skew. This is to prevent the data D4 from being output once to the input / output terminal 10 when the change of the output signal DO of the latch 114 and the rising of the read enable signal OE are simultaneous. .

Next, the operation of the input / output circuit 11 according to the first embodiment of the present invention will be described. First, the control signal generator 11 will be described.
The operation of No. 6 will be described. FIG. 3 and control signal generator 1
Referring also to FIG. 6 showing a timing chart for explaining the operation of No. 16, in synchronization with the rising timing of the internal clock signal CLK, for example, the latch 1161 latches the data output control timing signal N2 of H level for four cycle periods. , The output is sequentially latched by the latches 1162, 1163 to shift the data output control timing signal N2 by 3 cycles, and the data output control timing signal N2, the output M3 of the latch 1161, and the latch 11 are output.
The output signal M1 of the NOR circuit 1164, which receives the output M4 of 62 and the output M5 of the latch 1163, is input to the latch 116.
By shifting by 5, the read enable signal OE of L level is generated for 7 cycle periods.

On the other hand, the AND circuit 1167 which receives the output signal M3B of the inverter circuit 1166 which receives the output M3 of the latch 1161 and the output M4 of the latch 1162 which receives the output signal M3B.
The selector control signal SEL is generated by shifting the output signal M2 of 1 by the latch 1168.

These data output control timing signals N
2, read enable signal OE and selector control signal SE
Looking at the phase relationship with L, the fall timing of the read enable signal OE is shifted by one clock cycle with respect to the rise timing of the data output control timing signal N2, and selector control is performed with respect to the fall timing of the read enable signal OE. The rising timing of the signal SEL is shifted by 5 clock cycles and is synchronized with the internal clock signal CLK.

Next, the operation of the entire input / output circuit 11 will be described. Referring to FIG. 2 and FIG. 7 which is a timing chart for explaining the operation of the input / output circuit 11, it is assumed that the write enable signal WE is at the L level. At this time, when the data output control timing signal N2 becomes H level for, for example, four clock cycle periods, the data generating circuit 13 responds to this H level by the operation described above, and one clock starts from the rising timing of the data output control timing signal N2. The read enable signal OE which is at L level for 7 clock cycle periods is output from the timing after the cycle.

In response to the L level of the read enable signal OE, the 3-state buffer 115 is inactivated, the input / output shared terminal 10a is in a high impedance state, and is in a state of waiting for input data.

As described above, the data generation circuit 13 starts data D from the timing two clock cycles after the rising timing of the data output control timing signal N2.
Since 1, D2, D3, D4 are output as the data string N4, the data D1, D2, D3, D4 are input to the input / output terminal 10a as continuous data of one cycle or more.

The data D1, D2, D3, D4 input to the input / output combined terminal 10a is latched by the latch 112 via the input buffer 111, shifted by one clock cycle, and input to the selector 113.

At this time, the selector 113 selects and outputs the output of the subsequent latch 114 because both the write enable signal WE and the selector control signal SEL are at the L level according to the truth table of FIG. Is data D0 which is the selector selection output when the previous selector control signal SEL is at H level.

Data D1, D2 and D are sent to the selector 113.
The selector control signal SEL rises to the H level at a timing 4 clock cycles after the input of 3, D4 (shifts by 5 clock cycles with respect to the falling timing of the read enable signal OE), and the selector 113 is in this H level period. The data D4 input to is selected and output, is latched by the subsequent latch 114, is shifted by one clock cycle, and is output (the output value D4 of the output signal DO of the latch 114).

That is, the clock timing for selecting the data D4 and the clock timing for the selector control signal SEL to rise to the H level are synchronized with the rising edge of the same clock. Also, the output signal DO of the latch 114
Timing of output value D4 of selector and selector control signal SE
The falling timing of L is synchronized with the rising timing of the same clock.

The above-mentioned continuous data D1, D2, D
Since the selector control signal SEL becomes H level and the read enable signal OE is still in L level in synchronization with the rising timing of the same clock in which the rising timing of the last data D4 of 3 and D4 is synchronized, the data D1, D2 , D3, D4 have been input, the input / output combined terminal 10a is again in the high impedance state.

The above-mentioned high impedance state generally does not change the potential of the input / output combined terminal 10a, and the potential is held for a fixed time (several milliseconds to several seconds) due to the parasitic capacitance of the input / output combined terminal 10a. Because
In a high-speed system with a short clock cycle time (several nanoseconds to several microseconds), the potential of the input / output combined terminal 10a is maintained even in the high impedance state.

Next, read enable signal OE attains H level, and 3-state buffer 115 is switched from the input state to the output state. The 3-state buffer 115 is activated to the output state and outputs the output signal DO of the latch 114 to the input / output shared terminal 10a. At this time, the final data D4 input to the input / output shared terminal 10a.
However, since it is latched by the latch 114 and held and output as the signal DO, the input / output dual-purpose terminal 10a has the data D4.
The input state is switched to the output state while holding.

Since the 3-state buffer 115 is in the output state when the read enable signal OE is at the H level,
The 3-state buffer 115 outputs the output signal D of the latch 114.
The data D4 which is O is output to the input / output terminal 10a.

At this time, since the selector control signal SEL is already at L level, if the write enable signal WE is at L level, the output signal DO (data D
4) is the selector 113 as shown in the truth table of FIG.
Is output as a selection output signal SD of the selector 113 and is input to the latch 114.

Since the latch output is input to the selector again and selected, the output signal SD of the selector 113 continues to output the same data D4 even if the internal clock signal changes, and the signal SD is input. Latch 11
Since 4 also keeps the data D4, its output signal DO does not change, and therefore the input / output terminal 10a does not change.

Further, since the selector control signal SEL is already at the L level, if the write enable signal WE is at the H level, the data D5 and D6 of the output signal N1 of the internal circuit are as shown in the truth table of FIG. Selected by the selector 113 and output as a selection output signal SD, the latch 114
Data D5 and D6 are output to the I / O terminal 10a via the 3-state buffer 115.

In the above embodiment, the control circuit 12 generates the control signal of the input / output circuit of the present invention as an example of the system configuration.
3 may generate signals corresponding to the data output control timing signal N2 and the data string control signal N3, and control the input / output circuit of the present invention by these signals.

That is, as described above, the control circuit 12
Detects the H level of the read request signal RD, and if the detection result indicates that the data value of the mode setting signal MD is "4", the data output control timing signal N2 is set to the H level for four cycle periods to set the mode. If the data value of the signal MD is "2", the data output control timing signal N2 is set to H level for two cycle periods, and when the H level of the write request signal WR is detected, the data value of the mode setting signal MD is "4". If so, the write enable signal WE is set to the H level for the “4” cycle period, and the mode setting signal MD
If the data value of is “2”, the write enable signal WE
Is set to H level for two cycle periods, and the control circuit 12
The output data string control signal N3 is generated by shifting the data output control timing signal N2 output from the control circuit 12 by one cycle, and generates the generation signal of the data generation circuit.

In the above-described embodiment, the single control signal generator 116 controls the input / output terminal 10a, the selector 113 and the three-state buffer 115, but the control signal generator is not limited to this. One 116 may be configured to control the selector and the three-state buffer for a plurality of input / output terminals.

Further, when the output state of the input / output circuit of the present invention is used only for preventing floating of the input / output terminal, the signal N1 and the write enable signal WE can be omitted. That is, the input / output circuit of the present invention is
Since it can be used as a means for preventing the floating of the input terminal in the input circuit, it is not necessary to attach a pull-up resistor or a pull-down resistor to the I / O terminal.

As described above, since the input / output circuit of the present invention is provided with the control signal generator 116, in the input state of the three-state buffer, the data string input to the input / output combined terminal 10a and continuous for any cycle is provided. Since only the last data of the above is fetched into the latch 114, the change of the output signal DO of the latch 114 occurs only once in synchronization with the same clock timing as the output timing of the last data, and the current consumption is reduced. The effect is obtained.

For example, when data comes in continuously for 4 cycles, the number of changes of the output signal DO of the latch 114 can be reduced to 1/4 from 4 times, and similarly, data can be continuously output for 8 cycles. When comes, it can be reduced to 1/8.

In other words, the number of changes of the signal DO when data is continuously received for n cycles can be reduced to 1 / n, and an effect of reducing current consumption can be obtained.

Since the reduction of the current consumption leads to the reduction of the noise component, there is an effect that the reliability is improved at the same time.

Further, since the latch 112 is provided at the output of the input buffer 111, the timing margin from the input / output dual-purpose terminal 10a to the latch 114 is reduced by the selector 1.
It is possible to obtain the effect of improving the signal delay at 13 and the delay due to the signal wiring from the input buffer 111 to the selector 113.

Conventionally, from the input / output terminal 10a to the latch 1
The signal path up to 14 was the input / output terminal 10a → the input buffer 111 → the selector 113 → the latch 114, but in the input / output circuit of the present invention, the latch 112 is provided between the input buffer 111 and the selector 113. As a result, the input / output combined terminal 10a → the input buffer 111 → the latch 112 is established, and therefore the timing margin from the input / output combined terminal 10a to the latch 114 is the selector 113.
It is possible to obtain the effect of improving the signal delay in the above and the wiring delay from the input buffer 111 to the selector 113.

Further, even if the latch 112 is not provided and the wiring of the output signal I1 of the input buffer 111 and the wiring of the output signal DI of the latch 112 are directly connected, the timing margin from the input / output terminal 10a to the latch 114 is improved. However, it is clear that the effect of reducing the current consumption can be obtained.

Next, a second embodiment of the present invention will be described. The basic configuration is the same as that of the first embodiment,
The control of the latch 112 and the latch 114 is further devised.

Referring to FIG. 8 which is a block diagram showing the configuration of the second embodiment, the difference from the first embodiment is that the latch 82 ( corresponding to the latch 112 in FIG. 2 ). To the latch 84 ( corresponding to the latch 114 of FIG. 2 ) and the clock signal control circuit 88 for providing the internal clock signal CLK to the latch 84 ( corresponding to the latch 114 of FIG. 2 ). The control signal generator 86 is configured to generate the signal M4 for controlling the clock signal control circuit 88 in the signal generator 116.

That is, the control signal generator 86 which is the second control signal generating means is equivalent to the control signal generator 116 of FIG. 2 shown in FIG. 3, but the read enable signal OE is used.
And the latch control signal M4 (the output signal M4 of the latch 1162 in the control signal generator 116 in FIG. 3 is extracted by shifting the data output timing control data output control timing signal N2 by two cycles of the internal clock signal CLK together with the selector control signal SEL). Use).

The clock control circuit 87 which is the first clock control means uses the latch 871 which is the eighth holding means for holding the latch control signal M4 in synchronization with the internal clock signal CLK and the output signal of this latch 871. It is constituted by AND 872 which is a logical product means for extracting the internal clock signal CLK.

The clock control circuit 88, which is the second clock control means, internally operates the OR circuit 881 which is the logical sum means for taking the logic of the write enable signal WE and the selector control signal SEL and the output signal J3 of this OR circuit 881. A latch 882, which is a ninth holding unit that holds the clock signal CLK in synchronization, and an output signal J of the latch 882.
2 and AND883 which is a logical product means for extracting the internal clock signal CLK. The rest of the configuration is the same as that of the first embodiment, so the description of the configuration here is omitted.

Next, the operation of the second embodiment will be described with reference to FIG. 9 showing a timing chart for explaining the operation.

First, the operation of the clock control circuit 87 and the clock control circuit 88 will be described. The latch 871 of the clock control circuit 87 outputs the latch control signal M4 to 1 at the falling timing of the L level of the internal clock signal CLK.
The AND872 receives the output signal J1 after shifting by 1/2 clock cycle and outputs the output signal J1. The AND872 receives, for example, four consecutive internal clock signals CLK within the period only when the output signal J1 is in the H level period. Is extracted and is output as the control clock signal K1 of the latch 82.

On the other hand, the OR circuit 8 of the clock control circuit 88
Reference numeral 81 extracts the H level of each of the write enable signal WE and the selector control signal SEL and outputs it to the latch 882 as a signal J3. The latch 882 receives the signal J at the falling timing of the internal clock signal CLK at the L level.
3 is shifted by 1/2 clock cycle and output signal J2
AND 883 which received this output signal J2
Extracts, for example, two continuous internal clock signals CLK within the period only when the output signal J2 is in the H level period, and also controls clock signal K2 of the latch 84.
Output as.

[0088] Next will be described the input and output circuits entire operation here taking into account the control clock signals K1 and K2 described above, input and output circuits of the read enable signal OE L
In response to the level, the input state is set, and the 3-state output buffer 85 is set to the high impedance state, so that the input / output terminal 10b is also set to the high impedance state.

Data D1, which is one clock cycle later, is input to the input / output dual-purpose terminal 10b in the high impedance state.
A data string of D2, D3, D4 is given and input to the latch 82 via the input buffer 81. The latch 82 is a control clock signal K supplied from the clock control circuit 87.
The data D1, D2, D3 and D4 are respectively latched in synchronization with 1, the latched held data are sequentially sent to the selector 83, and the final data D4 is held.
At this time, the input / output dual-purpose terminal 10b receives these data D
After receiving 1, D2, D3, and D4, respectively, the high impedance state is established again.

The selector 83 has a write enable signal W.
In response to the H level of the selector control signal SEL for one clock cycle period, only the data D4 given at the same clock timing as this H level is selected according to the truth table described above under the condition that E is at the L level. Then, the selected output signal SD is output to the latch 84. Latch 84
Synchronizes with the rising timing of the control clock signal K2 supplied from the clock control circuit 88, latches and holds the data D4 of the selection output signal SD, and outputs the data D4 to the I / O terminal 10b.

Next, when the read enable signal OE is inactivated and becomes H level, the 3-state output buffer 85 changes from a high impedance state to a signal output state and outputs the data D4 held in the latch 84. To do.

In this state, the write enable signal WE becomes 2
When the clock signal goes to the H level during the clock period, the selector 83 responds to the H level of the write enable signal WE during the two clock cycles according to the above truth table under the condition that the selector control signal SEL is at the L level. Only the output data D5, D6 of the internal circuit given at the same clock timing as the level are selected and output to the latch 84 as the selected output signal SD, and the input / output terminal 10 is also used.
Output to b.

The latch 84 synchronizes with the rising timing of each of the two clocks of the control clock signal K2 supplied from the clock control circuit 88, and outputs the selection output signal SD.
The data D5 and D6 are latched and held.

As described above, the clock signal control circuit 8
The input / output circuit using 7, 88 is a control clock signal K1.
Is the internal clock signal CLK when the signal M4 is at the H level.
The control clock signal K2 is output in synchronization with the internal clock signal when either the write enable signal WE or the selector control signal SEL is at the H level.

Therefore, the clock CL of the latches 82 and 84
The latch operation in synchronization with K can be minimized, and when the input / output circuit is in the output state and the write enable signal WE is at the H level, the latch 82 does not operate and outputs its output. Since the signal DI does not change, this embodiment has the effect of further reducing the current consumption.

Further, in the above-described second embodiment, the selector 8 corresponding to one input / output terminal is provided for each set of the control signal generator 86 and the clock signal control circuits 87, 88.
Three- and three-state output buffer 85, latches 82, 84
However, the control signal generator 86 and the clock signal control circuits 87 and 88 respectively correspond to a selector corresponding to a plurality of input / output terminals, a 3-state output buffer group, and latches 82 and 84. It may be configured to control the latch group that operates.

[0097]

As described above, in the input / output circuit of the present invention, the selector for selectively deriving the external input data or the output data of the internal circuit to the 3-state output buffer via the output side holding means. And an input / output circuit for controlling the selector selection operation and the output operation of the 3-state output buffer by a predetermined control signal, the selector selection operation and the 3-state output buffer output operation are controlled by different control signals, respectively. And a control signal generating means for controlling the three-state output buffer to be in a high-impedance state by one of the different control signals, and externally input to the three-state output buffer and the input / output terminal of the input buffer. When a continuous data string input as data is selected by the selector and held by the output side holding means Output side holding means at the time of input operation by generating the selector control signal of the selector and holding only the final data in the output side holding means only at the same clock timing as the last data output timing in the continuous data string The number of operations of the output side latch is suppressed, and when the external input data is derived to the output side holding means, the input side holding means is further provided between the input buffer connected to the input / output terminal and the selector. The output signal changes only once in synchronization with the same clock timing as the final data output timing, and the effect of reducing current consumption can be obtained.

For example, when data comes in continuously for 4 cycles, the number of changes of the output signal of the output side latch is changed from 4 times to 1
It can be reduced to 1/4 of the number of times, and likewise when data comes in 8 consecutive cycles, it can be reduced to 1/8. That is, it is possible to reduce the number of changes of the output signal of the output side latch when data is continuously received for n cycles to 1 / n, and to reduce the current consumption corresponding to that.

Further, the reduction of the current consumption leads to the reduction of the noise component, and at the same time, the effect of improving the reliability can be obtained.

Further, by providing the input side latch, the timing margin from the input / output terminal to the output side latch is improved by the delay of the selector and the wiring delay from the input buffer to the selector. Conventionally, the signal path from the input / output combined terminal to the output side latch is the input / output combined terminal → input buffer → selector →
Although it was an output side latch, in the input / output circuit of the present invention, by providing the input side latch, the input / output combined terminal becomes an input buffer → the input side latch. It is possible to obtain the effect that the timing margin is improved by the delay of the selector and the wiring delay from the input buffer to the selector.

Furthermore, when the output state of the input / output circuit of the present invention is used only for preventing the floating of the input / output terminal, the output data of the internal circuit and the write enable signal WE can be omitted. That is, the input / output circuit of the present invention can be used as a means for preventing the floating of the input / output combined terminal in the input circuit and contributes to the improvement of reliability.

Furthermore, even if the input side latch is not provided and the output signal of the input buffer is directly applied to the selector, the timing margin from the input / output terminal to the output side latch is not improved, but the current consumption is reduced. It is clear that this effect can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a system to which an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a control signal generator 116.

FIG. 4 is a diagram showing a truth table of the operation of the selector 113.

5 is a timing chart for explaining the operation of the system shown in FIG.

FIG. 6 is a timing chart for explaining the operation of the control signal generation circuit 116.

FIG. 7 is a timing chart for explaining the operation of the input / output circuit 11 of the first embodiment.

FIG. 8 is a block diagram showing a configuration of a second exemplary embodiment.

FIG. 9 is a timing chart for explaining the operation of the input / output circuit of the second embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional input / output circuit.

FIG. 11 is a timing chart for explaining the operation of the conventional input / output circuit.

[Explanation of symbols]

10, 10a, 10b, 100 Input / output terminal 11 Input / output circuit 12 Control circuit 13 Data generation circuit 101, 111, 81 Input buffer 112, 82 Input side latch 113, 83 Selector 114, 84 Output side latch 115, 85 3 states Output buffers 116, 86 of the control signal generators 1161-1163, 1165, 1168, 871, 8
82 latch 881 OR circuit 1166 inverter circuit 1167, 872, 883 AND circuit 87, 88 clock control circuit 1164 NOR circuit CLK internal clock signal DI output signal I1 input side latch output signal I1 input buffer output signal J1 latch 871 output signal J2 latch 882 Output signal J3 OR circuit 881 output signal K1 AND circuit 872 output signal K2 AND circuit 883 output signal M1 NOR circuit 1164 output signal M2 AND circuit 1167 output signal M3 latch 1161 output signal M4 latch 1162 output signal M5 output signal of latch 1163 N1 output data of internal circuit N2 data output control timing signal N3 data string control signal N4 data string MD mode setting signal OE read enable signal RD read request signal WE write enable Bull signal WR write request signal

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/00 G06F 3/00 G11C 11/34

Claims (14)

(57) [Claims] 1. A selector for selectively deriving external input data or output data of an internal circuit to a 3-state output buffer via an output side holding means, and a selecting operation of the selector by a predetermined control signal. And an input / output circuit for controlling the output operation of the 3-state output buffer, further comprising control signal generation means for controlling the selection operation of the selector and the output operation of the 3-state output buffer by different control signals. In the input state in which the three-state output buffer is in a high impedance state by one of the different control signals, the three-state output buffer and the input / output terminal of the input buffer are input as the external input data. When a continuous data string is selected by the selector and held by the output side holding means, Of the continuous data string, the selector control signal of the selector is generated only at the same clock timing as the last data output timing to hold only the final data in the output side holding means. An input / output circuit of a semiconductor device, characterized in that the number of operations of the output side holding means is suppressed. 2. The semiconductor device according to claim 1, further comprising an input side holding means provided between the selector and the input buffer connected to the input / output terminal when the external input data is derived to the output side holding means. The input / output circuit of the device. 3. The control signal generating means sets the selector control signal and the 3-state output buffer to a high impedance or output state in response to a first control signal input from the outside in synchronization with an internal clock signal. 2. The input / output of the semiconductor device according to claim 1, wherein the selector control signal is generated together with an enable signal, and the generation period of the selector control signal is included in a period in which the read enable signal is activated to the high impedance state. circuit. 4. The control signal generating means is pre-positioned in the 3-state output buffer by generating the selector control signal at least two cycles before the activation period of the read enable signal ends. In response to the selector control signal, the output side holding means latches the last data of the continuous data string externally input to the input / output terminal of the 3-state output buffer, and the latched final The input / output circuit of a semiconductor device according to claim 3, wherein the data is output to the input / output terminal. 5. The selector selects the output data of the internal circuit and holds the output data in the output side holding means when the predetermined write request signal and the selector control signal are at a high level, and the three-state output buffer. To the input / output terminal via the input / output terminal, and when the selector control signal is at the high level and the write request signal is at the low level, the input side holding provided between the input buffer connected to the input / output terminal and the selector is held. When the write request signal and the selector control signal are both at the low level, the output data of the input side holding means held by the output side holding means is changed to the high level by the selector control signal. The input / output circuit of a semiconductor device according to claim 1, which is maintained until the above. 6. The output side holding means responds to the high level of the selector control signal to hold the last data, and outputs the output data of the internal circuit in response to the high level of the write request signal. 2. The input / output circuit of a semiconductor device according to claim 1, wherein the input / output circuit is kept held until it is selected by the selector and read. 7. An input / output dual-purpose terminal, a 3-state output buffer which outputs output data of an internal circuit to the input / output dual-purpose terminal, and whose output state becomes a high impedance state by a predetermined control signal, and the high-level output buffer. An input buffer for inputting predetermined data from the input / output terminal in the impedance state; a first holding means for temporarily holding the output of the input buffer in synchronization with an internal clock signal;
The output of the holding means is received at a first input end, and the output data of the internal circuit is received at a second input end.
When the write request signal given to the external control circuit is at the active level, the control terminal of becomes high level for the clock cycle period designated by the set value m of the predetermined mode setting signal (m is a real number) A selector that receives a write enable signal for selectively outputting a column from the external control circuit, a selector output that is temporarily held in synchronization with the internal clock signal, and holding data is output to the 3-state output buffer. Second holding means for returning to the third input terminal of the selector; and a predetermined set value n (n is a real number) of the mode setting signal when the read request signal given to the external control circuit is at an active level. The data output timing control signal, which becomes active level only during the clock cycle period, is received from the external control circuit. On the other hand, one clock cycle is delayed from the transition timing of the data output timing control signal to the active level and at least 3 is longer than the active level period of the data output timing control signal.
A read enable signal that is activated for a clock cycle is generated to set the 3-state output buffer to the high impedance state, and the read enable signal is delayed by one clock cycle from the transition timing of the read enable signal to the active level. At the same clock timing as the n-th data of the n data strings output to the selector with a further delay of one clock cycle via the input / output terminal and the first holding means during the active level period of First control signal generating means for generating a selector control signal which becomes an active level only for one clock cycle to control the second control terminal of the selector to selectively output only the n-th data. Continuously input the data string of In this case, in response to the active level of the selector control signal, the selector is caused to control the selection of only the n-th data to reduce the number of changes in the output of the second holding means to 1 / n. An input / output circuit of a semiconductor device having a suppressing function. Wherein said first control signal generating means, said data output cascaded third timing control signal input in synchronization with said internal clock signal, the fourth and fifth
And holding means, these third, and NOR means taking the logic of the output signal and the data output timing control signals of the fourth and fifth holding means, said internal clock signal output of the NOR means logic that takes the logic of the generation means of a sixth the read enable signal comprising a holding means for holding synchronization, an output of the third polarity inverting output and the fourth retaining means of the output of the holding means to the semiconductor device according to claim 7 wherein the configuration at the first 7 <br/> generating means of said selector control signal consisting of a holding means for holding the product means the output of the logical product means in synchronization with said internal clock signal I / O circuit. 9. The synchronizing means of the first and second holding means are controlled by a first clock control means and a second clock control means, respectively, in place of the internal clock signal, and the first control is performed. Second control signal generating means is provided in place of the signal generating means, and the second control signal generating means outputs the data output timing control signal together with the read enable signal and the selector control signal for two cycles of the internal clock signal. The first clock control means further comprises an eighth holding means for holding the latch control signal in synchronization with the internal clock signal and an output signal of the eighth holding means. And a logical product means for extracting the internal clock signal,
The second clock control means includes a logical sum means for taking a logic of the write enable signal and the selector control signal, and a ninth holding means for holding an output signal of the logical sum means in synchronization with the internal clock signal. 8. An input / output circuit for a semiconductor device according to claim 7, wherein the input / output circuit comprises a logical product means for extracting the internal clock signal with an output signal of the ninth holding means. 10. The second holding means corresponding to the plurality of input / output terminals by one set each of the second control signal generation means, the first clock control means and the second clock control means. input-output circuit of a semiconductor device according to claim 9 wherein the common control each selector is preceded and said second holding means and the output buffer of the three-state to. 11. The first and second holding means operate only at a rising timing of a control clock signal output from the first clock control means and the second clock control means, and the other portions other than the above. 10. The input / output circuit of a semiconductor device according to claim 9, wherein the holding operation is suppressed during the internal clock signal period, and the current amount due to the holding operation in response to the internal clock signal is suppressed. 12. only the output signal of said first and said second holding means, an input signal of the selector <br/> click data prefix of the second holding means, selecting one of these two signals 10. The input / output circuit of the semiconductor device according to claim 7, wherein the 3-state output buffer that outputs the generated signal serves as a floating prevention unit for the input / output terminal. Wherein said selector is input-output circuit of a semiconductor device according to claim 7 or 9, wherein entering directly the data string input to the input-output terminal without passing through the first holding means. 14. The control circuit and the data generating circuit are formed on the same chip, or any one of them is formed.
10. The manufacturing method according to claim 7, wherein only one of them is formed on the same chip.
An input / output circuit of the described semiconductor device.