JP3468505B2 - Input/output circuit of semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to an input/output circuit, and more particularly to an input/output circuit which is connected to an input/output terminal of a semiconductor device and improves the timing margin from the input/output terminal to a latch circuit provided immediately before a three-state output buffer, thereby improving operating speed, power consumption and reliability.

[0002]

2. Description of the Related Art Conventional input/output circuits of this type are used particularly as input/output circuits connected to input/output terminals of semiconductor devices.

[0003] This input/output circuit generally comprises an input buffer which receives data supplied from the outside and supplies it to the internal circuit, and an output buffer which receives data output from the internal circuit and outputs it to the external circuit. Some output buffers function as a three-state output buffer, with output states being logically high level (hereinafter referred to as H level), low level (hereinafter referred to as L level), and an undefined high impedance state, and the input end of the input buffer and the output end of the output buffer are each commonly connected to a single input/output terminal.

In other words, one input/output terminal serves as both an input terminal and an output terminal so that when data is input, the three-state output buffer is placed in a high impedance state, and when data is output, the three-state output buffer outputs a binary signal of either H level or L level.

As mentioned above, the input/output circuit mediates the exchange of data with external circuits, but it also has the role of preventing unwanted noise from the outside and protecting the inside of the semiconductor device from electrostatic breakdown.

[0006] Such input/output circuits are usually built into semiconductor devices at the time of manufacture, and are required to have the functionality of inputting and outputting continuous data. Furthermore, they are required to be faster, consume less power, and be more reliable than conventional circuits.

One example disclosed to meet this demand is described in Japanese Patent Laid-Open Publication No. 60-170094. Referring to FIG. 10 showing the configuration of an input/output circuit described in the publication, this conventional input/output circuit has a common input/output terminal 100.
An input buffer 101 to which a signal is supplied from the outside via an input end of this terminal, and an output signal DI of the input buffer 101 is generated in response to the L level of an input/output switching control signal (read enable signal) OE from the output of this input buffer 101 and data N1 to be output from the internal circuit to the outside.
and selects the output data N1 of the internal circuit at a high level; a latch 103 that holds the selected signal SD; and a three-state output buffer 104 that outputs the output signal of the latch 103 to an input/output terminal 100.
It consists of 04.

This input/output circuit includes a common input/output terminal 100.
The data input to the input buffer 101 is connected to the selector 1
The data is latched in latch 103 via inputs 02 and 03, and when the operation state of input/output terminal 100 is switched to output operation, the latched data, i.e., the data that was input to input/output terminal 100 immediately before, is output, thereby preventing unnecessary changes in the input/output terminal.

[0009] Referring to Figure 11, which shows a timing chart for explaining the operation of the conventional input/output circuit described above, the output data N1 of the internal circuit outputs data D0 while the input/output circuit is in the input state, and the read enable signal OE provided to the selector 102 and the three-state output buffer 104 is set to L level for, for example, six clock periods, thereby putting the input/output circuit into the input state, and thereafter is returned to H level, putting it into the output state.

When the read enable signal OE goes low and the three-state output buffer 104 goes into a high impedance state, the I/O terminal 100 goes low after one clock.
Data D1, D2, D3, and D4 are input to and selected by a selector 102 via an input buffer 101. A latch 103 sequentially latches and holds this selected signal SD at the rising edge of the next internal clock signal.

When the read enable signal OE is inverted to H level, the selector 102 selects and outputs the output data N1 (D5, D6) of the internal circuit.
The latch 103 latches and holds the data D5, D6 at the rising edge of the next internal clock signal.
The signals D5, D6 are output to the input/output terminal 100 via a three-state output buffer 104.

In the figure, a high impedance period of one clock is provided before and after the data trains D1, D2, D3, and D4. This high impedance period is generally called a turnaround time, and is used for simultaneous activation of a three-state output buffer and external data at the input/output terminal,
In other words, it is generally defined as a specification to avoid bus fights (e.g. PCI, SDRAM
etc.).

[0013]

As will be apparent from a comparison of FIG. 2 showing the configuration of a first embodiment of the present invention described later with FIG. 7 showing its timing chart, the above-mentioned conventional input/output circuit is configured such that data input from the outside to an input/output terminal is selected by a selector in response to a read enable signal OE and output to a subsequent latch circuit.

Therefore, while the I/O terminal functions as an input terminal, the latch circuit also operates in response to changes in the input data, resulting in unnecessary power consumption. Moreover, unnecessary power consumption leads to an increase in noise components, which leads to a decrease in reliability.

Furthermore, since the input data is output directly to the selector via the input buffer, there is a problem in that an additional timing margin is required from the input/output terminal to the latch following the selector, including the delay of the selector and the wiring delay from the input buffer to the selector.

[0016] The object of the present invention has been made in consideration of the above-mentioned conventional drawbacks, and is to provide an extremely good input/output circuit which is faster, consumes less power and is highly reliable by selecting and latching the required data from a continuous data string input to an input/output terminal, thereby improving the timing margin from the input/output terminal to the latch following the selector.

[0017]

The input/output circuit of the present invention is characterized in that, in an input/output circuit having a selector for selectively directing external input data or output data of an internal circuit to a three-state output buffer via output side holding means, and which controls the selection operation of the selector and the output operation of the three-state output buffer with a prescribed control signal, the input/output circuit further has control signal generating means for controlling the selection operation of the selector and the output operation of the three-state output buffer with two different control signals, respectively, and when, in an input state in which the three-state output buffer is in a high impedance state with one of the two different control signals, a continuous data string input as the external input data to the input/output terminals of the three-state output buffer and input buffer is selected by the selector and held by the output side holding means, a selector control signal for the selector is generated only at the same clock timing as the output timing of the final data of the continuous data string, thereby causing the output side holding means to hold only the final data, thereby reducing the number of operations of the output side holding means during the input operation.

Furthermore, when the external input data is led to the output side holding means, an input side holding means can be further provided between the selector and an input buffer connected to the input/output terminal.

Furthermore, the control signal generating means generates the selector control signal and a read enable signal for placing the three-state output buffer in a high impedance or output state in response to a first control signal input from the outside in synchronization with the internal clock signal, and the period during which the selector control signal is generated is included in the period during which the read enable signal is activated to the high impedance state.

Furthermore, the control signal generating means can generate the selector control signal at least two cycles before the end of the activation period of the read enable signal, thereby causing the output side holding means located in front of the three-state output buffer to latch the final data of a continuous data string input from the outside to the input/output terminal of the three-state output buffer in response to the selector control signal, and output this latched final data to the input/output terminal.

[0021] Furthermore, when a predetermined write request signal and the selector control signal are at high level, the selector selects the output data of the internal circuit and holds it in the output side holding means, and outputs it to the input/output terminal via the three-state output buffer; when the selector control signal is at high level and the write request signal is at low level, the selector selects the output data of the input side holding means provided between the input buffer connected to the input/output terminal and the selector; and when the write request signal and the selector control signal are both at low level, the selector maintains the output data of the input side holding means held in the output side holding means until the selector control signal changes to high level.

[0022] Furthermore, the output side holding means can continue to hold the final data held in response to the high level of the selector control signal for a period until the output data of the internal circuit is selected and read by the selector in response to the high level of the write request signal.

Another feature of the input/output circuit of the semiconductor device of the present invention is that it has one input/output terminal and an output data of the internal circuit.
is output to the I/O terminal, and a predetermined control signal is
Three-state output where the output state is high impedance
an input buffer,
An input buffer that inputs the specified data from the output terminal
and synchronizing the output of the input buffer with the internal clock signal.
a first holding means for temporarily holding the first holding means;
A first input terminal receives the output of the stage, and a second input terminal receives
A first control terminal receives the output data of the internal circuit and
The write request signal is sent to the external control circuit.
The set value of the mode setting signal when it is at the active level
m (m is a real number) is the clock cycle period specified by
level, and the m data strings are selected and output.
The write enable signal is received from the external control circuit.
a selector for selecting an output of the selector and connecting the selected output to the internal clock
The data is temporarily held in synchronization with the clock signal and the held data is
The first input of the selector is output to the output buffer.
a second holding means for returning the signal to the input terminal of said external control circuit;
When the read request signal given to the path is at an active level,
At a predetermined mode setting signal setting value n (n is a real number),
Sets the active level for the specified clock cycle period.
The data output timing control signal is transmitted to the external control circuit.
the data output timing control signal is received from the
One clock cycle from the transition to the active level
delay and the activation of the data output timing control signal
At least three clock cycles longer than the active level period.
A read enable signal that is active for only
This generates a high impedance output for the three-state output buffer.
The read enable signal is set to a read-dance state.
One clock from the transition of the signal to the active level
Cycle delay and activation of the read enable signal
During a positive level period, the input/output terminal and the first
The holding means is further delayed by one clock cycle.
The nth data string among the n data strings output to the selector
The first data is read at the same clock timing as the second data.
A selector control signal is also generated, which makes only the
The second control terminal of the selector is controlled to generate the nth
A first control signal generating means for selectively outputting only the first data.
and inputting the n data strings consecutively.
When the selector control signal is
In response to the n-th data, the selector selects only the n-th data.
The number of changes in the output of the second holding means is controlled by selectively controlling the
The present invention has a function for suppressing current consumption to 1/n .

The first control signal generating means comprises third, fourth and fifth holding means connected in cascade for inputting the data output timing control signal in synchronization with the internal clock signal, NOR means for calculating the logic between the output signals of the third, fourth and fifth holding means and the data output timing control signal, and sixth holding means for holding the output of the NOR means in synchronization with the internal clock signal, and the selector control signal generating means comprises AND means for calculating the logic between the polarity inverted output of the output of the third holding means and the output of the fourth holding means, and seventh holding means for holding the output of the AND means in synchronization with the internal clock signal.
and a generating means for generating the signal.

[0025] Furthermore, the synchronization means of the first and second holding means may be controlled by a first clock control means and a second clock control means, respectively, instead of the internal clock signal, and a second control signal generating means may be provided instead of the first control signal generating means, and the second control signal generating means may further include a latch control signal which is the data output timing control signal shifted by two cycles of the internal clock signal, together with the read enable signal and the selector control signal, and the first clock control means may be composed of an eighth holding means which holds the latch control signal in synchronization with the internal clock signal and a logical product means which extracts the internal clock signal from the output signal of the eighth holding means, and the second clock control means may be composed of a logical sum means which takes the logic of the write enable signal and the selector control signal, a ninth holding means which holds the output signal of the logical sum means in synchronization with the internal clock signal, and a logical product means which extracts the internal clock signal from the output signal of the ninth holding means.

Furthermore, a set of the second control signal generating means, the first clock control means and the second clock control means is used to select a plurality of input/output terminals, which are provided in front of the second holding means.
The input/ output terminal, the second holding means and the three-state output buffer can be controlled in common.

[0027] Furthermore, the first and second holding means can operate only at the rising timing of the control clock signals output by the first clock control means and the second clock control means, and suppress the holding operation during other periods of the internal clock signal, thereby suppressing the amount of current due to the holding operation in response to the internal clock signal.

[0028] Furthermore, only the output signals of the first and second holding means can be used as input signals to a selector placed in front of the second holding means, and the three-state output buffer that outputs a signal selected from these two signals can be used as a floating prevention means for the input/output terminal.

[0029]

Furthermore , the selector can directly input the data string to be input to the input/output terminal without passing through the first holding means.

Furthermore , the control circuit and the data generating circuit may be formed on the same chip, or either one of them may be formed on the same chip.

[0032]

First, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a system configuration diagram to which a first embodiment of the present invention is applied. Referring to Fig. 1, a system using the input/output circuit of the present invention comprises an input/output circuit 11 of the present invention, and a write request signal WR (Write Request), a read request signal RD (Read Request), and a mode setting signal M (Mode Setting Signal) which are control signals generated by a predetermined signal generating circuit (not shown) as the system.
D (Mode) are input as control signals, and if the value of the mode setting signal MD is n (n is a real number) in response to the H level of the write request signal WR, the nth value of the internal clock signal is
Write enable signal WE at H level during the cycle
(Write Enable) and a read request signal RD
In response to the H level of the signal, the value of the mode setting signal MD becomes n
If so, the data output timing control signal N2 is set to H level for n cycles of the internal clock signal, and this signal is set to 1
The input/output circuit 11 is configured with a control circuit 12 which generates and outputs a data string control signal N3 shifted by one cycle, and a data generating circuit 13 which receives the data string control signal N3 and generates and outputs n consecutive data strings N4.
A write enable signal WE , a data output timing control signal N2, a data string N4, and output data N1 from the internal circuit are applied as input signals to this clock.

These may be formed on the same chip, or each may be formed as a separate chip, or only one of them may be formed as a separate chip.

On the other hand, referring to FIG. 2, which shows a block diagram of the input/output circuit 11 of the present invention, the input/output circuit 11 outputs an internal clock signal C in response to a data output timing control signal N2.
A control signal generator 116 is a first control signal generating means which generates a read enable signal OE for controlling a three-state output buffer at the same clock timing as the output timing of the last data of a data string N4 input in synchronization with the internal clock signal CLK, and also generates a selector control signal SEL for a selection means in synchronization with the internal clock signal CLK in response to a write enable signal WE. A shared input/output terminal 10 receives input signals from the data string N4 and other external circuits.
a, and an input buffer 111 which receives a data string N4 input to this terminal 10a or an input signal from an external circuit.
a latch 112 which is a first holding means for holding the input signal via the input buffer 111 in synchronization with a predetermined internal clock CLK; a selector 113 which is a selection means for selecting between the held data of the latch 112 and output data N1 of the internal circuit; a latch 114 which is a second holding means for holding the selected data output from the selector 113 in synchronization with the internal clock CLK; and a three-state buffer 115 which is connected between the latch 114 and the input/output terminal 10a and whose output state is controlled to high impedance by a read enable signal OE.

Referring to FIG. 3 showing the configuration of the control signal generator 116, the control signal generator 116 comprises latches 1161, 1162, 1163 which are third, fourth and fifth holding means connected in series and which input the data output timing control signal N2 in synchronization with the internal clock CLK.
Output signals M3, M4, and M5 of 61, 1162, and 1163
and the data output timing control signal N2, and a read enable signal OE generating means including a latch 1165 which is a sixth holding means for holding the output of the NOR circuit 1164 in synchronization with the internal clock CLK; and an output M3 of an inverter circuit 1166 which inverts the polarity of the output of the latch 1161.
B and the output M4 of the latch 1162, which is a logical product means, and this AND circuit 1167
and a generating means for generating a selector control signal SEL, which is a latch 1168 serving as seventh holding means for holding the output M2 of the selector 1161 in synchronization with the internal clock CLK.

4 showing a truth table of the operation of selector 113, when the input signals, write enable signal WE and selector control signal SEL, are "0" and "0", respectively, output SD selects and outputs output DO of latch 114, when they are "0" and "1", output SD selects and outputs output DI of latch 112, and when they are "1" and "0", output SD selects and outputs output data N1 of the internal circuit. The combination of "1" and "1" is a prohibited condition. Here, "0" indicates L level and "1" indicates H level.

1, the interrelationship between the input/output circuit 11, the control circuit 12 and the data generating circuit 13 of the present invention is as follows: the input/output circuit 11 of the present invention is controlled by a data output control timing signal N2 from the control circuit 12, and the timing control of the data string N4 of the data generating circuit 13 is also controlled by a data string control signal N3 input from the control circuit 12, and when the data string control signal N3 is at H level, the data generating circuit 13 outputs the data string N4.
The input/output circuit 11, the control circuit 12 and the data generating circuit 13 have in common that they operate in synchronization with the rising edge of the internal clock signal CLK.

That is, the control circuit 12 detects the H level of the read request signal RD, and as a result of the detection, if the data value of the mode setting signal MD is "4", the data output control timing signal N2 is set to H level for four cycles, and if the data value of the mode setting signal MD is "2", the data output control timing signal N2 is set to H level for two cycles.
Make it level.

Furthermore, when an H level of the write request signal WR is detected, if the data value of the mode setting signal MD is "4", the write enable signal WE is set to H level for a period of "4" cycles, and if the data value of the mode setting signal MD is "2", the write enable signal WE is set to H level for a period of 2 cycles.

On the other hand, the data string control signal N3 output from the control circuit 12 is generated by shifting the data output control timing signal N2 output from the control circuit 12 by one cycle.

The control circuit 12 and data generating circuit 13 which perform the above-mentioned operations can be easily realized by those skilled in the art, and as they are not directly related to the configuration of the present invention itself, a detailed description of their configuration will be omitted.

Next, the operation of the system shown in Fig. 1 will be described. Referring to Fig. 1, Fig. 5 showing a timing chart for explaining the operation, and Fig. 2 as well, it is assumed that the mode setting signal MD outputs a data value of "4" and the write request signal WR outputs an L level. At this time, when the read request signal RD goes to an H level, the data value of the mode setting signal MD is "4", so the control circuit 1
From clock 2, the data output control timing signal N2 is outputted at H level for four cycles in synchronization with the falling edge of the write request signal RD.

At this time, the data train control signal N3 is also outputted at H level for four cycles in a state where the data output control timing signal N2 is shifted by one cycle.

When the data output control timing signal N2 goes high, the input/output circuit 11 goes into an input state. When the data string control signal N3 goes high for four cycles, the data generating circuit 13 responds to the data string control signal N3 that is high for four cycles by generating data D1, D2, and D3 for four cycles from a timing shifted by one cycle from the rising edge of the data string control signal N3.
D3 and D4 are output as data string N4.

The input/output circuit 11 takes in these data D1, D2, D3, and D4 from the input/output terminal 10 as input data into the input buffer 111 in FIG.

Next, when the data string control signal N3 goes low after four cycles, the data generating circuit 13 also stops outputting the data D1, D2, D3, and D4 one cycle after the low-level timing in response to the low-level timing, and the potential of the input/output terminal 10 of the input/output circuit 11 goes into a high impedance state for two cycles from this end timing.
Assume that D has its data value reset to, for example, "2".

On the other hand, the data output control timing signal N2
In response to this going to the L level, the input/output circuit 11 goes into an output state and starts outputting predetermined data to the input/output terminal 10 .

When the input/output circuit 11 is in the output state, if the write request signal WR goes high, the control circuit 12 outputs the write enable signal WE one clock after the high-level rise timing. At this time, the data of the mode setting signal MD is "2".
Therefore, the write enable signal WE is outputted at H level for two cycles.

When the input/output circuit 11 is in an output state, if the write enable signal WE goes to H level, the input/output circuit 11 reads the output data N of the internal circuit one clock after the rising edge of the H level.
1 is output via the input/output terminal 10.

When the input/output circuit 11 is in the input state, the data D1, D2, and D3 at the input/output terminal 10 are
3. The high impedance period before and after the D4 input period is generally called a turnaround time, as described above.
It is generally defined as a standard for avoiding simultaneous activation of the output signal of .5 and the input data, i.e., a bus fight.

In this embodiment, the high impedance period after data input is two cycles longer than the one cycle of the conventional example, and this is to provide a skew between the change (D0→D4) of the output signal DO of the latch 114 and the rising edge of the read enable signal OE in Fig. 7, which will be described later. This is to prevent data D4 from being output to the input/output terminal 10 after data D0 has been output once, if the change of the output signal DO of the latch 114 and the rising edge of the read enable signal OE occur simultaneously.

Next, the operation of the input/output circuit 11 according to the first embodiment of the present invention will be described. First, the control signal generator 11
The operation of the control signal generator 16 will now be described.
6 which shows a timing chart for explaining the operation of the latch 1161, the data output control timing signal N2 which is at the H level for, for example, four cycles is latched by the latch 1161 in synchronization with the rising edge of the internal clock signal CLK, and the output of the latch 1161 is sequentially latched by the latches 1162 and 1163, whereby the data output control timing signal N2 is shifted by three cycles.
The output signal M1 of a NOR circuit 1164 having an output M4 of the latch 1162 and an output M5 of the latch 1163 as inputs is input to the latch 116
5, a read enable signal OE at the L level for seven cycles is generated.

On the other hand, an AND circuit 1167 receives an output signal M3B of an inverter circuit 1166, which receives the output M3 of the latch 1161 as an input, and an output M4 of the latch 1162 as an input.
The output signal M2 of the selector 1162 is shifted through a latch 1168 to generate the selector control signal SEL.

These data output control timing signals N
2, the read enable signal OE, and the selector control signal SE
Looking at the phase relationship with L, the falling timing of the read enable signal OE is shifted by one clock cycle with respect to the rising timing of the data output control timing signal N2, and the rising timing of the selector control signal SEL is shifted by five clock cycles with respect to the falling timing of the read enable signal OE, and both are synchronized with the internal clock signal CLK.

Next, the operation of the entire input/output circuit 11 will be described. Referring to Fig. 2 and Fig. 7 showing a timing chart for explaining the operation of the input/output circuit 11, it is assumed that the write enable signal WE is at L level. At this time, when the data output control timing signal N2 becomes H level for, for example, four clock cycles, in response to this H level, the data generating circuit 13 operates as described above to output the read enable signal OE which becomes L level for seven clock cycles from the timing one clock cycle after the rising edge of the data output control timing signal N2.

In response to the L level of the read enable signal OE, the three-state buffer 115 is deactivated, and the input/output terminal 10a is in a high impedance state and is in a state waiting for input data.

As described above, the data generating circuit 13 outputs the data D from the timing two clock cycles after the rising edge of the data output control timing signal N2.
Since 1, D2, D3, and D4 are output as data string N4, these data D1, D2, D3, and D4 are input to the input/output terminal 10a as continuous data of one cycle or more.

[0081] Data D 1 , D 2 , D 3 , and D 4 input to the input/output terminal 10 a are latched by the latch 112 via the input buffer 111 , shifted by one clock cycle, and input to the selector 113 .

At this time, since the write enable signal WE and the selector control signal SEL are both at L level according to the truth table of FIG. 4, the selector 113 selects and outputs the output of the subsequent latch 114, and the content held therein is data D0, which is the selector selection output when the previous selector control signal SEL was at H level.

The selector 113 receives the data D1, D2, and D
3. Four clock cycles after D4 is input (shifted by five clock cycles from the falling edge of the read enable signal OE), the selector control signal SEL rises to H level, and during this H level period the data D4 input to the selector 113 is selected and output, latched by the subsequent latch 114, shifted by one clock cycle, and output (output value D4 of the output signal DO of the latch 114).

That is, the clock timing at which data D4 is selected and the clock timing at which the selector control signal SEL rises to the H level are synchronized with the rising edge of the same clock.
Output timing of output value D4 and selector control signal SE
The falling timing of L is synchronized with the rising timing of the same clock.

The above-mentioned consecutive data D1, D2, D
The selector control signal SEL goes to H level in synchronization with the rising timing of the same clock with which the rising timing of the last data D4 of D3 and D4 is synchronized, and since the read enable signal OE is still at L level, the input/output terminal 10a, where the input of the data D1, D2, D3, and D4 has been completed, goes to a high impedance state again.

The high impedance state described above does not generally change the potential of the I/O terminal 10a, and the potential is maintained for a certain period of time (several milliseconds to several seconds) due to the parasitic capacitance of the I/O terminal 10a, etc.
In a high-speed system in which the clock cycle time is short (several nanoseconds to several microseconds), the potential of the I/O terminal 10a is maintained even when the terminal goes into a high impedance state.

Next, the read enable signal OE goes to H level, and the three-state buffer 115 is switched from the input state to the output state. The three-state buffer 115 is activated to the output state, and outputs the output signal DO of the latch 114 to the input/output terminal 10a. At this time, the last data D4 input to the input/output terminal 10a is
However, since the data is latched by the latch 114 and held as a signal DO and output, the input/output terminal 10a outputs data D4
The state is switched from the input state to the output state while maintaining the state.

When the read enable signal OE is at H level, the three-state buffer 115 is in the output state.
The three-state buffer 115 receives the output signal D of the latch 114.
Data D4, which is O, is output to the input/output terminal 10a.

At this time, the selector control signal SEL is already at L level, so if the write enable signal WE is at L level, the output signal DO (data D
4) is selected by the selector 113 as shown in the truth table of FIG.
The selected output signal SD is output from the selector 113 and input to the latch 114 .

The latch output is again input to the selector 113 for selection, so that even if the internal clock signal changes, the output signal SD of the selector 113 continues to output the same data D4, and the latch 11
Since the data D4 is also held by the input/output terminal 10a, the output signal DO does not change, and therefore the I/O terminal 10a does not change either.

Furthermore, since the selector control signal SEL is already at L level, if the write enable signal WE is at H level, as shown in the truth table of FIG. 4, the data D5 and D6 of the output signal N1 of the internal circuit are selected by the selector 113 and output as the selected output signal SD, and the latch 114
Through the three-state buffer 115, data D5 and D6 are output to the input/output terminal 10a.

In the above embodiment, the control circuit 12 generates the control signal for the input/output circuit of the present invention as an example of the system configuration.
It is also possible to generate signals corresponding to the data output control timing signal N2 and the data string control signal N3 from the data output control timing signal N3, and to use these signals to control the input/output circuit of the present invention.

That is, as described above, the control circuit 12
detects the H level of the read request signal RD, and as a result of the detection, if the data value of the mode setting signal MD is "4", the data output control timing signal N2 is set to the H level for four cycles, and if the data value of the mode setting signal MD is "2", the data output control timing signal N2 is set to the H level for two cycles. When the H level of the write request signal WR is detected, if the data value of the mode setting signal MD is "4", the write enable signal WE is set to the H level for four cycles, and
If the data value of is "2", the write enable signal WE
is set to H level for two cycles, and the control circuit 12
The data output control signal N3 is generated by shifting the data output control timing signal N2 output from the control circuit 12 by one cycle. The data generating circuit generates a signal so as to satisfy the above conditions.

[0071] In addition, in the above embodiment, one control signal generator 116 is configured to control the I/O terminal 10a, one selector 113, and three-state buffer 115, but it is also possible to configure one control signal generator 116 to control selectors and three-state buffers for a plurality of I/O terminals.

Furthermore, when the output state of the input/output circuit of the present invention is used only to prevent the input/output terminal from floating, the signal N1 and the write enable signal WE can be omitted.
Since it can also be used as a means for preventing floating of an input terminal in an input circuit, it is not necessary to provide a pull-up resistor or pull-down resistor to the input/output terminal.

As described above, the input/output circuit of the present invention is provided with a control signal generator 116, and is configured so that when the three-state buffer is in the input state, only the last data of any continuous cycle of a data string input to the input/output terminal 10a is captured by the latch 114. Therefore, the output signal DO of the latch 114 changes only once in synchronization with the same clock timing as the output timing of the last data, thereby achieving the effect of reducing current consumption.

For example, if data arrives for four consecutive cycles, the number of changes in the output signal DO of the latch 114 can be reduced to one quarter, from four to one. Similarly, if data arrives for eight consecutive cycles, the number of changes can be reduced to one eighth.

That is, when data arrives for n consecutive cycles, the number of changes in the signal DO can be reduced to 1/n, resulting in an effect of reducing current consumption.

Furthermore, the reduction in current consumption also leads to a reduction in noise components, which at the same time provides the effect of improving reliability.

Furthermore, by providing a latch 112 at the output of the input buffer 111, the timing margin from the input/output terminal 10a to the latch 114 is reduced by 10%.
13 and the delay due to the signal wiring from the input buffer 111 to the selector 113.

Conventionally, the input/output terminal 10a is connected to the latch 1
The signal path up to 14 was I/O terminal 10a → input buffer 111 → selector 113 → latch 114, but in the input/output circuit of the present invention, by providing latch 112 between input buffer 111 and selector 113, the signal path becomes I/O terminal 10a → input buffer 111 → latch 112. Therefore, the timing margin from I/O terminal 10a to latch 114 is reduced by 113.
and the wiring delay from the input buffer 111 to the selector 113.

Furthermore, even if the latch 112 is not provided and the wiring of the output signal I1 of the input buffer 111 and the output signal DI of the latch 112 are directly connected, the timing margin from the I/O terminal 10a to the latch 114 will not improve, but it is clear that the effect of reducing current consumption can be obtained.

Next, a second embodiment of the present invention will be described. The basic configuration is the same as that of the first embodiment, but:
The control of latch 112 and latch 114 is further devised.

[0081] Referring to Figure 8, which shows a block diagram of the configuration of the second embodiment, the differences from the first embodiment are that a clock signal control circuit 87 which provides an internal clock signal CLK to latch 82 ( corresponding to latch 112 in Figure 2 ) and a clock signal control circuit 88 which provides an internal clock signal CLK to latch 84 (corresponding to latch 114 in Figure 2 ) are newly provided, and further, a control signal generator 116 is configured to generate a signal M4 which controls the clock signal control circuit 88, thereby forming a control signal generator 86.

That is, the control signal generator 86 which is the second control signal generating means is equivalent to the control signal generator 116 shown in FIG. 2, but the read enable signal OE
and a latch control signal M4 (output signal M4 of latch 1162 in control signal generator 116 in FIG. 3 is used) which is obtained by shifting data output timing control data output control timing signal N2 by two cycles of internal clock signal CLK together with the selector control signal SEL.

[0083] The clock control circuit 87, which is the first clock control means, is composed of a latch 871, which is the eighth holding means that holds the latch control signal M4 in synchronization with the internal clock signal CLK, and an AND 872, which is a logical product means that extracts the internal clock signal CLK from the output signal of this latch 871.

The clock control circuit 88, which is the second clock control means, includes an OR circuit 881, which is a logical sum means for taking the logic of the write enable signal WE and the selector control signal SEL, a latch 882, which is a ninth holding means for holding an output signal J3 of the OR circuit 881 in synchronization with the internal clock signal CLK, and an output signal J2 of the latch 882.
2 and an AND 883 which is a logical multiplication means for extracting an internal clock signal CLK by the AND 883. The rest of the configuration is the same as in the first embodiment, so a description of the configuration will be omitted here.

Next, the operation of the second embodiment will be described with reference to FIG. 9 which shows a timing chart for explaining the operation.

First, the operations of the clock control circuits 87 and 88 will be described. The latch 871 of the clock control circuit 87 outputs the latch control signal M4 at the falling edge of the internal clock signal CLK to the L level.
1/2 clock cycle and outputs it as output signal J1. AND 872 receiving this output signal J1 extracts, for example, four consecutive internal clock signals CLK within the period when output signal J1 is at H level only, and outputs them as control clock signal K1 for latch 82.

On the other hand, the OR circuit 8 of the clock control circuit 88
The latch 881 extracts the H levels of the write enable signal WE and the selector control signal SEL and outputs them as a signal J3 to the latch 882. The latch 882 outputs the signal J3 at the falling edge of the internal clock signal CLK to the L level.
3 is shifted by 1/2 clock cycle to output signal J2
The AND883 receives the output signal J2 as
extracts, for example, two consecutive internal clock signals CLK within the period when the output signal J2 is at H level only, and outputs the control clock signal K2 of the latch 84.
The output is as follows:

Next, the operation of the entire input/output circuit will be described with consideration given to the above-mentioned control clock signals K1 and K2. The input/output circuit operates in accordance with the L level of the read enable signal OE.
In response to the level, the input state is reached, and the three-state output buffer 85 is set to a high impedance state, so that the I/O terminal 10b is also set to a high impedance state.

After one clock cycle, data D1,
A data sequence of D2, D3, and D4 is given and input to a latch 82 via an input buffer 81. The latch 82 receives a control clock signal K
In synchronization with clock 1, data D1, D2, D3, and D4 are latched, and the latched data are sequentially sent to selector 83 while the final data D4 is held.
At this time, the input/output terminal 10b receives these data D
After receiving D1, D2, D3, and D4, respectively, the input becomes high impedance again.

The selector 83 receives the write enable signal W
Under the condition that E is at the L level, according to the truth table described above, in response to the H level of the selector control signal SEL for one clock cycle period, only data D4 applied at the same clock timing as this H level is selected and output to the latch 84 as the selection output signal SD.
In synchronization with the rising edge of the control clock signal K2 applied from the clock control circuit 88, latches and holds the data D4 of the selection output signal SD and outputs it to the input/output terminal 10b.

Next, when the read enable signal OE is deactivated and goes to the H level, the three-state output buffer 85 goes from the high impedance state to a signal output state, and outputs the data D 4 held in the latch 84 .

In this state, the write enable signal WE is
When the selector control signal SEL is at the H level for the clock period, the selector 83 responds to the H level of the write enable signal WE for two clock cycle periods according to the truth table described above under the condition that the selector control signal SEL is at the L level, selects only the output data D5, D6 of the internal circuit provided at the same clock timing as this H level, and outputs it to the latch 84 as the selected output signal SD, and also outputs it to the input/output terminal 10.
The output is sent to b.

The latch 84 outputs the selection output signal SD in synchronization with the rising edge of each of the two clocks of the control clock signal K2 provided by the clock control circuit 88.
The data D5 and D6 are latched and held.

As described above, the clock signal control circuit 8
The input/output circuit using 7 and 88 is a control clock signal K1
When the signal M4 is at H level, the internal clock signal CLK
The control clock signal K2 is output in synchronization with the internal clock signal when either the write enable signal WE or the selector control signal SEL is at H level.

Therefore, the clock CL of the latches 82 and 84
Since the number of latch operations synchronized with K can be minimized, and when the input/output circuit is in the output state and the write enable signal WE is at H level, the latch 82 does not operate and the output signal DI does not change, the present embodiment has the effect of further reducing current consumption.

In the second embodiment described above, each of the control signal generator 86 and the clock signal control circuits 87 and 88 corresponds to one input/output terminal.
3. Three-state output buffer 85, latches 82, 84
However, a configuration in which a control signal generator 86 and clock signal control circuits 87 and 88 each control a selector corresponding to a plurality of input/output terminals, a group of three-state output buffers, and a group of latches corresponding to the latches 82 and 84 may also be used.

[0097]

As described above, the input/output circuit of the present invention has a selector for selectively deriving external input data or output data of an internal circuit to a three-state output buffer via output side holding means, and the input/output circuit controls the selection operation of the selector and the output operation of the three-state output buffer with a predetermined control signal, and further has control signal generating means for controlling the selection operation of the selector and the output operation of the three-state output buffer with different control signals, and when the three-state output buffer is in an input state where one of the different control signals causes the three-state output buffer to be in a high impedance state, the input data is input as external input data to the input/output terminals of the three-state output buffer and input buffer. When a continuous data string inputted is selected by the selector and held in the output side holding means, a selector control signal for the selector is generated only at the same clock timing as the output timing of the final data of the continuous data string, causing the output side holding means to hold only the final data, thereby reducing the number of operations of the output side holding means during input operation, and since an input side holding means is further provided between the input buffer connected to the input/output terminal and the selector when external input data is led to the output side holding means, the output signal of the output side latch changes only once in synchronization with the same clock timing as the output timing of the final data, thereby achieving the effect of reducing current consumption.

For example, if data arrives for four consecutive cycles, the number of changes in the output signal of the output side latch is reduced from four to one.
In other words, when data arrives for n consecutive cycles, the number of changes in the output signal of the output side latch can be reduced to one-n, resulting in an effect of reducing current consumption by the same amount.

Furthermore, the reduction in current consumption also leads to a reduction in noise components, which at the same time provides the effect of improving reliability.

Furthermore, by providing the input side latch, the timing margin from the input/output terminal to the output side latch is improved by the delay of the selector and the wiring delay from the input buffer to the selector. Conventionally, the signal path from the input/output terminal to the output side latch is the input/output terminal→input buffer→selector→
Previously, it was an output side latch, but in the input/output circuit of the present invention, by providing an input side latch, the order becomes I/O dual-purpose output terminal → input buffer → input side latch, and therefore, the effect is obtained that the timing margin from the I/O dual-purpose terminal to the output side latch is improved by the delay of the selector and the wiring delay from the input buffer to the selector.

Furthermore, when the output state of the input/output circuit of the present invention is used only to prevent the input/output terminal from floating, the output data of the internal circuit and the write enable signal WE can be omitted. In other words, the input/output circuit of the present invention can also be used as a means for preventing the input/output terminal in the input circuit from floating, which contributes to improving reliability.

Furthermore, even if an input side latch is not provided and the output signal of the input buffer is directly fed to the selector, the timing margin from the input/output terminal to the output side latch is not improved, but it is clear that the effect of reducing current consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a system to which an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a control signal generator 116.

FIG. 4 is a truth table of the operation of a selector 113.

5 is a timing chart for explaining the operation of the system shown in FIG. 1.

6 is a timing chart illustrating the operation of the control signal generating circuit 116. FIG.

FIG. 7 is a timing chart illustrating the operation of the input/output circuit 11 according to the first embodiment.

FIG. 8 is a block diagram showing a configuration of a second embodiment.

FIG. 9 is a timing chart illustrating the operation of the input/output circuit according to the second embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional input/output circuit.

FIG. 11 is a timing chart illustrating the operation of a conventional input/output circuit.

[Explanation of symbols]

10, 10a, 10b, 100 Input/output shared terminal 11 Input/output circuit 12 Control circuit 13 Data generation circuit 101, 111, 81 Input buffer 112, 82 Input side latch 113, 83 Selector 114, 84 Output side latch 115, 85 Three-state output buffer 116, 86 Control signal generator 1161 to 1163, 1165, 1168, 871, 8
82 Latch 881 OR circuit 1166 Inverter circuits 1167, 872, 883 AND circuits 87, 88 Clock control circuit 1164 NOR circuit CLK Internal clock signal DI Output signal I1 of input side latch Output signal J1 of input buffer Output signal J2 of latch 871 Output signal J3 of latch 882 Output signal K1 of OR circuit 881 Output signal K2 of AND circuit 872 Output signal M1 of AND circuit 883 Output signal M2 of NOR circuit 1164 Output signal M3 of AND circuit 1167 Output signal M4 of latch 1161 Output signal M5 of latch 1162 Output signal N1 of latch 1163 Output data N2 of internal circuit Data output control timing signal N3 Data string control signal N4 Data string MD Mode setting signal OE Read enable signal RD Read request signal WE Write enable signal WR Write request signal

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Claims (14)

(57) [Claims] [Claim 1] An input/output circuit for a semiconductor device having a selector for selectively directing external input data or output data of an internal circuit to a three-state output buffer via an output side holding means, and which controls the selection operation of the selector and the output operation of the three-state output buffer with a predetermined control signal, further comprising control signal generating means for controlling the selection operation of the selector and the output operation of the three-state output buffer with different control signals, wherein, in an input state in which one of the different control signals causes the three-state output buffer to be in a high impedance state, when a continuous data string input as the external input data to the input/output terminals of the three-state output buffer and input buffer is selected by the selector and held in the output side holding means, a selector control signal for the selector is generated only at the same clock timing as the output timing of the final data in the continuous data string, thereby causing only the final data to be held in the output side holding means, thereby suppressing the number of operations of the output side holding means during the input operation. 2. The input/output circuit of claim 1, further comprising an input side holding means provided between said selector and an input buffer connected to said input/output terminal when said external input data is delivered to said output side holding means. [Claim 3] The input/output circuit of a semiconductor device as described in claim 1, wherein the control signal generating means generates the selector control signal and a read enable signal that places the three-state output buffer in a high impedance or output state in response to a first control signal input from outside in synchronization with an internal clock signal, and the period during which the selector control signal is generated is included in the period during which the read enable signal is activated to the high impedance state. [Claim 4] An input/output circuit for a semiconductor device as described in claim 3, wherein the control signal generating means generates the selector control signal at least two cycles before the end of the activation period of the read enable signal, thereby causing an output side holding means located in front of the three-state output buffer to latch the final data of a consecutive data string input from outside to the input/output terminal of the three-state output buffer in response to the selector control signal, and outputs this latched final data to the input/output terminal. [Claim 5] An input/output circuit for a semiconductor device as described in claim 1, wherein when a predetermined write request signal and the selector control signal are at high level, the selector selects output data of the internal circuit and holds it in the output side holding means, and outputs it to the input/output terminal via the three-state output buffer, when the selector control signal is at high level and the write request signal is at low level, the selector selects output data of the input side holding means provided between the input buffer connected to the input/output terminal and the selector, and when the write request signal and the selector control signal are both at low level, the input data of the input side holding means held in the output side holding means is maintained until the selector control signal changes to high level. [Claim 6] An input/output circuit for a semiconductor device as described in claim 1, wherein the output side holding means continues to hold the final data held in response to the high level of the selector control signal for a period until the output data of the internal circuit is selected and read by the selector in response to the high level of the write request signal. 7. A device comprising: an input/output terminal; a three-state output buffer for outputting output data of an internal circuit to said input/output terminal and for changing an output state to a high impedance state in response to a predetermined control signal; an input buffer for inputting predetermined data from said input/output terminal in said high impedance state; first holding means for temporarily holding an output of said input buffer in synchronization with an internal clock signal;
a first input terminal for receiving the output of the holding means, and a second input terminal for receiving the output data of the internal circuit;
the control terminal of the second input terminal of the third ...
and first control signal generating means for generating a read enable signal which becomes active for one clock cycle longer to put the three-state output buffer into the high impedance state, and for generating a selector control signal which becomes active for one clock cycle at the same clock timing as the nth data of the n data strings which is output to the selector one clock cycle later than the transition timing of the read enable signal to the active level and further one clock cycle later during the active level period of the read enable signal via the input/output terminal and the first holding means, to control a second control terminal of the selector to select and output only the nth data, and having a current consumption suppression function which reduces the number of changes in the output of the second holding means to one-nth when the n data strings are continuously input by causing the selector to select and control only the nth data in response to the active level of the selector control signal. 8. The first control signal generating means comprises third, fourth and fifth cascaded control signals which input the data output timing control signal in synchronization with the internal clock signal.
the read enable signal generating means comprising holding means for generating a read enable signal, a negative OR means for calculating the logic between the output signals of the third, fourth and fifth holding means and the data output timing control signal, and a sixth holding means for holding the output of the negative OR means in synchronization with the internal clock signal; and the selector control signal generating means, comprising a logical AND means for calculating the logic between the polarity inverted output of the output of the third holding means and the output of the fourth holding means, and a seventh holding means for holding the output of the logical AND means in synchronization with the internal clock signal. 9. A clock control circuit for controlling the synchronization means of said first and second holding means by first and second clock control means, respectively, instead of said internal clock signal, and a second control signal generating means is provided instead of said first control signal generating means, said second control signal generating means further comprising a latch control signal obtained by shifting said data output timing control signal by two cycles of said internal clock signal together with said read enable signal and said selector control signal, said first clock control means comprising an eighth holding means for holding the latch control signal in synchronization with said internal clock signal, and a logical AND means for extracting said internal clock signal from an output signal of said eighth holding means,
8. The input/output circuit of a semiconductor device according to claim 7, wherein said second clock control means comprises: logical sum means for calculating a logic of said write enable signal and said selector control signal; ninth holding means for holding an output signal of said logical sum means in synchronization with said internal clock signal; and logical product means for extracting said internal clock signal from the output signal of said ninth holding means. [Claim 10] An input/output circuit for a semiconductor device as described in claim 9, wherein a set of the second control signal generating means, the first clock control means and the second clock control means each commonly controls a selector placed in front of the second holding means, the second holding means and the three-state output buffer corresponding to a plurality of the input/output terminals. [Claim 11] An input/output circuit for a semiconductor device as described in claim 9, wherein the first and second holding means operate only at the rising timing of the control clock signals output by the first clock control means and the second clock control means, and suppress the holding operation during other periods of the internal clock signal, thereby suppressing the amount of current due to the holding operation in response to the internal clock signal. [Claim 12] An input/output circuit of a semiconductor device as described in claim 7 or 9, wherein only the output signals of the first and second holding means are input signals to a selector placed in front of the second holding means, and the three-state output buffer that outputs a signal selected from these two signals is used as a floating prevention means for the input/output terminal. 13. The input/output circuit of a semiconductor device according to claim 7, wherein said selector directly inputs said data string to be input to said input/output terminal without passing through said first holding means. 14. The control circuit and the data generating circuit are formed on the same chip, or either one of them is formed on the same chip.
10. The method according to claim 7 or 9, wherein only one of the plurality of the first and second semiconductor devices is formed on the same chip.
An input/output circuit of the semiconductor device described above.