KR100546272B1 - Data input circuit using data strobe signal - Google Patents

Abstract

A data input circuit of a synchronous semiconductor memory device for synchronizing data input with a data strobe signal to a clock is described. The data input circuit according to the present invention includes a plurality of data input signals which are alternately outputted in response to data strobe signals and buffer stage control signals which are input at the same time as the data input time and serve as a clock for sampling data. In response to buffer stages and synchronous stage control signals, output data of the buffer stages are output in synchronization with an internal clock, and a plurality of synchronous stages connected to a common data input line and the outputs are provided. Therefore, the operation speed of the synchronous semiconductor memory device is improved by excluding the influence of the time required from the clock to the data output and the time required for the data to fly from the memory to the controller.

Description

Data input circuit using data strobe signal

The present invention relates to a synchronous semiconductor memory device, and more particularly, to a data input circuit of a semiconductor memory device using a data strobe signal.

Computer systems generally have a central processing unit (hereinafter referred to as a CPU) for executing instructions for given tasks and a main memory for storing data, programs, and the like required by the CPU. Therefore, in order to improve the performance of a computer system, it is required to increase the operating speed of the CPU and to make the access time to the main memory as short as possible by operating the CPU without waiting time. In response to such demands, a synchronous DRAM (hereinafter referred to as SDRAM), which operates under the control of the system clock and has a very short access time to main memory, has emerged.

Typically, the SDRAM is controlled in response to a pulse signal generated by the transition of the system clock. In such a synchronous semiconductor memory device operating in synchronization with a clock, the clock cycle time (CLOCK CYCLE TIME, hereinafter tCC) is limited by various factors.

That is, tCC is a difference between the time required for the clock input to the memory and the data controller (hereinafter referred to as tSW), the time required for the clock to output the data (DATA ACCESS TIME, tAC), and the data required for flight from the memory to the controller. It is determined by the sum of the time (hereinafter referred to as tFL) and the data set-up time (hereinafter referred to as tSS) in the controller.

1 is a timing diagram showing various time required for limiting tCC in the prior art. Here, CLK_SYS is the waveform of the system clock, CLK_CNTR is the waveform of the clock input to the controller, CLK_DRAM is the waveform of the clock input to the DRAM, DATA_DRAM is the data output from the DRAM, and DATA_CNTR is the data received from the controller. Represent each.

Referring to this, in the system, tCC is limited to be equal to or more than the sum of tSW, tAC, tFL, and tSS. Therefore, it was not possible to realize an SDRAM having a frequency of 300 MHz or more with a conventional data input / output circuit.

As a solution to this problem, a method of using a data strobe (DS) signal having a clock form has been proposed. This is because the DS signal is transmitted along with the data through the data strobe line having the same system load as the data line when transferring data between the memory and the controller, and the controller receives the data using the DS signal. Offset elements that limit the same system clock. Therefore, it becomes possible to use a system clock having a higher operating frequency than when not using a DS signal.

As described above, in the system using the DS signal, the data is received in synchronization with the DS signal, and therefore, it is essential to synchronize the input data with the system clock again. In addition, since a double data rate (DDR) technology for inputting and outputting data at rising and falling edges of a clock used in a memory device is becoming more common, a DS signal is used and DDR or higher data is used. There is an increasing demand for input buffers that have a rate and that data can be continuously input.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a data input circuit of a synchronous semiconductor memory device for synchronizing data input with a data strobe signal to a clock.

In order to achieve the above object, the data input circuit according to the present invention receives data input in response to a data strobe signal and a buffer stage control signal which are input at the same time as the data input time and serve as a clock for sampling data. A plurality of buffer stages alternately output and a plurality of synchronization stages for synchronizing the output data of the buffer stages with an internal clock in response to the synchronization stage control signals, and having a common data input line and the outputs connected thereto. .

The data input circuit may further include a buffer stage control circuit for inputting a data strobe signal converted to a CMOS level and generating buffer stage control signals having different phases by the number of buffer stages within a section in which a write operation is permitted; A synchronous stage control circuit for generating the synchronous stage control signals for inputting the buffer stage control signals and synchronizing them to an internal clock is provided within an allowed operation period.

The buffer stage control signals outputted through the buffer stage control circuit change their logic states whenever the data strobe signal switched to the CMOS level transitions to a high level.

Preferably, the buffer stages are connected in parallel as many times as the number of data inputted during one clock cycle. Each of the buffer stages includes: an AND function for performing an AND operation on a buffer stage control signal and a data strobe signal, and an output of the AND product. It is controlled by a plurality of transmission means for transmitting the input data and a plurality of latch means for storing the output of the transmission means for a predetermined time.

Each of the synchronization stages may include a NAND gate for inputting a synchronous stage control signal and an internal clock, at least one transfer means controlled by an output of the NAND gate to transfer output data of the buffer stage, and the transfer means. At least one latch means for storing the output for a certain time.

As described above, according to the present invention, it is effectively operated even when data is input together with a data strobe signal and data is input with a DDR or higher data rate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, the same reference numerals and numerals indicate the same circuit for each drawing.

FIG. 2 is a block diagram of a data input circuit according to an embodiment of the present invention, and will be described by taking an example in which data is input at a double data rate (DDR).

As shown in FIG. 2, an input buffer circuit according to an embodiment of the present invention includes a DS switching unit 10 which receives a DS signal input at a TTL level and converts the signal into a CMOS level, and the DS switching unit 10. A delay circuit 15 for delaying and outputting a signal outputted from a predetermined time period, a DIN switching unit 20 for receiving data DIN input at a TTL level and converting the signal to a CMOS level signal, and the DS switching unit 10. A synchronization stage synchronized with the internal clock PCLK by inputting the buffer stage control circuit 30 to generate the buffer stage control signals PDSEN1 and PDSEN2 by inputting an output signal of the control circuit 30 and the buffer stage control signals PDSEN1 and PDSEN2. A synchronization stage control circuit 40 for generating control signals PCLKEN1 and PCLKEN2 is provided.

The input buffer circuit according to the present invention also alternately alternates the data PDINT output from the DIN switching section 20 in response to the buffer stage control signals PDSEN1 and PDSEN2 and the delay circuit output signal PDSD. A plurality of outputting buffer stages, for example, the first and second buffer stages 50 and 60 and the synchronization stage control signals PCLKEN1 and PPCLKEN2, from the first and second buffer stages 50 and 60. A plurality of synchronization stages, for example, first and second synchronization stages 50 and 60, outputting the output data in synchronization with the internal clock PCLK.

The DS switching unit 10 outputs a DS signal serving as a clock for sampling data as a CMOS level signal PDS, and the DIN switching unit 20 outputs input data DI to a CMOS level signal ( PDINT).

The buffer stage control circuit 30 inputs a PDS signal output from the DS switching unit 10 to determine which one of the first and second buffer stages 50 and 60 determines whether the PDSD signal is input to the buffer stage. Generate control signals PDSEN1 and PDSEN2. The buffer stage control signals PDSEN1 and PDSEN2 alternately operate the first and second buffer stages 50 and 60.

The synchronous stage control circuit 40 may also output the synchronous stage control signals PCLKEN1 and PCLKEN2 in response to the buffer stage control signals PDSEN1 and PDSEN2 and the internal clock PCLK output from the buffer stage control circuit 30. Occurs.

Each of the first buffer stage and the second buffer stage 50 and 60 may include a signal PDSD, from which an external DS signal is converted to a CMOS level and delayed for a predetermined time, and buffer stage control signals PDSEN1 and outputted from the buffer stage control circuit. In response to PDSEN2), data PDINT switched to the CMOS level is alternately output. At this time, the data PDINT input to each of the buffer stages 50 and 60 are divided into even-numbered and odd-numbered data and provided to the output nodes NF1_E, NF1_O, NF2_E, and NF2_O.

According to the present invention, it is preferable that a number of buffer stages corresponding to the number of data input for one clock period are connected in parallel. For example, when data is input at the rising edge and the falling edge of the clock as in the present embodiment, it is preferable that two buffer stages are formed, that is, the first and second buffer stages 50 and 60.

The synchronization stages 70 and 80 synchronize the output data of the buffer stages to the internal clock PCLK in response to the synchronization stage control signals PCLKEN1 and PCLKEN2 to common data input lines DI_E and DI_O. to provide. Preferably, the sync stages are configured to have the same number as the buffer stages, and each output is connected to a common data input line.

3A and 3B are timing diagrams of signals used in the data input circuit shown in FIG. 2, and FIG. 3A shows a case in which a time difference between a clock and a DS signal (hereinafter, referred to as tDSS) is 0.5 CLK. The case is given as an example, and in both cases the write latency is set to two.

3A and 3B, the DS signal is input by being delayed by tDSS with respect to the clock CLK to which the write command WD is input. In this case, the center of the input data DIN is located at the rising edge or the falling edge of the DS signal.

The DS signal input through the DS switching unit (10 in FIG. 2) is input together with DIN and maintains a high impedance level in the standby mode. This is to reduce the standby current consumption caused by the formation of a current path between the DS line and the voltage source on the system when the DS signal remains high or low in standby mode. In addition, when the DS signal transitions directly from the high impedance level to the "high" level during data transmission, the waveform of the DS signal receiving the first data DO_E and the third data D1_E is changed. This change in waveform causes a difference in set up and hold time of the data. To prevent this, the DS signal is preferably configured to maintain a "low" level before one cycle before the first data is input, as shown.

The write master signal PWR is a signal that is activated in response to the write command WD and maintains a "high" state during the write operation. In this embodiment, since the write latency is 2 as an example, two clocks after the data write is completed are completed. It remains "high" during the cycle.

The buffer stage control signals PDSEN1 and PDSEN2 are generated in response to the signal PDS output through the DS switching unit 10 of FIG. 2. The signal PDSD output through the delay circuit 15 of FIG. 2 is a signal in which the DS switching unit output signal PDS is delayed for a predetermined time and is input to the first and second buffer stages 50 and 60.

The buffer stage control signals PDSEN1 and PDSEN2 determine which of the two buffer stages the PDSD signal is input to. Among the two buffer stages shown in FIG. 2, the PSDEN1 and the PDSEN2 maintain the low level when the PWR is low and then the PWR transitions high. PDSEN2 goes high, ready for operation. Subsequently, in response to the PDS signal transitioning high while the PWR signal is high, PDSEN1 transitions high and PDSEN2 transitions low, thereby activating the first buffer stage 30 so that the PDSD and PDINT signals It is input to the first buffer stage 30 and stored. When the PDS signal goes low and transitions high again, as shown, PDSEN1 goes low and PDSEN2 goes high. That is, whenever PDS goes high, PDSEN1 and PDSEN2 are toggled, and when the PWR signal goes low, both PDSEN1 and PDSEN2 go low.

The synchronization stage control signals PCLKEN1 and PCLKEN2 are signals in which the PDSEN1 and PDSEN2 signals are synchronized with the falling edge of the internal clock PCLK while the PWR signal maintains the high level.

The output signals DI_E and DI_O of the input buffer circuit output data in response to the rising edge of the internal clock PCLK.

FIG. 4 is a detailed circuit diagram of the first buffer stage 50, the second buffer stage 60, the first synchronization stage 70, and the second synchronization stage 80 shown in FIG. 2.

As shown in FIG. 4, each of the buffer stages, that is, the first buffer stage 50 and the second buffer stage 60, according to a preferred embodiment of the present invention has basically the same configuration. Similarly, the first synchronizing stage 70 and the second synchronizing stage 80 also have basically the same configuration. Therefore, the embodiment described below will be described based on the configuration and operation of the first buffer stage 50 and the first synchronization stage 70, and the second buffer stage 60 and the second synchronization stage 80 are thus described. It will be well understood to those skilled in the art having a similar configuration and operation.

First, the first buffer stage 50 is controlled by the logical product means 54 for ANDing the buffer stage control signal PSDEN1 and the PDSD signal, and the output of the logical product means 54 to transmit the input data. A plurality of transmission means (51a, 51b, 51c, 51d, 51e) and a plurality of latch means (52a, 52b, 52c, 52d, 52e) for storing the output of the transmission means for a predetermined time. The first buffer stage 50 further includes a plurality of inverting means 53a, 53b, 53c for delaying the input data PDINT for a predetermined time.

The transmission means 51a, 51b, 51c, 51d, 51e and the latch means 52a, 52b, 52c, 52d, 52e are configured in two stages to separate and output the even and odd numbers of the input data. It is preferable. For example, 51a, 51b, 51c and 52a, 52b and 52c of the transmission means and the latch means are configured in parallel to transmit even-numbered data and 51d, 51e and 52d and 52e to transmit odd-numbered data.

The switching means 51a, 51d located at the beginning of the first and second columns of the switching means are alternately " on " according to the PDSEN1 signal and the PDSD signal, so that the inverting means 53a, 53b, 53d. The data signal PDINT, which is input through the data, is transmitted to the latch means. The latch means 52a, 52d next to the switching means 51a, 51d mentioned are the even-numbered data and the odd-numbered data PDINT input during the time when the switching means 51a, 51d are 'on'. Save it.

For example, when PDSEN1 is high level and PDSD is low level, first input data is first stored in the latch means 52a through the switching means 51a of the first column. Subsequently, when the PDSD transitions to the high level so that both inputs of the OR block 54 are at the high level, the second switching means 51b in the first column and the first switching means 51d in the second column are “on”. do. Therefore, the first data stored in the first latch means 52a of the first column is transmitted to and stored in the second latch means 52b, and the second input second data is the first latch means 52d of the second column. Are stored in. Next, when the PDSD becomes logic low again, the third switching means 51c of the first column and the second switching means 51e of the second column are “on”, and the first data is the third latching means 52c of the first column. ), And the second data is stored in the second latch means 52e of the second column.

That is, while PDSEN1 is high, even-numbered data D0_E is provided when PDSD goes high, and odd-numbered data D0_O is provided to two output nodes NF1_E and NF1_O of first buffer stage 50 when PDSD goes low. Similarly, while PDSEN2 is high, even-numbered data D1_E is provided when PDSD goes high, and odd-numbered data D1_O is provided to two output nodes NF2_E and NF2_O of the second buffer stage when PDSD goes low.

The first synchronization stage 70 is controlled by the NAND gate 73 for inputting the synchronization stage control signal PCLKEN1 and the internal clock PCLK, and the output of the NAND gate. At least one transmission means for transmitting the output data of, for example, two transmission means (71, 72) and at least one latch means for storing the output of said transmission means, for example two latch means (74, 75) ).

Each of the transmission means 71 and 72 is transmitted from the output nodes NF1_E and NF1_O of the first buffer stage 50 when both the synchronous control signal PCLKEN1 and the internal clock PCLK have a high level. The first data and the second data are provided to the latch means 74, 75, which are provided to the common data input lines DI_E and DI_O.

Therefore, the first data D0_E input evenly and the second data input oddly input to the output nodes NF1_E, NF1_O, NF2_E, and NF2_O of the first buffer stage 50 and the second buffer stage 60. D0_O) are stored, respectively, and the first data and the second data D0_E and D0_O are output to the data input lines DI_E and DI_O in response to the rising edge of the PCLK while the PCLKEN1 is high.

As described above, since the buffer stage is composed of two stages, since tDSS is input with a delay time of, for example, 3n s to tCC, when the buffer stage is composed of one, PCLKEN1 and PCLK become high at tDSS (min). This is because the PDSD signal toggles before the data stored in the output nodes NF1_E and NF1_O of the buffer stage are transmitted so that the next data arrives at the output nodes NF1_E and NF1_O of the buffer stage.

Therefore, as in the embodiment of the present invention, when the write latency is 2 CLK, data collision does not occur when the buffer stage is composed of two stages. If the write latency is assumed to be 3 CLK, the buffer stage should also be configured by three stages. . On the other hand, the synchronous end control signals PCLKEN1 and PCLKEN2 are signals generated in synchronization with the clock PCLK. PCLKEN1 receives a PCLK when PDSEN1 is high, and generates a window including a PCLK generated two clocks later than a clock at which a write command is input. It is a signal. In addition, PCLKEN2 is a signal that is alternately high with PCLKEN1 and has a window including PCLK that occurs three clocks later than the write command. That is, the data of the first buffer stage output nodes NF1_E and NF1_O are transmitted to the data input lines DI_E and DI_O by the PCLK generated 2 CLK after the write command, and the second buffer stage is generated by the PCLK generated after 3 CLK. Data of the output nodes NF2_E and NF2_O are supplied to the data input lines DI_E and DI_O.

5 is a circuit diagram of a buffer stage control circuit 30 according to an embodiment of the present invention.

As shown in FIG. 5, the buffer stage control circuit 30 includes a plurality of switching means 31a and 31b, a plurality of latch means 32a and 32b, NAND gates 33a and 33b, and an inverting means. Fields 34a, 34b, 34c, and 34d and the NMOS transistor 35.

Referring to the timing diagram of FIG. 3, referring to the operation of the buffer stage control circuit 30, first, when the PWR signal is low, the PDSEN1 and PDSEN2 signals remain low, and when the write operation is started, the PWR signal becomes high. PDSEN2 goes high. Thereafter, whenever the PDS signal transitions high, the PDSEN1 and PDSEN2 signals transition to "low" or "high". Therefore, it is preferable that the time point when the first PDS signal transitions high occurs after the PWR signal transitions high. That is, the PDSEN1 and PDSEN2 signals are preferably signals having windows including the high and low edges of the first PDS signal and the high and low edges of the second PDS signal, respectively.

6 is a circuit diagram of a synchronous control circuit 40 according to an embodiment of the present invention.

As shown in FIG. 6, the synchronous control circuit 40 includes a plurality of switching means 41a, 41b, 41c, 41d, a plurality of latch means 42a, 42b, 42c, 42d, and a NAND gate. 43 and inverting means 44a, 44b.

The synchronous stage control circuit 40 inputs the PDSEN1 and PDSEN2 signals output from the buffer stage control circuit 30 to generate the PCLKEN1 and PCLKEN2 signals, which are signals that control the data to be input to the data path with a delay of 2 CLK from the write command. do.

The best embodiments have been described in the drawings and specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. For example, although the present disclosure describes a case where data is input into DDR, the present invention may be applied even when data is input at a single data rate SDR, that is, only when data is received only at the high edge of the clock CLK. Can be applied. In this case, it is preferable to remove the second column and the data output terminal DI_O of the buffer stage and the synchronization stage. In addition, in the case of SDR, since the write latency can be implemented with 1CLK instead of 2CLK, the latch means of the buffer stage may be reduced from 3 stages to 1 stage. Therefore, the scope of the present invention should be defined by the technical spirit of the appended claims.

According to the present invention as described above, there is provided a data input circuit which is input together with a data strobe signal, has a data rate of DDR or higher, and which data is input. Therefore, the operation speed of the synchronous semiconductor memory device can be improved by excluding the influence of the time tAC from the clock to the data output and the time tFL required for the data to fly from the memory to the controller. In addition, it works effectively even if DS signals and data are continuously input to DDR with variable time difference. In addition, since the buffer stage is composed of two or more stages, the delay time of the buffer stage control circuit or a part of the synchronous stage control circuit can be easily corrected even if the time difference range between the DS signal and the clock is changed.

1 is a timing diagram showing various time required for limiting tCC in the prior art.

2 is a block diagram of a data input circuit according to an embodiment of the present invention.

3A and 3B are timing diagrams illustrating a case where a time difference between a clock and a DS signal is 0.5CLK and 1CLK, respectively, in the data input circuit shown in FIG.

FIG. 4 is a detailed circuit diagram of the first buffer stage, the second buffer stage, the first sync stage, and the second sync stage shown in FIG. 2.

5 is a detailed circuit diagram of a buffer stage control circuit according to an embodiment of the present invention.

6 is a detailed circuit diagram of a synchronous control circuit according to an embodiment of the present invention.

Claims (12)

A data input circuit of a synchronous memory device in which a data strobe signal input at the same time as a data input time and serving as a clock for sampling data is used. A plurality of buffer stages for alternately outputting input data in response to the data strobe signal and buffer stage control signals; A plurality of synchronization stages which, in response to the synchronization stage control signals, synchronize the output data of the buffer stages with an internal clock to provide a common data input line; A buffer stage control circuit for inputting a data strobe signal converted to a CMOS level and generating the buffer stage control signals having different phases by the number of buffer stages within a section in which a write operation is permitted; And And a synchronization stage control circuit for generating the synchronization stage control signals for inputting the buffer stage control signals and synchronizing them to an internal clock within a section in which a write operation is permitted. The data of the memory device according to claim 1, wherein the buffer stage control signals outputted through the buffer stage control circuit are changed every time the data strobe signal converted to a CMOS level transitions to a high level. Input circuit. The data input circuit of claim 1, wherein the plurality of buffer stages are connected in parallel as many as the number of data inputted during one clock cycle. 4. The data input circuit of claim 3, wherein the data input to the buffer stages is input at a rising edge and a falling edge of a clock, and the buffer stage is composed of two. The method of claim 1, wherein each of the buffer stages, Logical AND means for ANDing the buffer stage control signal and the data strobe signal; A plurality of transmission means controlled by the output of the AND product to transmit the input data; And And a plurality of latch means for storing an output of said transfer means. 6. The data input circuit of a memory device according to claim 5, wherein the transmission means and the latch means are configured in two stages to output the even and odd numbers separately from the input data. 6. The data input circuit of claim 5, wherein each of the transfer means comprises a transfer gate and each of the latch means comprises a CMOS latch. The method of claim 1, wherein each of the synchronization stages, A NAND gate for inputting a synchronous stage control signal and an internal clock; At least one transfer means controlled by an output of the NAND gate to transmit output data of the buffer stage; And And at least one latch means for storing an output of said transfer means. 10. The data input circuit of claim 8, wherein the transfer means comprises a transfer gate and the latch means comprises a CMOS latch. The data input circuit of claim 8, wherein the transmission means and the latch means are configured in two stages to separately output even and odd numbers from among input data. The method of claim 1, wherein the data input circuit, A data strobe switch for converting an external input data strobe signal to a CMOS level; And And a delay circuit for delaying an output signal of the data straw switching unit and supplying the delayed output signal to the buffer stage. The method of claim 1, wherein the data input circuit, And a data switching section for converting external input data to a CMOS level and supplying the buffer data to the buffer stage.