KR20010055443A - Serial input parallel output circuit - Google Patents

Abstract

PURPOSE: A serial-input and a parallel-output circuit is provided to increase processing speed by improving operating speed of the serial-input and the parallel-output circuit. CONSTITUTION: A serial-input and a parallel-output circuit outputs the parallel-output signal of N bits to accept the serial-input signal. A sub-clock creation unit creates sub-clock signal of N units, for phase to be difference each other, making response to clock signals approved from outside. The first flip-flop array(130) outputs and accepts the serial-input signal, making response each other to corresponding sub-clock signal. The second flip-flop array(140) outputs and accepts N-bits data from the first flip-flop array, making response to the main clock signal. The main clock creation unit(120) creates the main clock signal for compounding at least two signals among the sub-clock signals outputted from the sub-clock creation unit.

Description

Serial input parallel output circuit {SERIAL INPUT PARALLEL OUTPUT CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic circuits and, more particularly, to circuits that take serial data and output N-bits in parallel.

1 is a block diagram showing the configuration of a conventional series-input parallel-output circuit.

Referring to FIG. 1, a serial-input parallel-output circuit that receives serial data SI and outputs N-bits in parallel includes a shift register chain 10 and a latch circuit 20. The shift register chain 10 includes N D-flip flops 10_1 to 10_N connected in series, and the latch circuit 20 includes D-flip flops 10_1 to the shift register chain 10. N-D flip-flops 20_1 to 20_N respectively corresponding to 10_N).

The D-flip flops 10_1 to 10_N of the shift register chain 10 sequentially receive serial input data SI in response to a clock signal CLOCK. The enable signal ENABLE occurs when the clock signal CLOCK transitions (e.g., transitions from low level to high level) after the last N-th D-flip-flop 10_N receives the serial input data SI. Is activated.

The D-flip flops 20_1 to 20_N of the latch circuit 20 each receive data output from the corresponding D-flip flop of the shift register chain 10 in response to the enable signal ENABLE. Latch. At the next transition point of the enable signal ENABLE, the D-flip-flops 20_1 to 20_N simultaneously output N-bit data P0_1 to PO_N.

In this serial-input parallel-output circuit, the speed at which the serial input data SI is converted into the parallel output data PO and output is proportional to the speed of the clock signal CLOCK applied to each of the D flip-flops. Recent technological advances in data processing have resulted in data processing rates of up to several GHz. However, clock speeds are currently limited to a few MHz because of clock source printed circuit board (PCB) bandwidth limitations and crystal crystalline limitations. Therefore, the conventional serial-input parallel-output circuit as described above has a problem that high-speed data processing is difficult.

Accordingly, it is an object of the present invention to provide a serial-input parallel-output circuit that receives a serial input signal, converts it into a parallel output signal at high speed, and outputs the same.

1 is a block diagram showing the configuration of a conventional series-input parallel-output circuit;

2 is a block diagram showing the configuration of a series-input parallel-output circuit according to a preferred embodiment of the present invention;

3 is a block diagram showing the configuration of the DLL circuit shown in FIG.

4 is a detailed circuit diagram of the voltage control delay circuit shown in FIG. 3;

5 is a detailed circuit diagram of the delay element shown in FIG. 4;

6 is a detailed circuit diagram of the main clock generator shown in FIG. 2; And

FIG. 7 is a timing diagram that simulates the circuit shown in FIG. 2.

* Description of the symbols for the main parts of the drawings *

110: DLL circuit 112: phase detector

114: voltage control delay circuit 120: main clock generator

130: first D-flip-flop array 140: second D-flip-flop array

201 to 209: delay element

According to a feature of the present invention for achieving the object of the present invention as described above, a serial-input parallel-output circuit for receiving a serial input signal and outputting an N-bit parallel output signal includes: a clock signal applied from the outside; Subclock generating means for generating N sub clock signals having different phases in response to the sub clocks; A first flip-flop array that receives and outputs the serial input signal in response to a corresponding sub clock signal, respectively; Main clock generating means for generating a main clock signal in response to the sub clock signals; And a second flip-flop array that receives and outputs N-bit data from the first flip-flop array in response to the main clock signal.

In a preferred embodiment, the sub-clock generating means comprises: a voltage control delay for generating N sub-clock signals having different phases in response to the clock signal, the inverted clock signal, and the corrected clock signal and the inverted corrected clock signal. Circuitry and phase correction means for generating a correction clock signal inverted with the correction clock signal for correcting the phase of the sub clock signals.

In a preferred embodiment, the main clock generating means generates the main clock signal by combining at least two signals among the sub clock signals output from the sub clock generating means.

By such a device, it is possible to implement a serial-input parallel-output circuit with improved operation speed.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 7. In the following description, the same or similar reference numerals and signs in the drawings represent the same or similar components as much as possible.

FIG. 2 is a block diagram showing the configuration of a series-input parallel-output circuit according to a preferred embodiment of the present invention, and FIG. 7 is a timing diagram simulating the series-input parallel-output circuit shown in FIG. In Fig. 7, the clock speed is up to 65 MHz but it is obvious that it can be changed.

Referring to FIG. 2, a serial-input parallel-output circuit that receives a serial input signal SI and outputs 7-bit parallel output signals PO_1 to PO7 includes a delay locked loop (DLL) circuit 110 and a main clock. Generator 120, a first D flip-flop array 130, and a second D flip-flop array 140.

As illustrated in FIG. 7, the DLL circuit 110 generates N sub clock signals CLK1 to CLK7 having different phases in response to a clock signal CLOCK applied from the outside. The first D-flip-flop array includes seven D-flip-flops 130_1 to 130_7 respectively corresponding to the sub clock signals CLK1 to CLK7. Each of the D-flip-flops 130_1 to 130_7 outputs the serial input signal SI to an output terminal Q in response to a corresponding sub-clock signal. Since the sub clock signals CLK1 to CLK7 are sequentially enabled at a high level (logical '1'), the seven serial input signals SI which are sequentially input from the first D-flip-flop 130_1 to the last D -Flip-flop 130_7 is sequentially output.

The main clock generator 120 generates a main clock signal MCLK by combining a third sub clock signal CLK3 and a seventh sub clock signal CLK7 among the sub clock signals output from the DLL circuit 110. do.

The second D-flip-flop array 140 includes seven D-flip-flops 140_1 to 140_7 respectively corresponding to the D-flip-flops 130_1 to 130_7 of the first D-flip-flop array 130. It consists of. The D flip-flops 140_1 ˜ 140_7 receive and output signals output from the first D flip-flop array 130 in response to the main clock signal MCLK. Parallel output signals PO_1 to PO_7 output simultaneously from the second D-flip-flop array 140 are seven serial input signals sequentially input from the outside.

3 is a block diagram showing the configuration of the DLL circuit shown in FIG.

Referring to FIG. 3, the DLL circuit 110 includes a phase detector 112 and a voltage controlled delay circuit 114. The phase detector 110 receives the signals OUT1, OUT2, and OUT3 output from the voltage control delay circuit 114 while the power down signal PDWN is at an inactive level, and inputs the signals IN1, IN2, and IN3. The phase correction clock signals CK and CKB are generated to correct the phases of the sub clock signals CLK1 to CLK7 output from the voltage control delay circuit 114.

FIG. 4 is a detailed circuit diagram of the voltage control delay circuit shown in FIG. 3.

Referring to FIG. 4, the voltage control delay circuit 144 may include phase correction clock signals CK and CKB input from the phase detector 110, a clock signal CLOCK applied from the outside, and an inverter IV1. The inverted clock signal CLOCKB is applied to generate the phase correction output signals OUT1, OUT2, and OUT3 and the sub clock signals CLK1 to CLK7.

The voltage controlled delay circuit 144 is composed of nine delay elements 201 to 209, seven inverters 212 to 218, end gates 222 and 224, and a D-flip flop 210. . The delay element 201 includes inverters 302, 312, 314, three-state inverters 304, 306, 308, 310, a transfer gate 320, a NAND gate 322 as shown in FIG. 5. And an end gate 324.

The transfer gate 320 has a current path formed between the output terminal of the inverter 312 and the one input terminal of the NAND gate 322 and a PMOS transistor 316 having a gate connected to a ground voltage VSS and the inverter. The NMOS transistor 318 has a current path formed between the output terminal of 312 and the one input terminal of the NAND gate 322 and a gate connected to the power supply voltage VDD.

In the three-state inverters 304 to 310, the phase correction clock signal CK input from the phase detector 110 is an activation level (eg, a high level), and the inverted phase correction clock signal CKB is inactivated. At the level (eg, low level), the input signal is inverted and output.

The first output signal OUTA output through the delay element 201 is input through one input terminal DB, is inverted by the inverter 302, and is input through the type force terminal D. The signals through the three-state inverters 304-310, the inverter 312, and the transmission gate 320 are NAND-operated signals at the NAND gate 322.

The second output signal OUTB output through the delay element 201 is a signal output from the inverter 312, and the third output signal OUTC is a signal output from the last three-state inverter 310. to be. The fourth output signal OUTD is a signal in which the signal output from the second three-state inverter 306 is inverted by the inverter 314 and the signal input through the type force terminal D are inputted through an AND gate ( In operation 324, the signal is ANDed.

Although not shown in the figure, the remaining delay elements 202 to 209 also have the same circuit configuration as the delay element 201 shown in FIG.

Referring back to FIG. 4, the second and third output signals OUTB and OUTC output from the delay elements 201 to 208 are respectively input to the next input terminal and the type force terminal.

The fourth output signal OUTD output from the delay element 208 is output as the first sub clock signal CLK1 through the inverter 218. The third output signals output through the delay elements 202 to 207 are output as the second to seventh sub clock signals CLK2 to CLK7 through a corresponding inverter among the inverters 212 to 217.

The first output signals OUTA output from the delay elements 202 to 205 are input to the AND gate 222. The first output signals OUTA output from the delay elements 206 to 208 are input to the AND gate 224. The first output signal OUTA output from the last delay element 209 is provided as an input signal D of the D flip-flop 210. The D flip-flop 210 outputs the input signal D to the output terminal Q in response to the inverted clock signal CLOCKB. The signal OUT1 output from the D flip-flop 210 and the signals OUT2 and OUT3 output from the AND gates 222 and 224 are provided to the phase detector 112.

FIG. 6 is a detailed circuit diagram of the main clock generator shown in FIG. 2.

Referring to FIG. 6, the main clock generator 120 includes NAND gates 342 and 344, an inverter 350, and capacitors 352 and 354. The NAND gate 342 receives a NAND operation by receiving a third sub clock signal CLK3 output from the DLL circuit 110 and an output signal of the NAND gate 344, and the NAND gate 344 performs the NAND operation. The NAND operation is performed on the output signal of the gate 342 and the seventh sub clock signal CLK7 output from the DLL circuit 110.

The inverter 350 is controlled by a PMOS transistor 346 having one current path and a gate controlled by an output signal of the NAND gate 344, and an output signal of one current path and the NAND gate 344. NMOS transistor 348 having a gate to be formed. Current paths of the transistors 346 and 348 are sequentially formed in series between the power supply voltage VDD and the ground voltage VSS.

In the initial state, when the third and seventh sub-clock signals CLK3 and CLK7 are both in an inactive level (eg, a low level), the NAND gates 342 and 344 both output a high level signal. When the third sub clock signal CLK3 is first activated to a high level, the NAND gate 342 outputs a low level signal. After a predetermined time, the NAND gate 342 outputs a high level state when the third clock signal CLK is deactivated to a low level again. The output signal of the NAND gate 344 maintains a high level while the seventh sub clock signal CLK7 is at a low level. Therefore, the main clock signal MCLK output through the inverter 350 maintains a low level.

When the seventh sub clock signal CLK7 is activated to a high level, the output signal of the NAND gate 344 transitions to a low level. Therefore, the main clock signal MCLK output through the inverter 350 is activated to a high level. In other words, when the seventh sub clock signal CLK7 output from the DLL circuit 110 is activated, the main clock signal MCLK is activated.

According to this embodiment, the main clock generator 120 generates the main clock signal using the third and seventh sub-clock signals among the sub-clock signals output from the DLL circuit 110, but may use other clock signals. .

As described above, the serial-input parallel-output circuit of the present invention generates the sub-clock signals CLK1 to CLK7 having different phases to transmit the serial input signal SI to the first D-flip-flop array 130. Latch. The main clock generator 120 generates the main clock signal MCLK when the last seventh sub clock signal CLK7 is generated. The second D flip-flop array 140 receives an output signal from the first D flip-flop array 130 in response to the main clock signal and outputs the N-bit parallel output signals PO1 to PO7.

The operating speed of the conventional serial-input parallel-output circuit is proportional to the speed of the clock signal CLOCK, but the operating speed of the serial-input parallel-output circuit of the present invention is the sub-clock signal generated by the DLL circuit 110. It is closely related to their frequency. As shown in FIG. 7, the DLL circuit of the present invention generates seven sub clock signals CLK1 to CLK7 during one cycle of the clock signal CLOCK. Therefore, an operation speed seven times faster than the conventional one can be obtained.

In this embodiment, the DLL circuit 110 generates seven sub-clock signals, but this is merely described, for example, and the circuit for generating the sub-clock signals can be expanded. Obviously, as the number of sub-clock signals increases, the number of parallel output bits can be increased.

According to the present invention as described above, the operation speed of the series-input parallel-output circuit is improved. Therefore, high speed data processing is possible.

Claims (3)

In a serial-input parallel-output circuit that accepts a serial input signal and outputs an N-bit parallel output signal: Sub-clock generating means for generating N sub-clock signals having different phases in response to a clock signal applied from the outside; A first flip-flop array that receives and outputs the serial input signal in response to a corresponding sub clock signal, respectively; Main clock generating means for generating a main clock signal in response to the sub clock signals; And And a second flip-flop array for receiving and outputting N-bit data from the first flip-flop array in response to the main clock signal. The method of claim 1, The sub clock generating means, A voltage control delay circuit for generating N sub-clock signals having different phases in response to the clock signal, an inverted clock signal, and a corrected clock signal and an inverted corrected clock signal; And And phase correction means for generating a correction clock signal inverted with the correction clock signal for correcting the phase of the sub clock signals. The method of claim 1, The main clock generating means, And the at least two signals of the sub clock signals output from the sub clock generating means generate the main clock signal.