KR19990053199A - High-Speed Synchronous Memory Devices for Testing - Google Patents

Abstract

The present invention provides a clock generator that generates a high-frequency clock inside the memory chip to solve the problem that the test frequency can not be tested in accordance with the specifications of the synchronous memory device due to the limitation of the clock frequency that can be generated in the test equipment. The internal clock allows the synchronous memory device to run and test. To this end, the high-speed synchronous memory device of the present invention, the external clock input unit for receiving an external clock; An internal clock generator for generating a high frequency internal clock for a test; A control signal generator for generating a control signal for determining a test mode and a general mode other than the test mode; And an output unit for selectively outputting the internal clock or the external clock in response to the control signal.

Description

High-Speed Synchronous Memory Devices for Testing

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a synchronous memory device, and more particularly to a high-speed synchronous memory device having a high-speed clock generator in a memory for testing a cycle time of the memory device.

As is well known, synchronous memory devices operating in synchronization with clocks for high speed operation of memory devices are being actively studied.

However, since the characteristics of the conventional synchronous memory device exceed the limit of test equipment, a lot of problems are generated in the test for mass production of the high-speed synchronous memory device. In other words, the current testable memory device test equipment has a maximum measurable frequency of 250MHZ, and the synchronous memory device currently being developed has a frequency of 250MHZ or higher. Since we can't test, we can't figure out the actual fail.

It is an object of the present invention to provide a fast synchronous memory device that can be tested by overcoming the limitations of test equipment.

1 is a block diagram illustrating a memory device according to an embodiment of the present invention.

2 shows an exemplary diagram of a ring oscillator and an internal clock output therefrom.

* Explanation of symbols for main parts of the drawings

100: control signal generator 200: external clock input pad

300: ring oscillator 400: output

110: test pad 120: resistance

130, 140: Inverter 410, 420, 430: NOR gate

A high-speed synchronous memory device of the present invention for achieving the above object, the external clock input unit for receiving an external clock; An internal clock generator for generating a high frequency internal clock for a test; A control signal generator for generating a control signal for determining a test mode and a general mode other than the test mode; And an output unit for selectively outputting the internal clock or the external clock in response to the control signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram illustrating a memory device according to an embodiment of the present invention.

Referring to FIG. 1, a memory device according to an embodiment of the present invention includes an external clock input pad 200 as an external clock input unit that receives an external clock, and a ring oscillator 300 that generates an internal clock of high frequency for a test. A control signal generator 100 generating control signals TEST and / TEST for determining a test mode and a general mode other than the test mode; And an output unit 400 for selectively outputting the internal clock or the external clock in response to the control signals TEST and / TEST.

Looking at each configuration in detail, first, the control signal generator is a pad 110 receives a signal having a binary value of 'high' or 'low', and when the pad is floating to provide a bias to the pad A plurality of resistors 120 connected between the pad 110 and the ground voltage terminal and the first and second control signals TEST and / TEST complementary to each other by buffering the signal input from the pad 110. Inverters 130 and 140 are included. Next, the output unit 400 includes a first NOR gate 410 for receiving an external clock from the external clock input unit 200 and the first control signal TEST, and the ring oscillator 300 from the first NOR gate 410. A second NOR gate 420 that receives an internal clock and the second control signal / TEST, and an NOR operation of each output signal from the first and second NOR gate paths 410 and 420 are stored in a memory. And a third NOR gate 430 output to the internal circuit.

FIG. 2 shows an exemplary diagram of a ring oscillator and an internal clock output therefrom. As shown in the drawing, an odd number of inverters are connected in series and a final output signal is fed back to an input terminal. Such a ring oscillator can generate an internal clock having a high frequency of 300 MHz by implementing the delay time of the total number of inverters at 3.0 ns.

As described above, the operation of FIG. 1 will be described. When the 'high' signal is applied to the extra test pad 110, since the first control signal TEST becomes 'high', the external clock is not transmitted to the internal circuit by the first NOR gate 410. Instead, the internal clock generated from the ring oscillator 300 is transferred to the internal circuit by the second NOR gate 420 because the second control signal is 'low'. That is, in the present invention, since a frequency not generated by the existing test equipment can be generated internally, a test conforming to a design specification can be performed. In addition, when testing by the test equipment normally, it is possible to apply a 'low' signal to the test pad 110.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those who have knowledge of.

The present invention can solve the test problem of the current synchronous memory because it is possible to operate only inside the chip by making the high frequency that cannot be generated by the memory test equipment inside the chip.

Claims (5)

An external clock input unit configured to receive an external clock; An internal clock generator for generating a high frequency internal clock for a test; A control signal generator for generating a control signal for determining a test mode and a general mode other than the test mode; And An output unit for selectively outputting the internal clock or the external clock in response to the control signal A synchronous memory device comprising a. The method of claim 1, The control signal generator, A pad receiving a signal having a binary value; Means for providing a bias to the pad when the pad is floated; And And means for buffering a signal input from the pad to output first and second control signals complementary to each other. The method of claim 2, The output unit, A first NOR gate configured to receive an external clock and the first control signal from the external clock input unit; A second NOR gate configured to receive an internal clock and the second control signal from the internal clock generator; And And a third NOR gate configured to perform an NOR operation on the output signals from the first and second NOR gates as two input signals, and then output the same to an internal circuit embedded in the memory. The method of claim 2, And a bias providing means of the control signal generator includes a resistor connected between the pad and the ground voltage terminal. The method of claim 1, And the internal clock generation unit is a ring oscillator.