JP2010056592A - Flip-flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit which eliminates the asymmetry of delay time and shortens delay time from an input up to an output. <P>SOLUTION: The flip-flop circuit includes: a clocked amplifier which is a master latch for outputting first and second signals having mutually complementary relationship and third and fourth signals having mutually complementary relationship in accordance with a differential input signal and a differential clock signal; and a symmetric slave latch for outputting two output signals in accordance with the first to fourth signals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present disclosure generally relates to electronic circuits, and more particularly to flip-flop circuits.

  The types of flip-flop circuits can be roughly divided into three types: static type, dynamic type, and CML (current mode logic) type. Static flip-flops are widely used because they do not consume static current and have a wide operation margin, but have the problem of the slowest operating speed among the above three types of flip-flops. .

  As the static flip-flop, a large number of circuit forms using CMOS have been proposed. A sense amplifier type flip-flop is known as a type of flip-flop capable of operating at the highest speed.

  FIG. 1 is a diagram illustrating an example of a configuration of a sense amplifier type flip-flop. The sense amplifier type flip-flop of FIG. 1 includes a master latch 10 and a slave latch 24. The master latch 10 includes PMOS transistors 11 to 16 and NMOS transistors 17 to 21. The slave latch 24 includes NAND circuits 22 and 23.

  The master latch 10 is a clocked amplifier, and a differential amplifier is configured with NMOS transistors 19 to 21 as a basic part. A clock signal CLK is applied to the gate terminal of the NMOS transistor 21 that functions as a constant current source of the differential amplifier. When the clock signal CLK becomes HIGH, the NMOS transistor 21 conducts and functions as a constant current source, and the output signals SB and RB are changed according to the differential input signals IN and INB input to the gates of the NMOS transistors 19 and 20. Output as a differential signal. When the clock signal CLK is LOW, the PMOS transistors 11 and 14 are turned on, so that the output signals SB and RB are both HIGH.

  In the slave latch 24, the outputs of the two-input NAND circuits 22 and 23 are supplied to one of the other inputs. Output signals SB and RB from the master latch 10 are supplied to the other inputs of the NAND circuits 22 and 23. Outputs of the NAND circuits 22 and 23 become output signals Q and QB of the slave latch 24, respectively.

  When the clock signal CLK is LOW, the signals SB and RB are both high, so that the slave latch 24 is in the data holding state and holds the logic levels of the output signals Q and QB. At this time, the input signals IN and INB are cut off. When the clock signal CLK becomes HIGH, differential signal outputs corresponding to the input signals IN and INB are supplied from the master latch 10 to the slave latch 24 as signals SB and RB. In response to the signals SB and RB, one of which is HIGH and the other is LOW, the latches formed by the NAND circuits 22 and 23 latch new data corresponding to the input signals IN and INB. Thereafter, when the clock signal CLK becomes LOW, both the signals SB and RB become HIGH, the slave latch 24 enters the data holding state, and holds the logic levels of the output signals Q and QB.

  The sense amplifier type flip-flop of FIG. 1 has an advantage that the operation speed of the master latch 10 which is a clocked amplifier is high. However, there is a problem that the timings of signal changes of the output signals Q and QB differ depending on the values of the input signals IN and INB.

  For example, in a state where the output signal Q is HIGH and the output signal QB is LOW, the signal SB and RB are both HIGH, and the signal SB and RB are HIGH and LOW, respectively. And In this case, first, the output signal QB changes to HIGH, and the HIGH output signal QB is input to the NAND circuit 22, whereby the output signal Q becomes LOW. Therefore, the time for the transition to occur in the output signal Q is later than that in the output signal QB. When the master latch 10 is counted as one gate, the slower signal is delayed by three gates from the input signals IN and INB.

  Further, for example, when the output signal Q is LOW and the output signal QB is HIGH, the signal SB and RB are both HIGH, and the signal SB and RB are LOW and HIGH, respectively. Suppose that In this case, first, the output signal Q changes to HIGH, and the HIGH output signal Q is input to the NAND circuit 23, whereby the output signal QB becomes LOW. Therefore, the output signal QB has a slower transition time than the output signal Q. When the master latch 10 is counted as one gate, the slower signal is delayed by three gates from the input signals IN and INB.

  As a circuit configuration for solving the problem that the timing of the signal changes of the output signals Q and QB is different, there is a circuit configuration using a symmetric slave latch instead of the slave latch 24 of FIG. FIG. 2 is a diagram illustrating an example of a configuration of a symmetric slave latch.

  The symmetric slave latch of FIG. 2 includes a keeper circuit 25 and a drive circuit 26. The keeper circuit 25 includes PMOS transistors 31 to 34 and NMOS transistors 35 to 38. The drive circuit 26 includes PMOS transistors 39 and 40 and NMOS transistors 41 and 42. Signals SB and RB input to the symmetric slave latch are outputs of the master latch 10 shown in FIG. The signal S is an inverted signal of the signal SB and is generated by the inverter 43. Further, the signal R is an inverted signal of the signal RB and is generated by the inverter 44.

  In the symmetric slave latch, an inverter constituted by the PMOS transistor 32 and the NMOS transistor 35 and an inverter constituted by the PMOS transistor 34 and the NMOS transistor 37 are cross-coupled to constitute a latch. The data holding function of the keeper circuit 25 is realized by this latch. When both the signals SB and RB are HIGH, the PMOS transistor 31, the PMOS transistor 33, the NMOS transistor 36, and the NMOS transistor 38 are all turned on, and the latch performs a data holding function. At this time, in the drive circuit 26, the PMOS transistor 39, the PMOS transistor 40, the NMOS transistor 41, and the NMOS transistor 42 are all non-conductive, and the drive circuit 26 does not affect the output signals Q and QB.

  It is assumed that the signals SB and RB are changed from the first state where both signals SB and RB are HIGH to the second state where signals SB and RB are HIGH and LOW, respectively. In this case, in the drive circuit 26, the PMOS transistor 39 is turned off, the PMOS transistor 40 is turned on, the NMOS transistor 41 is turned on, and the NMOS transistor 42 is turned off. Therefore, the output signal Q becomes LOW and the output signal QB becomes HIGH by the signal driving force by the drive circuit 26. Since the output signals Q and QB are simultaneously driven by the transistors of the drive circuit 26, the state transitions of the output signals Q and QB occur simultaneously. At this time, since the signal RB is LOW, both the PMOS transistor 31 and the NMOS transistor 38 become non-conductive. Therefore, when the output signal Q and the output signal QB are set to LOW and HIGH, respectively, by the signal driving force of the drive circuit 26, the keeper circuit 25 does not resist the signal change.

  The same applies when the first state in which the signals SB and RB are both HIGH changes to the second state in which the signals SB and RB are LOW and HIGH, respectively. In this case, due to the signal driving force by the drive circuit 26, the output signal Q becomes HIGH and the output signal QB becomes LOW. During this signal transition, the keeper circuit 25 does not resist the signal change.

  Thus, in the keeper circuit 25, a latch circuit is formed by cross-coupling so that the outputs of the two inverters are connected to the other input, and the outputs of the two inverters of the latch circuit are the outputs of the keeper circuit 25. There are two outputs. Further, the two outputs of the keeper circuit 25 are simultaneously shifted by the signal driving force of the drive circuit 26 corresponding to the two input signals. When the two inputs are HIGH, the latch function of the keeper circuit 25 is valid and holds data. When one of the two inputs is LOW and the other is HIGH, the drive circuit 26 changes the two outputs of the keeper circuit 25. At this time, the keeper circuit 25 does not exhibit a holding force against a signal change by the drive circuit 26.

As described above, in the symmetric slave latch of FIG. 2, the time at which two output transitions occur is the same. When attention is paid to one of the outputs, the delay time when transitioning from HIGH to LOW is equal to the delay time when transitioning from LOW to HIGH. As described above, the asymmetry of the delay time can be eliminated by the circuit configuration of FIG. 2, but the delay time from the input capture to the output is not particularly improved as compared with the circuit of FIG. If the master latch 10 is counted as one gate, the output signals Q and QB of the symmetric slave latch are delayed by three gates from the input signals IN and INB. That is, the master latch 10 is delayed by one stage, the inverters 43 and 44 are delayed by one stage, and the drive circuit 26 is delayed by one stage.
JP 2004-48757 A Japanese translation of PCT publication No. 2003-512752

  In view of the above, a flip-flop circuit that eliminates the asymmetry of the delay time and shortens the delay time from input to output is desired.

  The flip-flop circuit outputs a third signal and a fourth signal complementary to each other in a complementary relationship with each other in accordance with the differential input signal and the differential clock signal. A clocked amplifier that is a master latch and a symmetric slave latch that outputs two output signals in response to the first to fourth signals.

  According to at least one embodiment, it is possible to suppress the delay from the differential input signal capture timing to the transition of the output signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram showing the principle configuration of a flip-flop circuit in which the asymmetry of the delay time is eliminated and the delay time from input to output is shortened. FIG. 3A shows a conventional sense amplifier type flip-flop circuit 50 having a long delay time, and FIG. 3B shows a sense amplifier type flip-flop circuit 51 having a reduced delay time. In FIG. 3, the same components as those in FIGS. 1 and 2 are referred to by the same numerals, and a description thereof will be omitted.

  The sense amplifier type flip-flop circuit 50 shown in FIG. 3A includes a clocked amplifier 10, an inverter 43, an inverter 44, and a symmetric slave latch 27. The clocked amplifier 10 has the same configuration as the master latch 10 shown in FIG. The symmetric slave latch 27 is the symmetric slave latch 27 shown in FIG. 2 and includes a keeper circuit 25 and a drive circuit 26. Moreover, the inverters 43 and 44 shown in FIG. 3 are the inverters 43 and 44 shown in FIG.

  The configuration and operation of the sense amplifier type flip-flop circuit 50 are as described above with reference to FIGS. In this sense amplifier type flip-flop circuit 50, the asymmetry of the delay time is eliminated, but there is a delay time corresponding to three stages of gates from the capture of the input signals IN and INB to the output signals Q and QB. Of these three stages of delay time, the inverters 43 and 44 cause a delay of one stage.

  The sense amplifier type flip-flop circuit 51 shown in FIG. 3B includes a clocked amplifier 53 and a symmetric slave latch 27. The symmetric slave latch 27 includes the keeper circuit 25 and the drive circuit 26 shown in FIG. The clocked amplifier 53 is a third signal complementary to the first signal SBH and the second signal SBL that are complementary to each other in accordance with the differential input signals IN and INB and the differential clock signals CLK and CLKX. The master latch outputs RBH and the fourth signal RBL. The symmetric slave latch 27 is a symmetric slave latch that outputs two output signals Q and QB in response to the first to fourth signals. Unlike the configuration of FIG. 3A, the clocked amplifier 53 is configured to output four signals, and the inverters 43 and 44 are not used.

  FIG. 4 is a diagram showing an example of the circuit configuration of the sense amplifier type flip-flop circuit 51. As shown in FIG. 4, the same components as those in FIGS. 2 and 3 are referred to by the same numerals, and a description thereof will be omitted.

  The clocked amplifier 53 includes a first clocked amplifier 55 that operates in synchronization with the first clock signal CLK of the differential clock signal and outputs the first signal SBH and the third signal RBH. The clocked amplifier 53 includes a second clocked amplifier 56 that operates in synchronization with the second clock signal CLKX of the differential clock signal and outputs the second signal SBL and the fourth signal RBL.

  The circuit configuration of the clocked amplifier 55 is the same as that of the master latch 10 shown in FIG. The clocked amplifier 55 includes PMOS transistors 61 to 66 and NMOS transistors 67 to 71. In the clocked amplifier 55, a differential amplifier is configured with the NMOS transistors 69 to 71 as basic portions. The clock signal CLK is applied to the gate terminal of the NMOS transistor 71 that functions as a constant current source of the differential amplifier. When the clock signal CLK becomes HIGH, the NMOS transistor 71 conducts and functions as a constant current source, and the output signals SBH and RBH are output according to the differential input signals IN and INB input to the gates of the NMOS transistors 69 and 70. Output as a differential signal. When the clock signal CLK is LOW, the PMOS transistors 61 and 64 are turned on, so that the output signals SBH and RBH are both HIGH.

  The circuit configuration of the clocked amplifier 56 corresponds to the circuit configuration of the clocked amplifier 55 in which the NMOS transistor and the PMOS transistor are replaced with a PMOS transistor and an NMOS transistor, respectively. The clocked amplifier 56 includes NMOS transistors 81 to 86 and PMOS transistors 87 to 91. In the clocked amplifier 56, a differential amplifier is configured with PMOS transistors 89 to 91 as a basic part. The clock signal CLK is applied to the gate terminal of the PMOS transistor 91 that functions as a constant current source of the differential amplifier. When the clock signal CLKX becomes LOW, the PMOS transistor 91 becomes conductive and functions as a constant current source, and the output signals SBL and RBL are changed according to the differential input signals IN and INB input to the gates of the PMOS transistors 89 and 00. Output as a differential signal. When the clock signal CLKX is HIGH, the NMOS transistors 81 and 84 are turned on, so that the output signals SBH and RBH are both LOW.

  With the above configuration, the clocked amplifier 53 generates the first to fourth signals SBH, SBL, RBH, and RBL. Here, the signal SBH and the signal SBL are complementary to each other, and the signal SBL is an inverted signal of the signal SBH. The signal RBH and the signal RBL are complementary to each other, and the signal RBL is an inverted signal of the signal RBH. These inverted signals are not generated by the inverter as in the sense amplifier type flip-flop circuit 50 of FIG. 3A, but are directly generated by the clocked amplifier 53. Accordingly, the first to fourth signals SBH, SBL, RBH, and RBL are all delayed by one gate from the input signals IN and INB.

  The symmetric slave latch 27 includes a keeper circuit 25 that receives the first to fourth signals SBH, SBL, RBH, and RBL and outputs two output signals Q and QB. In addition, the symmetric slave latch 27 includes a drive circuit 26 that simultaneously transitions two output signals Q and QB according to the first to fourth signals SBH, SBL, RBH, and RBL.

  When both the signals SBH and RBH are HIGH, the PMOS transistor 31, the PMOS transistor 33, the NMOS transistor 36, and the NMOS transistor 38 are all in a conductive state, and the latch of the keeper circuit 25 exhibits a data holding function. At this time, in the drive circuit 26, the PMOS transistor 39, the PMOS transistor 40, the NMOS transistor 41, and the NMOS transistor 42 are all non-conductive, and the drive circuit 26 does not affect the output signals Q and QB.

  Assume that the signals SBH and RBH are changed from the first state in which both the signals SBH and RBH are HIGH to the second state in which the signals SBH and RBH are HIGH and LOW, respectively. In this case, in the drive circuit 26, the PMOS transistor 39 is turned off, the PMOS transistor 40 is turned on, the NMOS transistor 41 is turned on, and the NMOS transistor 42 is turned off. Therefore, the output signal Q becomes LOW and the output signal QB becomes HIGH by the signal driving force by the drive circuit 26. Since the output signals Q and QB are simultaneously driven by the transistors of the drive circuit 26, the state transitions of the output signals Q and QB occur simultaneously. At this time, since the signal RBH is LOW, both the PMOS transistor 31 and the NMOS transistor 38 become non-conductive. Therefore, when the output signal Q and the output signal QB are set to LOW and HIGH, respectively, by the signal driving force of the drive circuit 26, the keeper circuit 25 does not resist the signal change.

  The same applies to the case where the signals SBH and RBH change from the first state where both the signals SBH and RBH are HIGH to the second state where the signals SBH and RBH are LOW and HIGH, respectively. In this case, due to the signal driving force by the drive circuit 26, the output signal Q becomes HIGH and the output signal QB becomes LOW. During this signal transition, the keeper circuit 25 does not resist the signal change.

  As described above, in the first state of the differential clock signal (CLK = LOW, CLKX = HIGH), the clocked amplifier 53 receives the first signal SBH regardless of the signal values of the differential input signals IN and INB. Both the third signals RBH are set to the first level (HIGH). In addition, in the second state of the differential clock signal (CLK = HIGH, CLKX = LOW), one of the first signal SBH and the third signal RBH is changed to the first signal according to the signal values of the differential input signals IN and INB. One level (for example, HIGH) is set, and the other is set to the second level (for example, LOW). The symmetric slave latch 27 holds the logic states of the two output signals Q and QB when both the first signal SBH and the third signal RBH are at the first level (HIGH). The symmetric slave latch 27 outputs two output signals Q and QB when one of the first signal SBH and the third signal RBH is at the first level (HIGH) and the other is at the second level (LOW). The level is set according to the first signal SBH and the third signal RBH. Further, the keeper circuit 25 includes a latch circuit, and when the drive circuit 26 makes the signal transition of the two output signals Q and QB simultaneously, the latch circuit does not exhibit a holding power that prevents the signal from changing.

  FIG. 5 is a timing chart showing the change timing of each signal in the sense amplifier type flip-flop circuit 50 of FIG. FIG. 6 is a timing chart showing the change timing of each signal in the sense amplifier type flip-flop circuit 51 of FIG.

  In FIG. 5, the input signals IN and INB are taken in at the rising timing of the clock signal CLK, and the signals SB and RB that are the outputs of the clocked amplifier 10 transition after T1 time from the timing. Further, the signals S and R transition after T2 hours from the transition timing of the signals SB and RB. Further, the output signals Q and QB transition after T3 time from the transition timing of the signals S and R. T1 is a delay of one gate by the clocked amplifier 10, T2 is a delay of one gate by the inverters 43 and 44, and T3 is a delay of one gate by the symmetric slave latch 27.

  In FIG. 6, the input signals IN and INB are taken in at the rising timing of the clock signal CLK, and the signals SBH and RBH, which are the outputs of the clocked amplifier 53, transition after T1 time from the timing. Further, the signals SBL and RBL transition almost simultaneously with the transition timing of the signals SBH and RBH. Further, the output signals Q and QB transition after T3 hours from the transition timing of the signals SBH, RBH, SBL, and RBL. T1 is a delay of one gate by the clocked amplifier 10, and T3 is a delay of one gate by the symmetric slave latch 27. As described above, in the sense amplifier type flip-flop circuit 51 shown in FIG. 3B, there is only a delay of two stages of gates from the input signal IN and INB capture timing to the transition of the output signals Q and QB.

  If the threshold setting of the NMOS transistor and the PMOS transistor in the clocked amplifier 53 is set so that the response speeds of both are the same, the transition timing of the signals SBH and RBH and the transition timing of the signals SBL and RBL And almost at the same time. However, when the threshold setting of the NMOS transistor and the PMOS transistor is not so, the transition timing of the signals SBH and RBH and the transition timing of the signals SBL and RBL are slightly different. However, in the clocked amplifier 53, the delay from the input signal IN and INB capture timing to the signal SBH, RBH, SBL, and RBL transition timing is still a delay of one gate stage.

  FIG. 7 is a diagram of simulation results showing the difference in operating speed between the sense amplifier type flip-flop circuit 50 of FIG. 3A and the sense amplifier type flip-flop circuit 51 of FIG. In FIG. 7, the horizontal axis represents time (picoseconds), and the vertical axis represents voltage (millivolts). A clock waveform 101 indicates a waveform of a clock signal having a frequency of 4 GHz. A signal waveform 102 is a waveform showing a transition of the output signal Q of the sense amplifier type flip-flop circuit 51. A signal waveform 103 is a waveform showing a transition of the output signal Q of the sense amplifier type flip-flop circuit 50. The input signals IN and INB are taken in at the rising timing of the clock waveform 101. As can be seen from FIG. 7, the response speed of the sense amplifier type flip-flop circuit 51 is improved by about 13 picoseconds in this simulation compared to the sense amplifier type flip-flop circuit 50.

  FIG. 8 is a diagram showing a modification of the symmetric slave latch. In FIG. 8, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. The symmetric slave latch 27A shown in FIG. 8 has the same circuit configuration as the symmetric slave latch 27 shown in FIG. However, signals applied to the gate ends of the PMOS transistor 31, the PMOS transistor 33, the NMOS transistor 36, and the NMOS transistor 38 are different from those in FIG.

  In the symmetric slave latch 27A, the clock signal CLK is applied to the gate terminals of the PMOS transistor 31 and the PMOS transistor 33, and the clock signal CLKX is applied to the gate terminals of the NMOS transistor 36 and the NMOS transistor 38. Accordingly, when the clock signal CLK is LOW (CLKX = HIGH), the data holding function of the keeper circuit 25 is enabled, and when the clock signal CLK is HIGH (CLKX = LOW), the data holding function of the keeper circuit 25 is disabled. Become. Thereby, similar to the symmetric slave latch 27, an appropriate data holding operation and data rewriting operation can be realized.

  In the configuration of the symmetric slave latch 27A, the data holding function of the keeper circuit 25 can be invalidated by the clock signal before the output signal of the clocked amplifier 53 (see FIG. 3B) transitions. Therefore, a higher speed operation can be realized.

  FIG. 9 is a diagram showing a modification of the symmetric slave latch. 9, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. The symmetric slave latch 27B shown in FIG. 9 is obtained by removing the PMOS transistor 31, the PMOS transistor 33, the NMOS transistor 36, and the NMOS transistor 38 of the symmetric slave latch 27 shown in FIG. Furthermore, the symmetric slave latch 27B includes transmission gates 111 and 112. The transmission gates 111 and 112 connect between the latch circuit 113 and the drive circuit 26.

  Each of the transmission gates 111 and 112 is configured by parallel connection of a PMOS transistor and an NMOS transistor. A clock signal CLK is applied to the gate terminal of the PMOS transistor, and a clock signal CLKX is applied to the gate terminal of the NMOS transistor. Thereby, when the clock signal CLK is LOW (CLKX = HIGH), the transmission gates 111 and 112 are brought into conduction, the cross-coupled connection of the latch circuit 113 is established, and the data holding function is enabled. When the clock signal CLK is HIGH (CLKX = LOW), the transmission gates 111 and 112 are turned off, the cross-coupled connection of the latch circuit 113 is cut off, and the data holding function is disabled. Thereby, similar to the symmetric slave latch 27, an appropriate data holding operation and data rewriting operation can be realized.

  In the configuration of the symmetric slave latch 27B, the data holding function of the latch partial circuit 113 can be invalidated by the clock signal before the output signal of the clocked amplifier 53 (see FIG. 3B) transitions. Therefore, a higher speed operation can be realized.

  As described above, in the sense amplifier type flip-flop circuit 51 shown in FIG. 3B, the first to fourth signals SBH, SBL, RBH are used by using the differential clock signals CLK and CLKX. , And RBL. In general, in the case of a circuit that operates at a high-speed clock frequency of several GHz to 10 GHz or more, it is common to configure the circuit in a differential configuration. In the case of a circuit having a differential configuration, stable operation resistant to noise can be realized as compared with a circuit having a single phase configuration. Therefore, in a high-speed operation circuit that operates at a high clock frequency, the normal circuit configuration is that the clock signal CLK and its complementary signal CLKX are prepared.

  FIG. 10 is a diagram illustrating an example of the configuration of the high-speed operation circuit. In the configuration of FIG. 10, for example, a differential clock signal of 20 GHz is generated by a VCO (Voltage Controlled Oscillator) circuit 121. A VCO circuit that oscillates at a high frequency is generally composed of a differential circuit, and already has a differential structure in the VCO circuit 121 that is a clock signal source. The differential clock signal generated by the VCO circuit 121 is sequentially divided into ½ frequency by the frequency dividers 122 to 124. As a result, a 10 GHz differential clock signal and a 5 GHz differential clock signal are generated. These differential clock signals are supplied to multiplexers 125-127. The multiplexers 125 to 127 operate in synchronization with the supplied differential clock signal and multiplex the differential data signal to generate a differential data signal having a frequency 16 times that of the original differential data signal. .

  FIG. 11 is a diagram illustrating an example of the configuration of the 1/2 frequency divider. 1/2 divider 122 includes flip-flops 131 and 132. Each flip-flop 131 and 132 takes in and holds the differential data signals D and / D in synchronization with the differential clock signals CLK and CLKX. By cascading the flip-flops 131 and 132 and returning the output of the flip-flop 132 to the input of the flip-flop 131, a 1/2 frequency divider circuit can be configured.

FIG. 12 is a diagram showing an example of the configuration of the multiplexer shown in FIG. In FIG. 12, the clock signal CLK, the data signal D _IN1 , and the data signal D _IN2 are shown as a single signal line for the sake of simplicity of illustration, but all of them are a pair of signals that propagate through the two signal lines. It is a differential signal. The 2: 1 multiplexer 127 includes a 2: 1 selector 141 and latch circuits 142 to 146. Latch circuits 142 to 144 are cascaded to delay the differential data signal _DIN1 by two clock cycles. Latch circuits 145 and 146 are cascaded to delay differential data signal _DIN2 by one clock cycle. A differential data signal D _IN1 and the differential data signal D _IN2 after these delays, 2 operates in synchronization with the differential clock signal: a first selector 141, by selecting alternately every clock cycle, 2: Multiplexing of 1 is performed.

  In the configuration of the high-speed operation circuit as shown in FIGS. 10 to 12, the sense amplifier type flip-flop 51 shown in FIG. 3B can be used. For example, a sense amplifier type flip-flop 51 can be used for the flip-flops 131 and 132 in FIG. In FIG. 12, a sense amplifier type flip-flop 51 can be used for the flip-flop 147 corresponding to the latch circuits 142 and 143 and the flip-flop 148 corresponding to the latch circuits 145 and 146.

  As described above, a circuit that operates at a high frequency, that is, a frequency divider that divides a high-frequency clock signal or a multiplexer circuit that operates with a high-frequency clock signal is generally configured as a differential circuit. Is. In such a configuration, there is no problem in adopting a circuit configuration using a differential clock signal like the clocked amplifier 53 of the sense amplifier type flip-flop 51 shown in FIG.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows an example of a structure of a sense amplifier type flip-flop. It is a figure which shows an example of a structure of a symmetric slave latch. It is a figure which shows the principle structure of the flip-flop circuit which eliminated the asymmetry of delay time and shortened the delay time from an input to an output. It is a figure which shows an example of the circuit structure of a sense amplifier type flip-flop circuit. FIG. 4 is a timing chart showing the change timing of each signal in the sense amplifier type flip-flop circuit of FIG. FIG. 4 is a timing chart showing the change timing of each signal in the sense amplifier type flip-flop circuit of FIG. FIG. 4 is a diagram of a simulation result showing a difference in operating speed between the sense amplifier type flip-flop of FIG. 3A and the sense amplifier type flip-flop circuit of FIG. It is a figure which shows the modification of a symmetric slave latch. It is a figure which shows the modification of a symmetric slave latch. It is a figure which shows an example of a structure of a high-speed operation circuit. It is a figure which shows an example of a structure of a 1/2 frequency divider. It is a figure which shows an example of a structure of a multiplexer.

Explanation of symbols

10 clocked amplifier 25 keeper circuit 26 drive circuit 27 symmetric slave latch 50 sense amplifier type flip-flop circuit 51 sense amplifier type flip-flop circuit 53 clocked amplifier

Claims (5)

A master latch that outputs a third signal and a fourth signal that are complementary to each other in a complementary relationship with each other in accordance with the differential input signal and the differential clock signal. Clocked amplifier,
A flip-flop circuit comprising: a symmetric slave latch that outputs a first output signal and a second output signal that are complementary to each other in accordance with the first to fourth signals.   The clocked amplifier sets both the first signal and the third signal to the first level regardless of the signal value of the differential input signal in the first state of the differential clock signal, In the second state of the differential clock signal, one of the first signal and the third signal is set to the first level and the other is set to the second level according to the signal value of the differential input signal. The symmetric slave latch holds the logic state of the two output signals when the first signal and the third signal are both at the first level, and the first signal and the third signal When one of the signals is at the first level and the other is at the second level, the first output signal and the second output signal are set to levels according to the first signal and the third signal. 2. The flip-flop circuit according to claim 1, wherein The differential clock signal includes a first clock signal and a second clock signal having opposite phases, and the clocked amplifier includes:
A first clocked amplifier that operates in synchronization with the first clock signal of the differential clock signal and outputs the first signal and the third signal;
3. A second clocked amplifier that operates in synchronization with the second clock signal of the differential clock signal and outputs the second signal and the fourth signal. The flip-flop circuit described in 1. The symmetric slave latch is
A keeper circuit that receives the first to fourth signals as inputs and outputs the first output signal and the second output signal;
4. A drive circuit that simultaneously transitions the first output signal and the second output signal in accordance with the first to fourth signals, according to claim 1. Flip-flop circuit.   The keeper circuit includes a latch circuit, and the latch circuit does not exhibit a holding power that prevents a change in the signal when the drive circuit simultaneously changes the first output signal and the second output signal. The flip-flop circuit according to claim 4.

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