CN104506168A - Radiation-proof ultrahigh-speed triggering circuit and spaceflight ultrahigh-speed trigger - Google Patents
Radiation-proof ultrahigh-speed triggering circuit and spaceflight ultrahigh-speed trigger Download PDFInfo
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- CN104506168A CN104506168A CN201410756538.5A CN201410756538A CN104506168A CN 104506168 A CN104506168 A CN 104506168A CN 201410756538 A CN201410756538 A CN 201410756538A CN 104506168 A CN104506168 A CN 104506168A
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Abstract
The invention is applicable to the field of an integrated circuit and provides a radiation-proof ultrahigh-speed triggering circuit and a spaceflight ultrahigh-speed trigger. The radiation-proof ultrahigh-speed triggering circuit comprises a first sensitive amplifier, a second sensitive amplifier, a logic gate circuit and an RS (reset-set) latch, wherein the first and second sensitive amplifiers have double interlocking structures, data is stored into different nodes through two-way interlocking, the logic gate circuit carries out SEU (single particle upset) interference resistance processing on data in different nodes, and generates pre-charging signals, setting signals or resetting signals, the RS latch with a crossed coupling structure forms a phase inverter pair structure when receiving the pre-charging signals for realizing the data latching, or the output time delay avoidance is realized through a symmetrical structure during setting signal or resetting signal receiving. The radiation-proof ultrahigh-speed triggering circuit and the spaceflight ultrahigh-speed trigger have the advantages that the two sensitive amplifiers adopting the DICE structures are used as the front stage of the trigger for preventing the SEU influence, in addition, the front stage output is output to a later stage of RS latch through the logic gate operation, the ascending and descending edge difference-free output is realized through the two symmetrical RS latches with the crossed coupling structures, and the functions of high-speed data transmission is realized.
Description
Technical field
The invention belongs to integrated circuit fields, particularly relate to a kind of Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering and space flight ultrahigh speed trigger.
Background technology
In modern integrated circuits design, trigger plays key player in systems in which, especially when trigger is applied on aerospace equipment, except performance requiring more give prominence to, also have a very important point to be exactly need enough Radiation hardness, because under space radiation environment, device is easy to the impact being subject to single-particle inversion (SEU), the function of device probably will be allowed to be affected, the data of output error.
At present, trigger on aerospace equipment generally adopts trigger (the Sense-Amplifier-based Flip-Flop based on sense amplifier, SAFF), this trigger based on sense amplifier comprise latch-type sense amplifier 11 and RS latch 12 is formed, latch-type sense amplifier 11 adopts cross-couplings (interlocking) structure, latch the data after amplifying, the function resetted also is realized by precharge, its circuit structure is see Fig. 1, wherein, switching tube M4 and M8 is input pipe, switching tube M9 is switching clock signal pipe, switching tube M1 and M6 is preliminary filling fulgurite, the core of this circuit is switching tube M2 and M3, the inverter pair of pair of cross coupling (interlocking) that switching tube M5 and M7 is formed, the input of latch-type sense amplifier 11 is generally Differential Input, the differential signal of the low amplitude of oscillation that can be digital logic signal also can be, latch-type sense amplifier 11 realizes the function of sampling and resetting by the control of clock signal, when input clock CLK is low level, output Q end and Q_ end are all pulled to high level, realize reset operation, when input clock CLK signal is from low transition to high level, input signal is sampled, and amplified, eventually pass cross-linked four switching tube M2, M3, M5, M7 latches two and exports data, then RS latch 12 is outputted to.RS latch 12 comprises cross-linked two NAND doors, when clock signal clk is low, sense amplifier is pre-charge state, output (Q, Q_) be (1,1), then RS latch 12 is hold mode, and output remains unchanged, when clock signal clk from low become high hopping edge time, sense amplifier starts sampling input data D, when input (S_, R_) is (0,1) time, because gate is NAND gate, therefore output Q meeting output logic high level at once, output Q_ needs through a gate delay just output low level.
But, due to switching tube M2, M3 and switching tube M5, the cross-couplings latch structure that M7 is formed belongs to sensitive structure, in aerospace applications, because single-particle impacts the some bit flipping that the SEU effect brought causes node, cause the change of latch state in latch-type sense amplifier 11, there is the upset of key node, thus cause output error data, affect whole trigger normal function; And due to the trailing edge of output signal generally can a gate delay slower in rising edge, result in the asymmetric problem of rise and fall, and this gate delay also by the impact of RS latch 12 output load, can limit the operating rate of trigger.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering, be intended to solve traditional flip-flop be applied in aerospace environment, limited performance and be easily subject to single-particle inversion interference problem.
The embodiment of the present invention is achieved in that a kind of Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering, and described circuits for triggering comprise:
There is the first sense amplifier and second sense amplifier of double interlocking (DICE) structure, for by Bidirectional interlocking by deposit data at different node, two inputs of described first sense amplifier are corresponding with two inputs of described second sense amplifier to be connected, the clock end of described first sense amplifier is connected with the clock end of described second sense amplifier, first forward output of described first sense amplifier is connected with the first forward output of described second sense amplifier, first inverse output terminal of described first sense amplifier is connected with the first inverse output terminal of described second sense amplifier, second forward output of described first sense amplifier is connected with the second forward output of described second sense amplifier, second inverse output terminal of described first sense amplifier is connected with the second inverse output terminal of described second sense amplifier,
Logic gates, for carrying out anti-single particle overturn interference process to the data of different node, generate precharging signal, asserts signal or reset signal, the first input end of described logic gates and described first, second forward output of the second sense amplifier connects, second input of described logic gates and described first, first forward output of the second sense amplifier connects, 3rd input of described logic gates and described first, first inverse output terminal of the second sense amplifier connects, the four-input terminal of described logic gates and described first, second inverse output terminal of the second sense amplifier connects,
There is the RS latch of cross coupling structure, for when receiving precharging signal, form inverter to structure, with latch data, or, when receiving asserts signal or reset signal, realize exporting without time delay by symmetrical structure, the S_ input of described RS latch is connected with the first output of described logic gates, and the R_ input of described RS latch is connected with the second output of described logic gates, and two outputs of described RS latch are the output of described circuits for triggering;
Described double interlocking structure, by least eight switching tube coupling interactions, forms two inverters to formation.
Another object of the embodiment of the present invention is, provides a kind of space flight ultrahigh speed trigger adopting above-mentioned Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering.
The embodiment of the present invention adopts first of DICE structure, second sense amplifier is as the prime of trigger, the problem can also effectively preventing single-particle inversion to bring while the amplification realizing latch-type sense amplifier itself and reset function, and further by the output of two sense amplifiers by exporting to the RS latch of rear stage after logical gate operations, this RS latch is by first of full symmetric structure, second exports branch road, solve output signal rise and fall along the problem do not waited, and transmission delay can be reduced by the size reasonably adjusting crucial metal-oxide-semiconductor, strengthen the output driving force of whole high speed flip flop.And it is fast that this trigger has speed, and the feature that performance is good, effectively can prevent single-particle inversion, especially meets the characteristics of demand for ultrahigh speed trigger in field of aerospace technology.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the existing trigger based on sense amplifier;
The structure chart of the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that Fig. 2 provides for the embodiment of the present invention;
The exemplary circuit figure of the sense amplifier of DICE structure is adopted in the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that Fig. 3 provides for the embodiment of the present invention;
The exemplary circuit figure of logic gates in the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that Fig. 4 provides for the embodiment of the present invention;
The exemplary circuit figure of RS latch in the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that Fig. 5 provides for the embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each execution mode of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
The embodiment of the present invention by Bidirectional interlocking by deposit data at different node, anti-single particle overturn interference process is carried out to the data of different node, generate precharging signal, asserts signal or reset signal, again by logical operation, anti-single particle overturn interference process is carried out to the data of different node, and realize exporting without time delay by the RS latch with cross coupling structure.
Below in conjunction with specific embodiment, realization of the present invention is described in detail:
Fig. 2 shows the structure of the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention.
As one embodiment of the invention, these Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering can be applied in any space flight ultrahigh speed trigger, and these a kind of Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering comprise:
There is the first sense amplifier 21A and the second sense amplifier 21B of double interlocking structure, for by Bidirectional interlocking by deposit data at different node, two inputs of the first sense amplifier 21A are corresponding with two inputs of the second sense amplifier 21B to be connected, the clock end of the first sense amplifier 21A is connected with the clock end of the second sense amplifier 21B, the first forward output of the first sense amplifier 21A is connected with the first forward output of the second sense amplifier 21B, first inverse output terminal of the first sense amplifier 21A is connected with first inverse output terminal of the second sense amplifier 21B, the second forward output of the first sense amplifier 21A is connected with the second forward output of the second sense amplifier 21B, second inverse output terminal of the first sense amplifier 21A is connected with second inverse output terminal of the second sense amplifier 21B,
In embodiments of the present invention, the double interlocking structure that the first sense amplifier 21A and the second sense amplifier 21B is formed is DICE structure, by dual symmetrical structure by deposit data at different node.
Logic gates 22, for carrying out anti-single particle overturn interference process to the data of different node, generate precharging signal, asserts signal or reset signal, the first input end of logic gates 22 and first, the second forward output of the second sense amplifier 21B connects, second input of logic gates 22 and first, the first forward output of the second sense amplifier 21B connects, 3rd input of logic gates 22 and first, first inverse output terminal of the second sense amplifier 21B connects, the four-input terminal and first of logic gates 22, second inverse output terminal of the second sense amplifier 21B connects,
There is the RS latch 23 of cross coupling structure, for when receiving precharging signal, form inverter to structure, with latch data, or, when receiving asserts signal or reset signal, realize exporting without time delay by symmetrical structure, the S_ input of RS latch 23 is connected with the first output of logic gates 22, and the R_ input of RS latch 23 is connected with the second output of logic gates 22, and two outputs of RS latch 23 are the output of circuits for triggering;
Double interlocking structure, by least eight switching tube coupling interactions, forms two inverters to formation.
The embodiment of the present invention adopts first of DICE structure, second sense amplifier is as the prime of trigger, the problem can also effectively preventing single-particle inversion to bring while the amplification realizing latch-type sense amplifier itself and reset function, and further by the output of two sense amplifiers by exporting to the RS latch of rear stage after logical gate operations, this RS latch is by first of full symmetric structure, second exports branch road, solve output signal rise and fall along the problem do not waited, ultrahigh speed can be realized trigger, and transmission delay can be reduced by the size reasonably adjusting crucial metal-oxide-semiconductor, strengthen the output driving force of whole high speed flip flop.
It is fast that the circuits for triggering that the embodiment of the present invention provides and trigger have speed, and the feature that performance is good, effectively can prevent single-particle inversion, especially meets the characteristics of demand for ultrahigh speed trigger in field of aerospace technology.
Fig. 3 shows the exemplary circuit adopting the sense amplifier of DICE structure in the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention.
As one embodiment of the invention, the first sense amplifier 21A comprises:
Switching tube M1 is to switching tube M14;
The control end of switching tube M1 is the clock end of the first sense amplifier 21A, the input of switching tube M1 connects supply voltage, the output of switching tube M1 is the first forward output of the first sense amplifier 21A, the input of switching tube M6 connects supply voltage, the control end of switching tube M6 is first inverse output terminal of the first sense amplifier 21A, the output of switching tube M6 is connected with the input of switching tube M8, the control end of switching tube M8 is the first sense amplifier 21A second inverse output terminal, the output of switching tube M8 is connected with the output of switching tube M1 and the input of switching tube M10 simultaneously, the control end of switching tube M10 is first inverse output terminal of the first sense amplifier 21A, the output of switching tube M10 is connected with the input of switching tube M12, the control end of switching tube M12 is second inverse output terminal of the first sense amplifier 21A, the output of switching tube M12 is connected with the input of switching tube M4 and the input of switching tube M14 simultaneously, the control end of switching tube M4 is the positive input of the first sense amplifier 21A, the output of switching tube M4 is connected with the input of switching tube M5, the control end of switching tube M5 is the clock end of the first sense amplifier 21A, the output head grounding of switching tube M5, the input of switching tube M5 is also connected with the output of switching tube M3, the control end of switching tube M3 is the reverse input end of the first sense amplifier 21A, the input of switching tube M3 is connected with the output of switching tube M14 and the output of switching tube M13 simultaneously, the control end of switching tube M14 connects supply voltage, the control end of switching tube M13 is the second forward output of the first sense amplifier 21A, the input of switching tube M13 is connected with the output of switching tube M11, the control end of switching tube M11 is the first forward output of the first sense amplifier 21A, the input of switching tube M11 is connected with the output of switching tube M9 and the output of switching tube M2 simultaneously, the control end of switching tube M9 is the second forward output of the first sense amplifier 21A, the input of switching tube M9 is connected with the output of switching tube M7, the control end of switching tube M7 is the first forward output of the first sense amplifier 21A, the input of switching tube M7 is connected supply voltage with the input of switching tube M2 simultaneously, the control end of switching tube M2 is the clock end of the first sense amplifier 21A, the output of switching tube M2 is first inverse output terminal of the first sense amplifier 21A.
As one embodiment of the present invention, switching tube M1, switching tube M2, switching tube M6 are P type metal-oxide-semiconductor to switching tube M9, the source electrode of P type metal-oxide-semiconductor is the input of switching tube, and the drain electrode of P type metal-oxide-semiconductor is the output of switching tube, and the grid of P type metal-oxide-semiconductor is the control end of switching tube;
Switching tube M3, switching tube M4, switching tube M5, switching tube M10 are N-type metal-oxide-semiconductor to switching tube M14, and the drain electrode of N-type metal-oxide-semiconductor is the input of switching tube, and the source electrode of N-type metal-oxide-semiconductor is the output of switching tube, and the grid of N-type metal-oxide-semiconductor is the control end of switching tube.
Second sense amplifier 22B comprises:
Switching tube m1 is to switching tube m14;
The control end of switching tube m1 is the clock end of the second sense amplifier 21B, the input of switching tube m1 connects supply voltage, the output of switching tube m1 is the second forward output of the second sense amplifier 21B, the input of switching tube m6 connects supply voltage, the control end of switching tube m6 is second inverse output terminal of the second sense amplifier 21B, the output of switching tube m6 is connected with the input of switching tube m8, the control end of switching tube m8 is the second sense amplifier 21B first inverse output terminal, the output of switching tube m8 is connected with the output of switching tube m1 and the input of switching tube m10 simultaneously, the control end of switching tube m10 is second inverse output terminal of the second sense amplifier 21B, the output of switching tube m10 is connected with the input of switching tube m12, the control end of switching tube m12 is first inverse output terminal of the second sense amplifier 21B, the output of switching tube m12 is connected with the input of switching tube m4 and the input of switching tube m14 simultaneously, the control end of switching tube m4 is the positive input of the second sense amplifier 21B, the output of switching tube m4 is connected with the input of switching tube m5, the control end of switching tube m5 is the clock end of the first sense amplifier 21A, the output head grounding of switching tube m5, the input of switching tube m5 is also connected with the output of switching tube m3, the control end of switching tube m3 is the reverse input end of the second sense amplifier 21B, the input of switching tube m3 is connected with the output of switching tube m14 and the output of switching tube m13 simultaneously, the control end of switching tube m14 connects supply voltage, the control end of switching tube m13 is the first forward output of the second sense amplifier 21B, the input of switching tube m13 is connected with the output of switching tube m11, the control end of switching tube m11 is the second forward output of the second sense amplifier 21B, the input of switching tube m11 is connected with the output of switching tube m9 and the output of switching tube m2 simultaneously, the control end of switching tube m9 is the first forward output of the first sense amplifier 21A, the input of switching tube m9 is connected with the output of switching tube m7, the control end of switching tube m7 is the second forward output of the second sense amplifier 21B, the input of switching tube m7 is connected supply voltage with the input of switching tube m2 simultaneously, the control end of switching tube m2 is the clock end of the second sense amplifier 21B, the output of switching tube m2 is first inverse output terminal of the second sense amplifier 21B.
As one embodiment of the present invention, switching tube m1, switching tube m2, switching tube m6 are P type metal-oxide-semiconductor to switching tube m9, the source electrode of P type metal-oxide-semiconductor is the input of switching tube, and the drain electrode of P type metal-oxide-semiconductor is the output of switching tube, and the grid of P type metal-oxide-semiconductor is the control end of switching tube;
Switching tube m3, switching tube m4, switching tube m5, switching tube m10 are N-type metal-oxide-semiconductor to switching tube m14, and the drain electrode of N-type metal-oxide-semiconductor is the input of switching tube, and the source electrode of N-type metal-oxide-semiconductor is the output of switching tube, and the grid of N-type metal-oxide-semiconductor is the control end of switching tube.
In embodiments of the present invention, sense amplifier 21A, 21B of two double interlocking structures, the input of these two sense amplifiers is identical, all input data D and D_ and clock signal clk, the data of the first sense amplifier 21A are exported by the first forward output terminals A 1 and the first inverse output terminal B1, the data of the second sense amplifier 21B are exported by the second forward output terminals A 2 and the second inverse output terminal B2, these two sense amplifiers respectively by each eight metal-oxide-semiconductors of M6 ~ M13 and m6 ~ m13 as the metal-oxide-semiconductor of cross coupling structure.
For these two sense amplifiers, compared with traditional sense amplifier, adopt two structures and measure-alike switching tube (switching tube M6 and switching tube M8, switching tube M7 and switching tube M9, switching tube M10 and switching tube M12, switching tube M11 and switching tube M13, and switching tube m6 and switching tube m8, switching tube m7 and switching tube m9, switching tube m10 and switching tube m12, switching tube m11 and switching tube m13) replace a switching tube of the prior art, simultaneously at A, B (a, b) node connects the NMOS tube M14 that grid meet supply voltage VDD, to realize the Design of Reinforcement of anti-single particle, embodiment specifically in conjunction with logic gates is described in detail.
Fig. 4 shows the exemplary circuit of logic gates in the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention.
As one embodiment of the invention, logic gates 22 comprises:
First or door, first or two inputs of door be respectively first, second input of logic gates 22, first or the output of door be the first output of logic gates 22;
Second or door, second or two inputs of door be respectively logic gates 22 the 3rd, four-input terminal, second or the output of door be the second output of logic gates 22.
In embodiments of the present invention, the output of two sense amplifiers is respectively A1, B1 and A2, B2, wherein output terminals A 1 and A2 are exported by one or the S_ end exported behind the door as rear class RS latch, and the R_ end that output B1 and B2 is rear class RS latch by or output behind the door exports.
The signal of output terminals A 1, A2 is identical under normal circumstances, and the signal of output B1, B2 is identical, S_=A1+A2, R_=B1+B2, is at this time normal output;
If it is occur in pre-charging stage that single-particle impacts, clock signal clk is low, to the A1 in the first sense amplifier 21A, one or two current potential of B1 node causes upset, current potential is made to be 0, at this moment, do not change owing to exporting in the second sense amplifier 21B, so S_=A1+A2=1, R_=B1+B2=1, also be do not change, until preliminary filling fulgurite M1 and M2 draws high circuit two current potentials of the first sense amplifier 21A recover normal, such trigger volume exports and is not interfered, it is identical that kindred circumstances second sense amplifier 21B is subject to impact condition,
If when single-particle impacts that to occur in clock signal be high, suppose the signal (A of normal output latch, B) be (1, 0), if sense amplifier due to single-particle inversion B1 output switching activity be high potential, then because S_=A1+A2, R_=B1+B2, (S_, R_) then (1 can be become, 1), at this moment relative to rear class RS latch be namely the instruction of " maintenance ", so it is impregnable for exporting, because now switching tube M11 and switching tube M13 pipe are opened, the current potential of the B1 point raised can along with M11, M13, M14, M4 or M11, M13, these two branch road electric discharges of M3 return to electronegative potential, one is always had to open because M3 pipe is managed with M4, and M14 pipe is often opened.When A1 becomes 0 from 1, time, because export S_=A1+A2, R_=B1+B2, (S_, R_) or (1,0), the output of trigger is unaffected, and opening because of M6 and M8, and the current potential of A1 can be retracted as height gradually.
The misdata of the output that therefore can effectively prevent single-particle inversion to bring.
The embodiment of the present invention adopts first of DICE structure, second sense amplifier is as the prime of trigger, the problem can also effectively preventing single-particle inversion to bring while the amplification realizing latch-type sense amplifier itself and reset function, and further by the output of two sense amplifiers by exporting to the RS latch of rear stage after logical gate operations, ultrahigh speed can be realized trigger, this Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering speed is fast, performance is good, effectively can prevent single-particle inversion, especially the characteristics of demand for ultrahigh speed trigger in field of aerospace technology is met.
Fig. 5 shows the exemplary circuit of RS latch in the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention.
As one embodiment of the invention, RS latch 23 comprises:
First of symmetrical structure exports branch road 23A and second and exports branch road 23B;
First first input end exporting branch road 23A is connected with the second output exporting branch road 23B, and the first the second output exporting branch road 23A is the S_ input of RS latch 23, and the first output exporting branch road 23A is the inverse output terminal of RS latch 23;
Second first input end exporting branch road 23B is connected with the first output exporting branch road 23A, and second exports second output of branch road 23B and the R_ input being RS latch 23, and the second output exporting branch road 23B is the forward output of RS latch 23.
As one embodiment of the present invention, first exports branch road 23A comprises:
Switching tube M21 is to switching tube M26, and the first inverter I1;
The input of switching tube M21 connects supply voltage, the control end of switching tube M21 is second input of the first output branch road 23A, the output of switching tube M21 is that the first input end of the first output branch road 23A is connected with the control end of switching tube M22, the input of switching tube M22 connects supply voltage, the output of switching tube M22 is connected with the input of switching tube M24, the control end of switching tube M24 is connected with the output of the first inverter and the control end of switching tube M26 simultaneously, the output of switching tube M24 is that the output of the first output branch road 23A is connected with the input of switching tube M26, the output head grounding of switching tube M26, the input of the first inverter I1 is connected with the control end of switching tube M21, the output of switching tube M21 is also connected with the input of switching tube M23, the control end of switching tube M23 is connected with the output of switching tube M24, the output of switching tube M23 is connected with the input of switching tube M25, the control end of switching tube M25 is connected with the control end of switching tube M21, the output head grounding of switching tube M25,
Second exports branch road 23B comprises:
Switching tube M27 is to switching tube M32, and the second inverter I2;
The input of switching tube M27 connects supply voltage, the control end of switching tube M27 is second input of the second output branch road 23B, the output of switching tube M27 is that the first input end of the second output branch road 23B is connected with the control end of switching tube M28, the input of switching tube M28 connects supply voltage, the output of switching tube M28 is connected with the input of switching tube M30, the control end of switching tube M30 is connected with the output of the second inverter I2 and the control end of switching tube M32 simultaneously, the output of switching tube M30 is that the output of the second output branch road 23B is connected with the input of switching tube M32, the output head grounding of switching tube M32, the input of the second inverter I2 is connected with the control end of switching tube M27, the input of switching tube M29 is connected with the output of switching tube M27, the control end of switching tube M29 is connected with the output of switching tube M30, the output of switching tube M29 is connected with the input of switching tube M31, the control end of switching tube M31 is connected with the control end of switching tube M27, the output head grounding of switching tube M31.
As one embodiment of the present invention, switching tube M21, switching tube M22, switching tube M24, switching tube M27, switching tube M28, switching tube M30 are P type metal-oxide-semiconductor, the source electrode of P type metal-oxide-semiconductor is the input of switching tube, the drain electrode of P type metal-oxide-semiconductor is the output of switching tube, and the grid of P type metal-oxide-semiconductor is the control end of switching tube;
Switching tube M23, switching tube M25, switching tube M26, switching tube M29, switching tube M31, switching tube M32 are N-type metal-oxide-semiconductor, the drain electrode of N-type metal-oxide-semiconductor is the input of switching tube, the source electrode of N-type metal-oxide-semiconductor is the output of switching tube, and the grid of N-type metal-oxide-semiconductor is the control end of switching tube.
In embodiments of the present invention, RS latch 23 be input as S_, R_, wherein, first, second exports structure of branch road is full symmetric, and the output of one of them is again as another input, i.e. cross coupling structure.Switching tube M2, switching tube M3, and switching tube M8, switching tube M9 is as the latch pipe of data, and switching tube M1, switching tube M6 and switching tube M7, switching tube M12, for exporting driving tube, controls output driving current.
Its functional realiey process is described below: because the output of pre-amplifier is two kinds of patterns, a kind of precharging signal that exports enters precharge mode, and another kind of output set or reset signal enter set or reset mode.
When pre-amplifier is in precharge mode, the input S_ of RS latch 23, R_ are high level, now switching tube M1, switching tube M5, switching tube M7, switching tube M12 closes, switching tube M4, switching tube M5, switching tube M10, switching tube M11 pipe is opened, and is equivalent to switching tube M2 and switching tube M3, switching tube M9 and switching tube M8 constitutes two to cross-linked inverter pair, as the effect of latch data, in pre-charging stage, during the input of data, not affect the operating state of latch below.
When pre-amplifier is in mode of operation, if the input S_ of RS latch 23, when R_ is respectively low and high level, now switching tube M1 opens and charges to Q node, switching tube M5 opens, Q_ node is discharged, switching tube M8 slowly opens until Q_ drops to low level in this process, Q is due to switching tube M10, switching tube M8 conducting and be stabilized to high level, this process is full symmetric structure because of two output branch roads, so exporting rising edge is consistent with the time of trailing edge, would not has like this and export the asymmetric problem of time delay.
Further, because when state changes, switching tube M1, switching tube M6 and switching tube M7, switching tube M12 be conducting one respectively only, if can cross-linked switching tube M2 and switching tube M3, the suitable point that the size of switching tube M9 and switching tube M8 is done, the speed transformed just can be made significantly to promote, then make the speed of trigger be greatly enhanced, and the size suitably adjusting driving tube can also improve the driving force of output further.
Another object of the embodiment of the present invention is, provides a kind of space flight ultrahigh speed trigger adopting above-mentioned Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering.
The embodiment of the present invention adopts first of DICE structure, second sense amplifier is as the prime of trigger, the problem can also effectively preventing single-particle inversion to bring while the amplification realizing latch-type sense amplifier itself and reset function, and further by the output of two sense amplifiers by exporting to the RS latch of rear stage after logical gate operations, this RS latch is by first of full symmetric structure, second exports branch road, solve output signal rise and fall along the problem do not waited, ultrahigh speed can be realized trigger, and transmission delay can be reduced by the size reasonably adjusting crucial metal-oxide-semiconductor, strengthen the output driving force of whole high speed flip flop.
It is fast that the circuits for triggering that the embodiment of the present invention provides and trigger have speed, and the feature that performance is good, effectively can prevent single-particle inversion, especially meets the characteristics of demand for ultrahigh speed trigger in field of aerospace technology.
These are only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering, is characterized in that, described circuits for triggering comprise:
There is the first sense amplifier and second sense amplifier of double interlocking structure, for by Bidirectional interlocking by deposit data at different node, two inputs of described first sense amplifier are corresponding with two inputs of described second sense amplifier to be connected, the clock end of described first sense amplifier is connected with the clock end of described second sense amplifier, first forward output of described first sense amplifier is connected with the first forward output of described second sense amplifier, first inverse output terminal of described first sense amplifier is connected with the first inverse output terminal of described second sense amplifier, second forward output of described first sense amplifier is connected with the second forward output of described second sense amplifier, second inverse output terminal of described first sense amplifier is connected with the second inverse output terminal of described second sense amplifier,
Logic gates, for carrying out anti-single particle overturn interference process to the data of different node, generate precharging signal, asserts signal or reset signal, the first input end of described logic gates and described first, second forward output of the second sense amplifier connects, second input of described logic gates and described first, first forward output of the second sense amplifier connects, 3rd input of described logic gates and described first, first inverse output terminal of the second sense amplifier connects, the four-input terminal of described logic gates and described first, second inverse output terminal of the second sense amplifier connects,
There is the RS latch of cross coupling structure, for when receiving precharging signal, form inverter to structure, with latch data, or, when receiving asserts signal or reset signal, realize exporting without time delay by symmetrical structure, the S_ input of described RS latch is connected with the first output of described logic gates, and the R_ input of described RS latch is connected with the second output of described logic gates, and two outputs of described RS latch are the output of described circuits for triggering;
Described double interlocking structure, by least eight switching tube coupling interactions, forms two inverters to formation.
2. circuits for triggering as claimed in claim 1, it is characterized in that, described first sense amplifier comprises:
Switching tube M1 is to switching tube M14;
The control end of described switching tube M1 is the clock end of described first sense amplifier, the input of described switching tube M1 connects supply voltage, the output of described switching tube M1 is the first forward output of described first sense amplifier, the input of described switching tube M6 connects supply voltage, the control end of described switching tube M6 is the first inverse output terminal of described first sense amplifier, the output of described switching tube M6 is connected with the input of described switching tube M8, the control end of described switching tube M8 is described first sense amplifier second inverse output terminal, the output of described switching tube M8 is connected with the output of described switching tube M1 and the input of described switching tube M10 simultaneously, the control end of described switching tube M10 is the first inverse output terminal of described first sense amplifier, the output of described switching tube M10 is connected with the input of described switching tube M12, the control end of described switching tube M12 is the second inverse output terminal of described first sense amplifier, the output of described switching tube M12 is connected with the input of described switching tube M4 and the input of described switching tube M14 simultaneously, the control end of described switching tube M4 is the positive input of described first sense amplifier, the output of described switching tube M4 is connected with the input of described switching tube M5, the control end of described switching tube M5 is the clock end of described first sense amplifier, the output head grounding of described switching tube M5, the input of described switching tube M5 is also connected with the output of described switching tube M3, the control end of described switching tube M3 is the reverse input end of described first sense amplifier, the input of described switching tube M3 is connected with the output of described switching tube M14 and the output of described switching tube M13 simultaneously, the control end of described switching tube M14 connects supply voltage, the control end of described switching tube M13 is the second forward output of described first sense amplifier, the input of described switching tube M13 is connected with the output of described switching tube M11, the control end of described switching tube M11 is the first forward output of described first sense amplifier, the input of described switching tube M11 is connected with the output of described switching tube M9 and the output of described switching tube M2 simultaneously, the control end of described switching tube M9 is the second forward output of described first sense amplifier, the input of described switching tube M9 is connected with the output of described switching tube M7, the control end of described switching tube M7 is the first forward output of described first sense amplifier, the input of described switching tube M7 is connected supply voltage with the input of described switching tube M2 simultaneously, the control end of described switching tube M2 is the clock end of described first sense amplifier, the output of described switching tube M2 is the first inverse output terminal of described first sense amplifier.
3. circuits for triggering as claimed in claim 2, it is characterized in that, described switching tube M1, described switching tube M2, described switching tube M6 are P type metal-oxide-semiconductor to described switching tube M9, the source electrode of described P type metal-oxide-semiconductor is the input of described switching tube, the drain electrode of described P type metal-oxide-semiconductor is the output of described switching tube, and the grid of described P type metal-oxide-semiconductor is the control end of described switching tube;
Described switching tube M3, described switching tube M4, described switching tube M5, described switching tube M10 are N-type metal-oxide-semiconductor to described switching tube M14, the drain electrode of described N-type metal-oxide-semiconductor is the input of described switching tube, the source electrode of described N-type metal-oxide-semiconductor is the output of described switching tube, and the grid of described N-type metal-oxide-semiconductor is the control end of described switching tube.
4. circuits for triggering as claimed in claim 1, it is characterized in that, described second sense amplifier comprises:
Switching tube m1 is to switching tube m14;
The control end of described switching tube m1 is the clock end of described second sense amplifier, the input of described switching tube m1 connects supply voltage, the output of described switching tube m1 is the second forward output of described second sense amplifier, the input of described switching tube m6 connects supply voltage, the control end of described switching tube m6 is the second inverse output terminal of described second sense amplifier, the output of described switching tube m6 is connected with the input of described switching tube m8, the control end of described switching tube m8 is described second sense amplifier first inverse output terminal, the output of described switching tube m8 is connected with the output of described switching tube m1 and the input of described switching tube m10 simultaneously, the control end of described switching tube m10 is the second inverse output terminal of described second sense amplifier, the output of described switching tube m10 is connected with the input of described switching tube m12, the control end of described switching tube m12 is the first inverse output terminal of described second sense amplifier, the output of described switching tube m12 is connected with the input of described switching tube m4 and the input of described switching tube m14 simultaneously, the control end of described switching tube m4 is the positive input of described second sense amplifier, the output of described switching tube m4 is connected with the input of described switching tube m5, the control end of described switching tube m5 is the clock end of described first sense amplifier, the output head grounding of described switching tube m5, the input of described switching tube m5 is also connected with the output of described switching tube m3, the control end of described switching tube m3 is the reverse input end of described second sense amplifier, the input of described switching tube m3 is connected with the output of described switching tube m14 and the output of described switching tube m13 simultaneously, the control end of described switching tube m14 connects supply voltage, the control end of described switching tube m13 is the first forward output of described second sense amplifier, the input of described switching tube m13 is connected with the output of described switching tube m11, the control end of described switching tube m11 is the second forward output of described second sense amplifier, the input of described switching tube m11 is connected with the output of described switching tube m9 and the output of described switching tube m2 simultaneously, the control end of described switching tube m9 is the first forward output of described first sense amplifier, the input of described switching tube m9 is connected with the output of described switching tube m7, the control end of described switching tube m7 is the second forward output of described second sense amplifier, the input of described switching tube m7 is connected supply voltage with the input of described switching tube m2 simultaneously, the control end of described switching tube m2 is the clock end of described second sense amplifier, the output of described switching tube m2 is the first inverse output terminal of described second sense amplifier.
5. circuits for triggering as claimed in claim 4, it is characterized in that, described switching tube m1, described switching tube m2, described switching tube m6 are P type metal-oxide-semiconductor to described switching tube m9, the source electrode of described P type metal-oxide-semiconductor is the input of described switching tube, the drain electrode of described P type metal-oxide-semiconductor is the output of described switching tube, and the grid of described P type metal-oxide-semiconductor is the control end of described switching tube;
Described switching tube m3, described switching tube m4, described switching tube m5, described switching tube m10 are N-type metal-oxide-semiconductor to described switching tube m14, the drain electrode of described N-type metal-oxide-semiconductor is the input of described switching tube, the source electrode of described N-type metal-oxide-semiconductor is the output of described switching tube, and the grid of described N-type metal-oxide-semiconductor is the control end of described switching tube.
6. circuits for triggering as claimed in claim 1, it is characterized in that, described logic gates comprises:
First or door, described first or two inputs of door be respectively first, second input of described logic gates, described first or the output of door be the first output of described logic gates;
Second or door, described second or two inputs of door be respectively described logic gates the 3rd, four-input terminal, described second or the output of door be the second output of described logic gates.
7. circuits for triggering as claimed in claim 1, it is characterized in that, described RS latch comprises:
First of symmetrical structure exports branch road and second and exports branch road;
Described first first input end exporting branch road is connected with the described second output exporting branch road, described first the second output exporting branch road is the S_ input of described RS latch, and the described first output exporting branch road is the inverse output terminal of described RS latch;
Described second first input end exporting branch road is connected with the described first output exporting branch road, described second exports the second output of branch road and the R_ input being described RS latch, and the described second output exporting branch road is the forward output of described RS latch.
8. circuits for triggering as claimed in claim 7, is characterized in that, described first exports branch road comprises:
Switching tube M21 is to switching tube M26, and the first reverser;
The input of described switching tube M21 connects supply voltage, the control end of described switching tube M21 is the described first the second input exporting branch road, the output of described switching tube M21 is that the described first first input end exporting branch road is connected with the control end of described switching tube M22, the input of described switching tube M22 connects supply voltage, the output of described switching tube M22 is connected with the input of described switching tube M24, the control end of described switching tube M24 is connected with the output of described first inverter and the control end of described switching tube M26 simultaneously, the output of described switching tube M24 is that the described first output exporting branch road is connected with the input of described switching tube M26, the output head grounding of described switching tube M26, the input of described first reverser is connected with the control end of described switching tube M21, the output of described switching tube M21 is also connected with the input of described switching tube M23, the control end of described switching tube M23 is connected with the output of described switching tube M24, the output of described switching tube M23 is connected with the input of described switching tube M25, the control end of described switching tube M25 is connected with the control end of described switching tube M21, the output head grounding of described switching tube M25,
Described second exports branch road comprises:
Switching tube M27 is to switching tube M32, and the second inverter;
The input of described switching tube M27 connects supply voltage, the control end of described switching tube M27 is the described second the second input exporting branch road, the output of described switching tube M27 is that the described second first input end exporting branch road is connected with the control end of described switching tube M28, the input of described switching tube M28 connects supply voltage, the output of described switching tube M28 is connected with the input of described switching tube M30, the control end of described switching tube M30 is connected with the output of described second inverter and the control end of described switching tube M32 simultaneously, the output of described switching tube M30 is that the described second output exporting branch road is connected with the input of described switching tube M32, the output head grounding of described switching tube M32, the input of described second inverter is connected with the control end of described switching tube M27, the input of described switching tube M29 is connected with the output of described switching tube M27, the control end of described switching tube M29 is connected with the output of described switching tube M30, the output of described switching tube M29 is connected with the input of described switching tube M31, the control end of described switching tube M31 is connected with the control end of described switching tube M27, the output head grounding of described switching tube M31.
9. circuits for triggering as claimed in claim 7, it is characterized in that, described switching tube M21, described switching tube M22, described switching tube M24, described switching tube M27, described switching tube M28, described switching tube M30 are P type metal-oxide-semiconductor, the source electrode of described P type metal-oxide-semiconductor is the input of described switching tube, the drain electrode of described P type metal-oxide-semiconductor is the output of described switching tube, and the grid of described P type metal-oxide-semiconductor is the control end of described switching tube;
Described switching tube M23, described switching tube M25, described switching tube M26, described switching tube M29, described switching tube M31, described switching tube M32 are N-type metal-oxide-semiconductor, the drain electrode of described N-type metal-oxide-semiconductor is the input of described switching tube, the source electrode of described N-type metal-oxide-semiconductor is the output of described switching tube, and the grid of described N-type metal-oxide-semiconductor is the control end of described switching tube.
10. a space flight ultrahigh speed trigger, is characterized in that, described space flight ultrahigh speed trigger comprises the Flouride-resistani acid phesphatase ultrahigh speed circuits for triggering as described in any one of claim 1 to 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105788624A (en) * | 2016-02-23 | 2016-07-20 | 北京大学（天津滨海）新代信息技术研究院 | Novel high-sensitivity sensitiveness amplifier with output edges symmetrical |
| CN105915222A (en) * | 2015-12-11 | 2016-08-31 | 中国航空工业集团公司西安航空计算技术研究所 | High-sensitivity high-speed sampler circuit |
| CN107425832A (en) * | 2017-09-15 | 2017-12-01 | 启攀微电子（上海）有限公司 | It is a kind of can two-way admittance current limliting load switch |
| CN108092647A (en) * | 2016-11-23 | 2018-05-29 | 三星电子株式会社 | Trigger |
| CN111211771A (en) * | 2020-02-26 | 2020-05-29 | 中国科学院微电子研究所 | High-speed data buffer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105915222A (en) * | 2015-12-11 | 2016-08-31 | 中国航空工业集团公司西安航空计算技术研究所 | High-sensitivity high-speed sampler circuit |
| CN105788624A (en) * | 2016-02-23 | 2016-07-20 | 北京大学（天津滨海）新代信息技术研究院 | Novel high-sensitivity sensitiveness amplifier with output edges symmetrical |
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| CN108092647A (en) * | 2016-11-23 | 2018-05-29 | 三星电子株式会社 | Trigger |
| CN108092647B (en) * | 2016-11-23 | 2023-05-26 | 三星电子株式会社 | Trigger device |
| CN107425832A (en) * | 2017-09-15 | 2017-12-01 | 启攀微电子（上海）有限公司 | It is a kind of can two-way admittance current limliting load switch |
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| CN111211771A (en) * | 2020-02-26 | 2020-05-29 | 中国科学院微电子研究所 | High-speed data buffer |
| CN111211771B (en) * | 2020-02-26 | 2023-10-24 | 中国科学院微电子研究所 | High-speed data buffer |
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