CN104506168B - A kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit and space flight ultrahigh speed trigger - Google Patents
A kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit and space flight ultrahigh speed trigger Download PDFInfo
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- CN104506168B CN104506168B CN201410756538.5A CN201410756538A CN104506168B CN 104506168 B CN104506168 B CN 104506168B CN 201410756538 A CN201410756538 A CN 201410756538A CN 104506168 B CN104506168 B CN 104506168B
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Abstract
The present invention is applied to integrated circuit fields, there is provided a kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit and space flight ultrahigh speed trigger, the circuit include：First, second sense amplifier with double interlocking structure, different nodes are placed the data in by Bidirectional interlocking；Logic gates, anti-single particle upset interference processing, generation precharging signal, set signal or reset signal are carried out to the data of different nodes；RS latch with cross coupling structure, when receiving precharging signal, phase inverter is formed to structure, with latch data, or when receiving set signal or reset signal, realizes that output is no-delay by symmetrical structure.The present invention uses two sense amplifiers of DICE structures to be influenceed as the prime of trigger to prevent SEU, and prime output is exported to the RS latch to rear stage after logical gate operations, realize that rise and fall export along indifference by two symmetrical RS latch with cross coupling structure, realize the function of high speed propagation data.
Description
Technical field
The invention belongs to integrated circuit fields, more particularly to a kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit and space flight ultrahigh speed to touch
Send out device.
Background technology
In modern integrated circuits design, trigger plays key player in systems, especially when trigger is applied
When on aerospace equipment, in addition to requiring more prominent in performance, it is important that also one is exactly to need enough
Radiation hardness because under space radiation environment, device is highly susceptible to single-particle inversion (SEU) influence, it is likely that
The function of device will be allowed to be affected, the data of output error.
At present, the trigger on aerospace equipment typically uses the trigger (Sense- based on sense amplifier
Amplifier-based Flip-Flop, SAFF), being somebody's turn to do the trigger based on sense amplifier includes latch-type sense amplifier
11 and RS latch 12 is formed, and latch-type sense amplifier 11 uses cross-couplings (interlocking) structure, latches the data after amplification,
The function of reset can also be realized by being pre-charged, its circuit structure referring to Fig. 1, wherein, switching tube M4 and M8 are input pipe, are opened
It is switching clock signal pipe to close pipe M9, and switching tube M1 and M6 are preliminary filling fulgurite, and the core of the circuit is switching tube M2 and M3,
The phase inverter pair for a pair of cross coupling (interlocking) that switching tube M5 and M7 are formed, the input of latch-type sense amplifier 11 are generally
Differential Input, can be the differential signal that digital logic signal can also be the low amplitude of oscillation, when latch-type sense amplifier 11 passes through
The function of controlling to realize sampling and reset of clock signal, when input clock CLK is low level, export Q ends and Q_ ends all
High level is pulled to, realizes and resets operation, when input clock CLK signal is from low transition to high level, to input signal
Sampled, and amplified, finally latch two output numbers by cross-linked four switching tubes M2, M3, M5, M7
According to being then output to RS latch 12.RS latch 12 includes cross-linked two NAND gates, when clock signal clk is low
When, sense amplifier is pre-charge state, and output end (Q, Q_) is (1,1), then RS latch 12 is hold mode, and output is kept
It is constant, when clock signal clk from it is low become high hopping edge when, sense amplifier start sample input data D, work as input
When (S_, R_) is (0,1), because gate is NAND gate, therefore output end Q can export logic high, output end Q_ at once
Need just to export low level by a gate delay.
But due to switching tube M2, M3 and switching tube M5, the cross-couplings latch structure that M7 is formed is to belong to sensitive knot
Structure, in aerospace applications, because the SEU effects that single-particle impact is brought cause the point bit flipping of node, cause latch-type
, there is the upset of key node in the change of latch state in sense amplifier 11, so as to cause output error data, influences whole
Individual trigger normal function；And due to output signal trailing edge typically can a gate delay slower than rising edge, result in rising
Decline asymmetric problem, and this gate delay can also be influenceed by the load of the output end of RS latch 12, limit triggering
The operating rate of device.
The content of the invention
The purpose of the embodiment of the present invention is to provide a kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit, it is intended to solves traditional flip-flop
Applied in aerospace environment, limited performance and the problem of easily disturbed by single-particle inversion.
The embodiment of the present invention is achieved in that a kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit, and the triggers circuit includes：
The first sense amplifier and the second sense amplifier with double interlocking (DICE) structure, for passing through Bidirectional interlocking
Place the data in different nodes, two inputs of two inputs of first sense amplifier and second sense amplifier
The corresponding connection in end, the clock end of first sense amplifier are connected with the clock end of second sense amplifier, and described the
First positive output end of one sense amplifier is connected with the first positive output end of second sense amplifier, and described first
First inverse output terminal of sense amplifier is connected with the first inverse output terminal of second sense amplifier, first spirit
Second positive output end of quick amplifier is connected with the second positive output end of second sense amplifier, and described first is sensitive
Second inverse output terminal of amplifier is connected with the second inverse output terminal of second sense amplifier；
Logic gates, for the data of different nodes to be carried out with anti-single particle upset interference processing, generate preliminary filling telecommunications
Number, set signal or reset signal, the of the first input end of the logic gates and first, second sense amplifier
The first of two positive output end connections, the second input of the logic gates and first, second sense amplifier is just
Connected to output end, the 3rd input of the logic gates is reversely defeated with the first of first, second sense amplifier
Go out end connection, the 4th input of the logic gates and the second inverse output terminal of first, second sense amplifier
Connection；
RS latch with cross coupling structure, for when receiving precharging signal, phase inverter is formed to structure, with
Latch data, or, when receiving set signal or reset signal, realize that output is no-delay by symmetrical structure, the RS is latched
The S_ inputs of device are connected with the first output end of the logic gates, R_ inputs and the logic of the RS latch
The second output end connection of gate circuit, two output ends of the RS latch are the output end of the triggers circuit；
The double interlocking structure forms two phase inverters to forming by least eight switching tube coupling interactions.
The another object of the embodiment of the present invention is, there is provided a kind of space flight using above-mentioned Flouride-resistani acid phesphatase ultrahigh speed triggers circuit
Ultrahigh speed trigger.
The embodiment of the present invention is being realized using prime of first, second sense amplifier of DICE structures as trigger
It can also effectively prevent the problem of single-particle inversion is brought while the amplification of latch-type sense amplifier in itself and reset function,
And further by the output of two sense amplifiers by exporting the RS latch to rear stage, RS locks after logical gate operations
Storage exports branch road by the first, second of full symmetric structure, solves the problems, such as output signal rise and fall edge, and
And transmission delay can be reduced by reasonably adjusting the size of crucial metal-oxide-semiconductor, the output for strengthening whole high speed flip flop is driven
Kinetic force.And the trigger has the characteristics of speed is fast, and performance is good, single-particle inversion can be effectively prevented, especially meets boat
For the characteristics of demand of ultrahigh speed trigger in empty space technology field.
Brief description of the drawings
Fig. 1 is the circuit diagram of the existing trigger based on sense amplifier；
Fig. 2 is the structure chart of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention；
Fig. 3 is the sense amplifier that DICE structures are used in Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention
Exemplary circuit figure；
Fig. 4 is the exemplary circuit figure of logic gates in Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention；
Fig. 5 is the exemplary circuit figure of RS latch in Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Conflict can is not formed each other to be mutually combined.
The embodiment of the present invention places the data in different nodes by Bidirectional interlocking, and anti-list is carried out to the data of different nodes
Particle upset interference processing, generation precharging signal, set signal or reset signal, then logic is passed through to the data of different nodes
Computing carries out anti-single particle upset interference processing, and is realized by the RS latch with cross coupling structure no-delay defeated
Go out.
It is described in detail below in conjunction with realization of the specific embodiment to the present invention：
Fig. 2 shows the structure of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention, for convenience of description, only
Show part related to the present invention.
As one embodiment of the invention, the Flouride-resistani acid phesphatase ultrahigh speed triggers circuit can apply to any space flight ultrahigh speed triggering
In device, a kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit includes：
The first sense amplifier 21A and the second sense amplifier 21B with double interlocking structure, for passing through Bidirectional interlocking
Place the data in two inputs of different nodes, the first sense amplifier 21A two inputs and the second sense amplifier 21B
Corresponding connection, the first sense amplifier 21A clock end are connected with the second sense amplifier 21B clock end, and first sensitive puts
Big device 21A the first positive output end is connected with the second sense amplifier 21B the first positive output end, the first sense amplifier
21A the first inverse output terminal is connected with the second sense amplifier 21B the first inverse output terminal, the first sense amplifier 21A
The second positive output end be connected with the second sense amplifier 21B the second positive output end, the of the first sense amplifier 21A
Two inverse output terminals are connected with the second sense amplifier 21B the second inverse output terminal；
In embodiments of the present invention, the double interlocking structure that the first sense amplifier 21A and the second sense amplifier 21B is formed
As DICE structures, different nodes are placed the data in by dual symmetrical structure.
Logic gates 22, for the data of different nodes to be carried out with anti-single particle upset interference processing, generation precharge
The of signal, set signal or reset signal, the first input end of logic gates 22 and first, second sense amplifier 21B
Two positive output end connections, the first forward direction of the second input of logic gates 22 and first, second sense amplifier 21B are defeated
Go out end connection, the 3rd input of logic gates 22 and first, second sense amplifier 21B the first inverse output terminal connect
Connect, the 4th input of logic gates 22 is connected with first, second sense amplifier 21B the second inverse output terminal；
RS latch 23 with cross coupling structure, for when receiving precharging signal, phase inverter is formed to structure,
With latch data, or, when receiving set signal or reset signal, realized by symmetrical structure and export no-delay, RS latch
23 S_ inputs are connected with the first output end of logic gates 22, R_ inputs and the logic gates 22 of RS latch 23
The connection of the second output end, two output ends of RS latch 23 are the output end of triggers circuit；
Double interlocking structure forms two phase inverters to forming by least eight switching tube coupling interactions.
The embodiment of the present invention is being realized using prime of first, second sense amplifier of DICE structures as trigger
It can also effectively prevent the problem of single-particle inversion is brought while the amplification of latch-type sense amplifier in itself and reset function,
And further by the output of two sense amplifiers by exporting the RS latch to rear stage, RS locks after logical gate operations
Storage exports branch road by the first, second of full symmetric structure, solves the problems, such as output signal rise and fall edge, can
To realize that ultrahigh speed triggers, and transmission delay can be reduced by reasonably adjusting the size of crucial metal-oxide-semiconductor, enhancing is entirely
The output driving ability of high speed flip flop.
Triggers circuit provided in an embodiment of the present invention and trigger have the characteristics of speed is fast, and performance is good, can be effective
Single-particle inversion is prevented, is especially met in field of aerospace technology for the characteristics of demand of ultrahigh speed trigger.
Fig. 3 is shown in Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention and put using the sensitive of DICE structures
The exemplary circuit of big device, for convenience of description, illustrate only part related to the present invention.
As one embodiment of the invention, the first sense amplifier 21A includes：
Switching tube M1 to switching tube M14；
Switching tube M1 control terminal is the first sense amplifier 21A clock end, and switching tube M1 input connects power supply
Voltage, switching tube M1 output end are the first sense amplifier 21A the first positive output end, and switching tube M6 input connects
Supply voltage, switching tube M6 control terminal are the first sense amplifier 21A the first inverse output terminal, switching tube M6 output end
It is connected with switching tube M8 input, switching tube M8 control terminal is first the second inverse output terminals of sense amplifier 21A, switch
Pipe M8 output end is connected with switching tube M1 output end and switching tube M10 input simultaneously, and switching tube M10 control terminal is
First sense amplifier 21A the first inverse output terminal, switching tube M10 output end are connected with switching tube M12 input, opened
The control terminal for closing pipe M12 is the first sense amplifier 21A the second inverse output terminal, and switching tube M12 output end is simultaneously with opening
The input for closing pipe M4 connect with switching tube M14 input, switching tube M4 control terminal be the first sense amplifier 21A just
To input, switching tube M4 output end is connected with switching tube M5 input, and switching tube M5 control terminal sensitive is put for first
Big device 21A clock end, switching tube M5 output head grounding, the output end of switching tube M5 input also with switching tube M3 connect
Connect, switching tube M3 control terminal is the first sense amplifier 21A reverse input end, switching tube M3 input simultaneously with switch
Pipe M14 output end connects with switching tube M13 output end, switching tube M14 control terminal connection supply voltage, switching tube M13
Control terminal be the first sense amplifier 21A the second positive output end, switching tube M13 input is defeated with switching tube M11's
Go out end connection, switching tube M11 control terminal is the first sense amplifier 21A the first positive output end, switching tube M11 input
End is connected with switching tube M9 output end and switching tube M2 output end simultaneously, and switching tube M9 control terminal is the first sensitive amplification
Device 21A the second positive output end, switching tube M9 input are connected with switching tube M7 output end, switching tube M7 control terminal
For the first sense amplifier 21A the first positive output end, switching tube M7 input and switching tube M2 input connect simultaneously
Supply voltage is connect, switching tube M2 control terminal is the first sense amplifier 21A clock end, and switching tube M2 output end is first
Sense amplifier 21A the first inverse output terminal.
As a preferred embodiment of the present invention, switching tube M1, switching tube M2, switching tube M6 to switching tube M9 be p-type MOS
Pipe, the source electrode of p-type metal-oxide-semiconductor are the input of switching tube, and p-type metal-oxide-semiconductor drains as the output end of switching tube, the grid of p-type metal-oxide-semiconductor
The extremely control terminal of switching tube；
Switching tube M3, switching tube M4, switching tube M5, switching tube M10 to switching tube M14 are N-type metal-oxide-semiconductor, N-type metal-oxide-semiconductor
It is the output end of switching tube to drain as the input of switching tube, the source electrode of N-type metal-oxide-semiconductor, and the grid of N-type metal-oxide-semiconductor is switching tube
Control terminal.
Second sense amplifier 22B includes：
Switching tube m1 to switching tube m14；
Switching tube m1 control terminal is the second sense amplifier 21B clock end, and switching tube m1 input connects power supply
Voltage, switching tube m1 output end are the second sense amplifier 21B the second positive output end, and switching tube m6 input connects
Supply voltage, switching tube m6 control terminal are the second sense amplifier 21B the second inverse output terminal, switching tube m6 output end
It is connected with switching tube m8 input, switching tube m8 control terminal is second the first inverse output terminals of sense amplifier 21B, switch
Pipe m8 output end is connected with switching tube m1 output end and switching tube m10 input simultaneously, and switching tube m10 control terminal is
Second sense amplifier 21B the second inverse output terminal, switching tube m10 output end are connected with switching tube m12 input, opened
The control terminal for closing pipe m12 is the second sense amplifier 21B the first inverse output terminal, and switching tube m12 output end is simultaneously with opening
The input for closing pipe m4 connect with switching tube m14 input, switching tube m4 control terminal be the second sense amplifier 21B just
To input, switching tube m4 output end is connected with switching tube m5 input, and switching tube m5 control terminal sensitive is put for first
Big device 21A clock end, switching tube m5 output head grounding, the output end of switching tube m5 input also with switching tube m3 connect
Connect, switching tube m3 control terminal is the second sense amplifier 21B reverse input end, switching tube m3 input simultaneously with switch
Pipe m14 output end connects with switching tube m13 output end, switching tube m14 control terminal connection supply voltage, switching tube m13
Control terminal be the second sense amplifier 21B the first positive output end, switching tube m13 input is defeated with switching tube m11's
Go out end connection, switching tube m11 control terminal is the second sense amplifier 21B the second positive output end, switching tube m11 input
End is connected with switching tube m9 output end and switching tube m2 output end simultaneously, and switching tube m9 control terminal is the first sensitive amplification
Device 21A the first positive output end, switching tube m9 input are connected with switching tube m7 output end, switching tube m7 control terminal
For the second sense amplifier 21B the second positive output end, switching tube m7 input and switching tube m2 input connect simultaneously
Supply voltage is connect, switching tube m2 control terminal is the second sense amplifier 21B clock end, and switching tube m2 output end is second
Sense amplifier 21B the first inverse output terminal.
As a preferred embodiment of the present invention, switching tube m1, switching tube m2, switching tube m6 to switching tube m9 be p-type MOS
Pipe, the source electrode of p-type metal-oxide-semiconductor are the input of switching tube, and p-type metal-oxide-semiconductor drains as the output end of switching tube, the grid of p-type metal-oxide-semiconductor
The extremely control terminal of switching tube；
Switching tube m3, switching tube m4, switching tube m5, switching tube m10 to switching tube m14 are N-type metal-oxide-semiconductor, N-type metal-oxide-semiconductor
It is the output end of switching tube to drain as the input of switching tube, the source electrode of N-type metal-oxide-semiconductor, and the grid of N-type metal-oxide-semiconductor is switching tube
Control terminal.
In embodiments of the present invention, sense amplifier 21A, 21B of two double interlocking structures, the two sense amplifiers
Input identical, be all input data D and D_ and clock signal clk, it is positive that the first sense amplifier 21A data pass through first
The inverse output terminal B1 of output terminals A 1 and first is exported, and the second sense amplifier 21B data pass through the second positive He of output terminals A 2
Second inverse output terminal B2 is exported, and the two sense amplifiers pass through M6~M13 and m6~m13 each eight metal-oxide-semiconductors respectively
Metal-oxide-semiconductor as cross coupling structure.
For the two sense amplifiers, compared with traditional sense amplifier, using two structures and size identical
Switching tube (switching tube M6 and switching tube M8, switching tube M7 and switching tube M9, switching tube M10 and switching tube M12, switching tube M11 and
Switching tube M13, and switching tube m6 and switching tube m8, switching tube m7 and switching tube m9, switching tube m10 and switching tube m12, switch
Pipe m11 and switching tube m13) switching tube of the prior art is replaced, while connect grid on A, B (a, b) node and connect power supply
Voltage VDD NMOS tube M14, to realize the Design of Reinforcement of anti-single particle, the specific embodiment with reference to logic gates carries out detailed
Describe in detail bright.
Fig. 4 shows the example electricity of logic gates in Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention
Road, for convenience of description, it illustrate only part related to the present invention.
As one embodiment of the invention, logic gates 22 includes：
First OR gate, two inputs of the first OR gate are respectively first, second input of logic gates 22, first or
The output end of door is the first output end of logic gates 22；
Second OR gate, two inputs of the second OR gate are respectively the three, the 4th inputs of logic gates 22, second or
The output end of door is the second output end of logic gates 22.
In embodiments of the present invention, the output of two sense amplifiers is respectively A1, B1 and A2, B2, wherein output terminals A 1
Exported with A2 by being exported after an OR gate for the S_ ends of rear class RS latch, output end B1 and B2 passes through defeated after an OR gate
Go out the R_ ends output for rear class RS latch.
Output terminals A 1, A2 signal are identicals under normal circumstances, and the signal of output end B1, B2 is identical, S_=A1+
A2, R_=B1+B2, it is at this time normally to export；
If single-particle impact is occurred in pre-charging stage, clock signal clk is low, to the first sense amplifier 21A
In one or two current potential of A1, B1 node cause upset so that current potential 0, at this moment, due to the second sensitive amplification
Export in device 21B and do not change, then S_=A1+A2=1, R_=B1+B2=1, and without change, until preliminary filling fulgurite M1
The first sense amplifier 21A two current potentials are drawn high circuit with M2 and recover normal, such trigger volume output be not by
Interference, kindred circumstances the second sense amplifier 21B is identical by impact condition；
If single-particle impact occur clock signal for it is high when, it is assumed that the signal (A, B) of normal output latch for (1,
0), if sense amplifier is because single-particle inversion B1 output switching activities are high potential, because S_=A1+A2, R_=B1+B2,
(S_, R_) can then become (1,1), at this moment be the instruction of " holding " for the RS latch of rear class, so output is
Impregnable, because now switching tube M11 and switching tube M13 pipes are to open, the current potentials of elevated B1 points can be with
M11, M13, M14, M4 or M11, M13, M3 this two branch roads electric discharge return to low potential, because M3 pipes always have one with M4 pipes
Individual is to open, and M14 pipes are normally opened.When A1 becomes 0 from 1, when, because output S_=A1+A2, R_=B1+B2, (S_,
R_) still (1,0), the output of trigger is unaffected, and because M6 and M8 opening, A1 current potential can gradually be retracted for
It is high.
Therefore the wrong data for the output that single-particle inversion is brought can effectively be prevented.
The embodiment of the present invention is being realized using prime of first, second sense amplifier of DICE structures as trigger
It can also effectively prevent the problem of single-particle inversion is brought while the amplification of latch-type sense amplifier in itself and reset function,
And further by the output of two sense amplifiers by exporting the RS latch to rear stage, Ke Yishi after logical gate operations
Existing ultrahigh speed triggering, the Flouride-resistani acid phesphatase ultrahigh speed triggers circuit speed is fast, and performance is good, can effectively prevent single-particle inversion, especially
Meet in field of aerospace technology for the characteristics of demand of ultrahigh speed trigger.
Fig. 5 shows the exemplary circuit of RS latch in Flouride-resistani acid phesphatase ultrahigh speed triggers circuit provided in an embodiment of the present invention,
For convenience of description, it illustrate only part related to the present invention.
As one embodiment of the invention, RS latch 23 includes：
First output branch road 23A of symmetrical structure and the second output branch road 23B；
First output branch road 23A first input end is connected with the second output branch road 23B output end, the first output branch road
23A the second output end is the S_ inputs of RS latch 23, and the first output branch road 23A output end is the anti-of RS latch 23
To output end；
Second output branch road 23B first input end is connected with the first output branch road 23A output end, the second output branch road
23B the second output end and the R_ inputs for RS latch 23, the second output branch road 23B output end is RS latch 23
Positive output end.
As a preferred embodiment of the present invention, the first output branch road 23A includes：
Switching tube M21 to switching tube M26, and the first phase inverter I1；
Switching tube M21 input connection supply voltage, switching tube M21 control terminal are the of the first output branch road 23A
Two inputs, switching tube M21 output end connect for the control terminal of the first output branch road 23A first input end and switching tube M22
Connect, switching tube M22 input connection supply voltage, switching tube M22 output end is connected with switching tube M24 input, opened
The control terminal for closing pipe M24 is connected with the output end of the first phase inverter and switching tube M26 control terminal simultaneously, and switching tube M24's is defeated
The output end for going out end for the first output branch road 23A is connected with switching tube M26 input, switching tube M26 output head grounding, the
One phase inverter I1 input is connected with switching tube M21 control terminal, and switching tube M21 output end is also defeated with switching tube M23
Enter end connection, switching tube M23 control terminal is connected with switching tube M24 output end, switching tube M23 output end and switching tube
M25 input connection, switching tube M25 control terminal are connected with switching tube M21 control terminal, switching tube M25 output termination
Ground；
Second output branch road 23B includes：
Switching tube M27 to switching tube M32, and the second phase inverter I2；
Switching tube M27 input connection supply voltage, switching tube M27 control terminal are the of the second output branch road 23B
Two inputs, switching tube M27 output end connect for the control terminal of the second output branch road 23B first input end and switching tube M28
Connect, switching tube M28 input connection supply voltage, switching tube M28 output end is connected with switching tube M30 input, opened
The control terminal for closing pipe M30 is connected with the second phase inverter I2 output end and switching tube M32 control terminal simultaneously, switching tube M30's
Output end is that the second output branch road 23B output end is connected with switching tube M32 input, switching tube M32 output head grounding,
Second phase inverter I2 input is connected with switching tube M27 control terminal, and switching tube M29 input is defeated with switching tube M27's
Go out end connection, switching tube M29 control terminal is connected with switching tube M30 output end, switching tube M29 output end and switching tube
M31 input connection, switching tube M31 control terminal are connected with switching tube M27 control terminal, switching tube M31 output termination
Ground.
As a preferred embodiment of the present invention, switching tube M21, switching tube M22, switching tube M24, switching tube M27, switching tube
M28, switching tube M30 are p-type metal-oxide-semiconductor, and the source electrode of p-type metal-oxide-semiconductor is the input of switching tube, and the drain electrode of p-type metal-oxide-semiconductor is switching tube
Output end, the grid of p-type metal-oxide-semiconductor is the control terminal of switching tube；
Switching tube M23, switching tube M25, switching tube M26, switching tube M29, switching tube M31, switching tube M32 are N-type MOS
Pipe, the drain electrode of N-type metal-oxide-semiconductor are the input of switching tube, and the source electrode of N-type metal-oxide-semiconductor is the output end of switching tube, the grid of N-type metal-oxide-semiconductor
The extremely control terminal of switching tube.
In embodiments of the present invention, the input of RS latch 23 is S_, R_, wherein, the structure of first, second output branch road
It is full symmetric, the output of one of them is again as another input, i.e. cross coupling structure.Switching tube M2, switching tube
M3, and switching tube M8, latch pipes of the switching tube M9 as data, switching tube M1, switching tube M6 and switching tube M7, switching tube
M12 is output driving pipe, controls output driving current.
Its function implementation process is described below：Because the output of pre-amplifier is both of which, one kind output precharge
Signal enters precharge mode, and either reset signal enters set or reset mode for another kind output set.
When pre-amplifier is in precharge mode, the input S_, R_ of RS latch 23 are high level, are now opened
Pipe M1, switching tube M5, switching tube M7 are closed, switching tube M12 is closed, switching tube M4, switching tube M5, switching tube M10, switching tube M11
Pipe is opened, and equivalent to switching tube M2 and switching tube M3, switching tube M9 and switching tube M8 constitute two pairs of cross-linked phase inverters
It is right, as the effect of latch data, do not influence the working condition of latch below in pre-charging stage, the input of data.
When pre-amplifier is in mode of operation, if the input S_, R_ of RS latch 23 are respectively low and high level
When, now switching tube M1 is opened and Q nodes is charged, and switching tube M5 is opened, and Q_ nodes is discharged, in this process
Switching tube M8 is slowly opened until Q_ drops to low level, Q because switching tube M10, switching tube M8 are turned on and are stabilized to high level,
For this process because two output branch roads are full symmetric structures, it is consistent to export rising edge and the time of trailing edge
, so there will be no the asymmetric problem of output delay.
Further, because in state change, switching tube M1, switching tube M6 and switching tube M7, switching tube M12 only divide
Dao Tong not be one, if cross-linked switching tube M2 and switching tube M3, switching tube M9 and switching tube M8 size can be done
Suitable dot, just the speed of conversion can significantly be lifted, then the speed of trigger is greatly enhanced,
And the size for suitably adjusting driving tube can also further improve the driving force of output.
The another object of the embodiment of the present invention is, there is provided a kind of space flight using above-mentioned Flouride-resistani acid phesphatase ultrahigh speed triggers circuit
Ultrahigh speed trigger.
The embodiment of the present invention is being realized using prime of first, second sense amplifier of DICE structures as trigger
It can also effectively prevent the problem of single-particle inversion is brought while the amplification of latch-type sense amplifier in itself and reset function,
And further by the output of two sense amplifiers by exporting the RS latch to rear stage, RS locks after logical gate operations
Storage exports branch road by the first, second of full symmetric structure, solves the problems, such as output signal rise and fall edge, can
To realize that ultrahigh speed triggers, and transmission delay can be reduced by reasonably adjusting the size of crucial metal-oxide-semiconductor, enhancing is entirely
The output driving ability of high speed flip flop.
Triggers circuit provided in an embodiment of the present invention and trigger have the characteristics of speed is fast, and performance is good, can be effective
Single-particle inversion is prevented, is especially met in field of aerospace technology for the characteristics of demand of ultrahigh speed trigger.
These are only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
All any modification, equivalent and improvement made within principle etc., should be included in the scope of the protection.
Claims (9)
1. a kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit, it is characterised in that the triggers circuit includes：
The first sense amplifier and the second sense amplifier with double interlocking structure, for being deposited data by Bidirectional interlocking
In different nodes, two inputs of first sense amplifier are corresponding with two inputs of second sense amplifier to be connected
Connect, the clock end of first sense amplifier is connected with the clock end of second sense amplifier, and described first sensitive puts
Big first positive output end of device is connected with the first positive output end of second sense amplifier, the first sensitive amplification
First inverse output terminal of device is connected with the first inverse output terminal of second sense amplifier, first sense amplifier
The second positive output end be connected with the second positive output end of second sense amplifier, first sense amplifier
Second inverse output terminal is connected with the second inverse output terminal of second sense amplifier；
Logic gates, for the data of different nodes to be carried out with anti-single particle upset interference processing, generation precharging signal, put
The second of position signal or reset signal, the first input end of the logic gates and first, second sense amplifier is just
Connected to output end, the first forward direction of the second input of the logic gates and first, second sense amplifier is defeated
Go out end connection, the 3rd input of the logic gates and the first inverse output terminal of first, second sense amplifier
Connection, the 4th input of the logic gates are connected with the second inverse output terminal of first, second sense amplifier；
RS latch with cross coupling structure, for when receiving precharging signal, forming phase inverter to structure, to latch
Data, or, when receiving set signal or reset signal, realize that output is no-delay by symmetrical structure, the RS latch
S_ inputs are connected with the first output end of the logic gates, R_ inputs and the gate electricity of the RS latch
The second output end connection on road, two output ends of the RS latch are the output end of the triggers circuit；
The double interlocking structure forms two phase inverters to forming by least eight switching tube coupling interactions；
The RS latch includes：
First output branch road of symmetrical structure and the second output branch road；
The first input end of the first output branch road is connected with the output end of the described second output branch road, the first output branch
Second output end on road is the S_ inputs of the RS latch, and the output end of the first output branch road is the RS latch
Inverse output terminal；
The first input end of the second output branch road is connected with the output end of the described first output branch road, the second output branch
Second output end on road and the R_ inputs for the RS latch, the output end of the second output branch road latch for the RS
The positive output end of device.
2. triggers circuit as claimed in claim 1, it is characterised in that first sense amplifier includes：
Switching tube M1 to switching tube M14；
The control terminal of the switching tube M1 is the clock end of first sense amplifier, and the input of the switching tube M1 connects
Supply voltage, the output end of the switching tube M1 are the first positive output end of first sense amplifier, the switching tube
M6 input connection supply voltage, the control terminal of the switching tube M6 reversely export for the first of first sense amplifier
End, the output end of the switching tube M6 are connected with the input of the switching tube M8, and the control terminal of the switching tube M8 is described
First the second inverse output terminal of sense amplifier, the output end of the switching tube M8 simultaneously with the output end of the switching tube M1 and
The input connection of the switching tube M10, the control terminal of the switching tube M10 are first reverse for first sense amplifier
Output end, the output end of the switching tube M10 are connected with the input of the switching tube M12, the control terminal of the switching tube M12
For the second inverse output terminal of first sense amplifier, the output end of the switching tube M12 simultaneously with the switching tube M4
Input connected with the input of the switching tube M14, the control terminal of the switching tube M4 is first sense amplifier
Positive input, the output end of the switching tube M4 is connected with the input of the switching tube M5, the control of the switching tube M5
End processed be first sense amplifier clock end, the output head grounding of the switching tube M5, the input of the switching tube M5
The output end also with the switching tube M3 is held to be connected, the control terminal of the switching tube M3 is the reverse of first sense amplifier
Input, the input of the switching tube M3 simultaneously with the output end of the switching tube M14 and the output end of the switching tube M13
Connection, the control terminal connection supply voltage of the switching tube M14, the control terminal of the switching tube M13 sensitive are put for described first
Second positive output end of big device, the input of the switching tube M13 is connected with the output end of the switching tube M11, described to open
The control terminal for closing pipe M11 is the first positive output end of first sense amplifier, and the input of the switching tube M11 is simultaneously
It is connected with the output end of the switching tube M9 and the output end of the switching tube M2, the control terminal of the switching tube M9 is described the
Second positive output end of one sense amplifier, the input of the switching tube M9 are connected with the output end of the switching tube M7,
The control terminal of the switching tube M7 be first sense amplifier the first positive output end, the input of the switching tube M7
Supply voltage is connected simultaneously with the input of the switching tube M2, the control terminal of the switching tube M2 is the described first sensitive amplification
The clock end of device, the output end of the switching tube M2 are the first inverse output terminal of first sense amplifier.
3. triggers circuit as claimed in claim 2, it is characterised in that the switching tube M1, the switching tube M2, the switch
Pipe M6 to the switching tube M9 is p-type metal-oxide-semiconductor, and the source electrode of the p-type metal-oxide-semiconductor is the input of the switching tube, the p-type
The drain electrode of metal-oxide-semiconductor is the output end of the switching tube, and the grid of the p-type metal-oxide-semiconductor is the control terminal of the switching tube；
The switching tube M3, the switching tube M4, the switching tube M5, the switching tube M10 to the switching tube M14 are N-type
Metal-oxide-semiconductor, the drain electrode of the N-type metal-oxide-semiconductor is the input of the switching tube, and the source electrode of the N-type metal-oxide-semiconductor is the switching tube
Output end, the grid of the N-type metal-oxide-semiconductor are the control terminal of the switching tube.
4. triggers circuit as claimed in claim 1, it is characterised in that second sense amplifier includes：
Switching tube m1 to switching tube m14；
The control terminal of the switching tube m1 is the clock end of second sense amplifier, and the input of the switching tube m1 connects
Supply voltage, the output end of the switching tube m1 are the second positive output end of second sense amplifier, the switching tube
M6 input connection supply voltage, the control terminal of the switching tube m6 reversely export for the second of second sense amplifier
End, the output end of the switching tube m6 are connected with the input of the switching tube m8, and the control terminal of the switching tube m8 is described
Second the first inverse output terminal of sense amplifier, the output end of the switching tube m8 simultaneously with the output end of the switching tube m1 and
The input connection of the switching tube m10, the control terminal of the switching tube m10 are second reverse for second sense amplifier
Output end, the output end of the switching tube m10 are connected with the input of the switching tube m12, the control terminal of the switching tube m12
For the first inverse output terminal of second sense amplifier, the output end of the switching tube m12 simultaneously with the switching tube m4
Input connected with the input of the switching tube m14, the control terminal of the switching tube m4 is second sense amplifier
Positive input, the output end of the switching tube m4 is connected with the input of the switching tube m5, the control of the switching tube m5
End processed be first sense amplifier clock end, the output head grounding of the switching tube m5, the input of the switching tube m5
The output end also with the switching tube m3 is held to be connected, the control terminal of the switching tube m3 is the reverse of second sense amplifier
Input, the input of the switching tube m3 simultaneously with the output end of the switching tube m14 and the output end of the switching tube m13
Connection, the control terminal connection supply voltage of the switching tube m14, the control terminal of the switching tube m13 sensitive are put for described second
First positive output end of big device, the input of the switching tube m13 is connected with the output end of the switching tube m11, described to open
The control terminal for closing pipe m11 is the second positive output end of second sense amplifier, and the input of the switching tube m11 is simultaneously
It is connected with the output end of the switching tube m9 and the output end of the switching tube m2, the control terminal of the switching tube m9 is described the
First positive output end of one sense amplifier, the input of the switching tube m9 are connected with the output end of the switching tube m7,
The control terminal of the switching tube m7 be second sense amplifier the second positive output end, the input of the switching tube m7
Supply voltage is connected simultaneously with the input of the switching tube m2, the control terminal of the switching tube m2 is the described second sensitive amplification
The clock end of device, the output end of the switching tube m2 are the first inverse output terminal of second sense amplifier.
5. triggers circuit as claimed in claim 4, it is characterised in that the switching tube m1, the switching tube m2, the switch
Pipe m6 to the switching tube m9 is p-type metal-oxide-semiconductor, and the source electrode of the p-type metal-oxide-semiconductor is the input of the switching tube, the p-type
The drain electrode of metal-oxide-semiconductor is the output end of the switching tube, and the grid of the p-type metal-oxide-semiconductor is the control terminal of the switching tube；
The switching tube m3, the switching tube m4, the switching tube m5, the switching tube m10 to the switching tube m14 are N-type
Metal-oxide-semiconductor, the drain electrode of the N-type metal-oxide-semiconductor is the input of the switching tube, and the source electrode of the N-type metal-oxide-semiconductor is the switching tube
Output end, the grid of the N-type metal-oxide-semiconductor are the control terminal of the switching tube.
6. triggers circuit as claimed in claim 1, it is characterised in that the logic gates includes：
First OR gate, two inputs of first OR gate are respectively first, second input of the logic gates, described
The output end of first OR gate is the first output end of the logic gates；
Second OR gate, two inputs of second OR gate are respectively the three, the 4th inputs of the logic gates, described
The output end of second OR gate is the second output end of the logic gates.
7. triggers circuit as claimed in claim 1, it is characterised in that the first output branch road includes：
Switching tube M21 to switching tube M26, and the first phase inverter；
The input connection supply voltage of the switching tube M21, the control terminal of the switching tube M21 is the described first output branch road
The second input, the first input end and the switching tube of the output end of the switching tube M21 for the described first output branch road
M22 control terminal connection, the switching tube M22 input connection supply voltage, the output end of the switching tube M22 with it is described
Switching tube M24 input connection, the control terminal of the switching tube M24 simultaneously with the output end of first phase inverter and described
Switching tube M26 control terminal connection, the output end of the switching tube M24 are opened for the output end of the described first output branch road with described
Pipe M26 input connection is closed, the output head grounding of the switching tube M26, the input of first phase inverter is opened with described
Close pipe M21 control terminal connection, the input of the output end of the switching tube M21 also with the switching tube M23 is connected, described to open
The control terminal for closing pipe M23 is connected with the output end of the switching tube M24, output end and the switching tube of the switching tube M23
M25 input connection, the control terminal of the switching tube M25 are connected with the control terminal of the switching tube M21, the switching tube
M25 output head grounding；
The second output branch road includes：
Switching tube M27 to switching tube M32, and the second phase inverter；
The input connection supply voltage of the switching tube M27, the control terminal of the switching tube M27 is the described second output branch road
The second input, the first input end and the switching tube of the output end of the switching tube M27 for the described second output branch road
M28 control terminal connection, the switching tube M28 input connection supply voltage, the output end of the switching tube M28 with it is described
Switching tube M30 input connection, the control terminal of the switching tube M30 simultaneously with the output end of second phase inverter and described
Switching tube M32 control terminal connection, the output end of the switching tube M30 are opened for the output end of the described second output branch road with described
Pipe M32 input connection is closed, the output head grounding of the switching tube M32, the input of second phase inverter is opened with described
Pipe M27 control terminal connection is closed, the input of the switching tube M29 is connected with the output end of the switching tube M27, the switch
Pipe M29 control terminal is connected with the output end of the switching tube M30, the output end of the switching tube M29 and the switching tube M31
Input connection, the control terminal of the switching tube M31 is connected with the control terminal of the switching tube M27, the switching tube M31's
Output head grounding.
8. triggers circuit as claimed in claim 1, it is characterised in that the switching tube M21, the switching tube M22, described open
It is p-type metal-oxide-semiconductor to close pipe M24, the switching tube M27, the switching tube M28, the switching tube M30, the source of the p-type metal-oxide-semiconductor
The input of extremely described switching tube, the drain electrode of the p-type metal-oxide-semiconductor are the output end of the switching tube, the p-type metal-oxide-semiconductor
Grid is the control terminal of the switching tube；
The switching tube M23, the switching tube M25, the switching tube M26, the switching tube M29, the switching tube M31, institute
It is N-type metal-oxide-semiconductor to state switching tube M32, and the N-type metal-oxide-semiconductor drains as the input of the switching tube, the source of the N-type metal-oxide-semiconductor
The output end of extremely described switching tube, the grid of the N-type metal-oxide-semiconductor are the control terminal of the switching tube.
9. a kind of space flight ultrahigh speed trigger, it is characterised in that the space flight ultrahigh speed trigger includes such as claim 1 to 8
Flouride-resistani acid phesphatase ultrahigh speed triggers circuit described in any one.
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| CN105915222A (en) * | 2015-12-11 | 2016-08-31 | 中国航空工业集团公司西安航空计算技术研究所 | High-sensitivity high-speed sampler circuit |
| CN105788624B (en) * | 2016-02-23 | 2019-01-04 | 北京大学（天津滨海）新一代信息技术研究院 | A kind of novel output is along symmetrical highly sensitive sense amplifier |
| KR102596875B1 (en) * | 2016-11-23 | 2023-11-01 | 삼성전자주식회사 | Flip flop |
| CN107425832B (en) * | 2017-09-15 | 2023-10-13 | 启攀微电子（上海）有限公司 | Load switch capable of conducting current limiting bidirectionally |
| CN111211771B (en) * | 2020-02-26 | 2023-10-24 | 中国科学院微电子研究所 | High-speed data buffer |
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| CN101138155A (en) * | 2005-01-10 | 2008-03-05 | 高通股份有限公司 | Multi-threshold mos circuits |
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| US7362154B2 (en) * | 2006-05-18 | 2008-04-22 | International Business Machines Corporation | Radiation hardened latch |
| JP2010056592A (en) * | 2008-08-26 | 2010-03-11 | Fujitsu Ltd | Flip-flop circuit |
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| CN101138155A (en) * | 2005-01-10 | 2008-03-05 | 高通股份有限公司 | Multi-threshold mos circuits |
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