CN105788624B - A kind of novel output is along symmetrical highly sensitive sense amplifier - Google Patents
A kind of novel output is along symmetrical highly sensitive sense amplifier Download PDFInfo
- Publication number
- CN105788624B CN105788624B CN201610102425.2A CN201610102425A CN105788624B CN 105788624 B CN105788624 B CN 105788624B CN 201610102425 A CN201610102425 A CN 201610102425A CN 105788624 B CN105788624 B CN 105788624B
- Authority
- CN
- China
- Prior art keywords
- transistor
- pmos transistor
- nmos transistor
- nmos
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
Abstract
The present invention relates to a kind of novel outputs along symmetrical highly sensitive sense amplifier.The first order pulse generator that the sense amplifier uses is identical as traditional structure, the structure of the S/R latch of the second level is made of two phase inverters and 6 PMOS (Mp1~Mp6) transistors and 6 NMOS (Mn1~Mn6) transistors, uses CLK and CLKB for the control of two-phase complementary clock.Novel sensitive amplifier structure of the invention has the advantages that structure after Nikolic improvement, exports rising edge and failing edge is very symmetrical；Since the second level introduces clock control, the load pipe of the first order is reduced, so that output data be made to reduce along delay, speed is become faster, and same power consumption decreases；And because the symmetry of decision instant first order differential load is greatly improved to which this structure has very high sensitivity.
Description
Technical field
The invention belongs to high-speed data communication technical field of integrated circuits, are a kind of sense amplifier knots of novel improvement
Sensitivity can be improved a magnitude in the case where power consumption, speed are not sacrificed, therefore can greatly improve many moulds by structure
The performance of block structure, than as can CDR (clock data recovery circuit) is allowed preferably to judge number according to the sampling situations of data edge
According to the corresponding relationship of clock.The structure can be widely suitable in various data communication transmitters or transceiver system.
Background technique
Fig. 1 is a kind of traditional sensitive amplifier structure, and the structure is mainly by the pulse generator of the first order and the second level
S/R latch constitute.In the pulse generator circuit of the first order, D and D ' indicate that differential input signal, S ' and R ' indicate SR lock
Two input nodes of storage, VDD indicate that power supply, GND indicate ground connection, and CLK indicates clock signal.The S/R latch electricity of the second level
Lu Zhong, Mp1~Mp4 are PMOS transistors, and Mn1~Mn4 is NMOS transistor, and Q and Q ' are differential output nodes.The first order when
Preliminary filling is carried out when clock low level, in clock high level according to D and D ' size carry out evaluation judgement, charging stage S ' and R ' quilt
High level is set, evaluation stage S ' and R ' can be set to respectively high level and low level according to the size of D and D '.Following second level SR
Latch is in S ' and R ' be all high level be in hold mode, in S ' and R ' is in set shape when being respectively low and high level
State.To which the structure converts the small signal of simulation in order to which the complete digital signal of the full amplitude of oscillation exports.
However since the output of the characteristic of the set-reset flip-floop traditional structure has asymmetric rising edge and failing edge, due to
Drop-down access need to wait the other end pull-up access complete pull-up after so that drive, if such as S ' pulls down to 0 after evaluation,
Mp1 opens then Q and is immediately essentially pulled up to 1, however after Q ' node then needs that Q is waited to become high level and then drives Mn4 could be by under
Draw to 0, so output failing edge always lags behind one gate delay of rising edge, in this way can serious restriction overall circuit performance,
Cause data " 0 " different with the duty ratio of data " 1 ", influences late-class circuit nargin, hinder further increasing for speed.
Fig. 2 is a kind of S/R latch classical architecture for symmetrical expression that Nikolic is proposed on JSSC, wherein Q, Q ' indicate poor
Point output node, the structure solve the problems, such as that output rising edge and failing edge are asymmetric, the more quickening for allowing failing edge to arrive from
And with rising edge synch (Nikolic, B., Oklobdzijia, V.G., et al. ' Improved sense-amplifier
based flip-flop:design and measurements’,IEEE J.Solid-State Circuits,2000,35,
(6),pp.876–883.”)。
However the S/R latch of the second level is in the evaluation stage to the first order pulse generator S ' and R ' in both the above structure
The load (since there is the load pipes of two entirely different working conditions) of two points is very asymmetric, thus serious system
The about raising of its sensitivity.In Fig. 1 structure, before evaluation in a flash, the gate voltage of Mn1 and Mn3 have been set to high level,
And Mn2 and Mn4 mono- open a closing, so that Mn1 and Mn3 have a job in the conductive state in triode region, one
In off state, so the C of Mn1 and Mn3 at this timeGSAnd CGDVery big difference (device principle is shown in Fig. 3) is had so as to cause total
Gate capacitance differ greatly.Therefore the difference of load has seriously affected the precision of evaluation, constrains the raising of sensitivity.Fig. 3's
In NMOS gate capacitance analysis chart, G indicates grid, and S and D indicate source and leakage, B are body, CGSFor gate-source capacitance, CGDFor gate leakage capacitance, iS、
iG、iDRespectively source electrode, grid and drain current, CJDFor drain terminal junction capacity, CJSFor source junction capacity, CGBFor grid body capacitance, CGSO
For grid source overlap capacitance, CGDOFor grid leak overlap capacitance,WithFor leakage current.
There is also similar situation equally in Fig. 2 structure of Nikolic (second level loads Mn3 and Mn5).
Summary of the invention
The present invention is directed to the defect of existing sense amplifier sensitivity, proposes the novel output of one kind along symmetrical Gao Ling
Sensitivity sense amplifier.
A kind of output of the invention is along symmetrical highly sensitive sense amplifier, pulse generator including the first order and the
The S/R latch of second level, the S/R latch include two phase inverters, six PMOS transistor Mp1~Mp6, six NMOS crystal
Pipe Mn1~Mn6 and two-phase complementary clock CLK, CLKB；The input node S ' and R ' of the S/R latch are separately connected MP1, MP2
Grid end, S ' and R ' be also respectively connected with two phase inverters, and the inversion signal of inverted device output is separately connected the grid of Mn2, Mn1
End；The source of Mp1, Mp2 connect power supply, the source ground connection of Mn1, Mn2；The drain terminal of Mp1, Mn1 are connected, the drain terminal phase of Mp2, Mn2
Even, respectively as output node Q and Q '；The source of Mp3, Mp5 connect power supply, and the drain terminal of Mp3, Mp5 are separately connected clock control
The grid end of the source of pipe Mp4, Mp6, Mp4, Mp6 is controlled by CLK；The source of Mn4, Mn6 are grounded, and the drain terminal of Mn4, Mn6 connect respectively
The source of clock control pipe Mn3, Mn5 is connect, the grid end of Mn3, Mn5 are controlled by CLK '；The grid end of Mp3, Mn4 connect Q ' node,
The grid end of Mp5, Mn6 connect Q node；The drain terminal of clock control pipe Mp4, Mn3 connect Q node, the leakage of clock control pipe Mp6, Mn5
End connection Q ' node.
Further, the course of work of above-mentioned sense amplifier is: when clock is low level, the pulse of the first order is generated
Device preliminary filling, S ' and R ' are placed in high level, and Mn1, Mn2, Mp1, Mp2 are closed, and Mn3, Mn4, Mp5, Mp6 are opened, the SR lock of the second level
Storage works in latch mode；When clock is high level, the pulse generator of the first order starts evaluation, by adjudicating S ' and R '
It is respectively placed in low and high level, Mn3, Mn4, Mp5, Mp6 are closed, and the S/R latch of the second level works in SM set mode.
Further, by Mp4, Mp6 and Mp3, Mp5 transposition, and Mp4, Mp6 are merged into a PMOS transistor,
Its source connects power supply；A NMOS transistor is merged by Mn3, Mn5 and Mn4, Mn6 transposition, and by Mn3, Mn5,
Source ground connection.
Compared with prior art, beneficial effects of the present invention are as follows:
It is defeated after novel sensitive amplifier structure of the invention has almost all of Nikolic to improve the advantages of structure
Rising edge and failing edge are very symmetrical out；Since the second level introduces clock control, the load pipe of the first order is reduced, to make to export
Data reduce speed along delay and become faster, and same power consumption decreases.Additionally, due to S ' and R ' load there was only two
A phase inverter and Mp1, Mp2 are adjudicated in a flash in evaluation, and Mp1, Mp2 is not turned on, and the load of S ' and R ' are almost the same, is made
Judgement almost depends only on Differential Input, to greatly improve sensitivity.
Detailed description of the invention
Fig. 1 is traditional sensitive amplifier structure figure.
Fig. 2 is the classical structure-improved figure that Nikolic is proposed.
Fig. 3 is NMOS gate capacitance analysis chart.
Fig. 4 is novel sense amplifier slave latch structure chart proposed by the present invention.
Fig. 5 is another slave latch structure chart that the present invention uses same principle.
Fig. 6 is three kinds of structure simulation comparison diagrams of the present invention with traditional sensitive amplifier structure, Nikolic structure.
Fig. 7 is the present invention and traditional structure Single-end output duty ratio comparison diagram.
Specific embodiment
Below by specific embodiments and the drawings, the present invention will be further described.
Sensitive amplifier structure of the invention is no longer limited to the logic of S/R latch, but according to the whole of sense amplifier
Body function introduces a kind of new slave latch by clock control, and the slave latch is to first order pulse generator circuit
There is more symmetrical load, structure is as shown in Figure 4.The first order pulse generator and conventional junction that the sense amplifier uses
Structure is identical.The structure of the S/R latch of the second level shown in Fig. 4 is: total is by two phase inverters and 6 PMOS (Mp1
~Mp6) transistor and 6 NMOS (Mn1~Mn6) transistors composition, pull-up access and drop-down access are very symmetrical, S ' and R '
For the input node of S/R latch, CLK and CLKB are two-phase complementary clock, and Q and Q ' are differential output nodes.
The specific connection relationship of each device is in Fig. 4: S ' and R ' is separately connected the grid end of MP1, MP2, inversion signal, that is, S
It is separately connected the grid end of Mn2, Mn1 with R, Mp1, Mp2 and Mn1, Mn2 source meet VDD and GND respectively, and Mn1, Mp1 and Mn2,
Mp2 drain terminal is respectively connected with (respectively output node Q and Q '), to constitute Q and Q ' four set accesses of node.Mp3,
The source of Mp5 and Mn4, Mn6 are separately connected VDD and GND, their drain terminal be separately connected clock control pipe Mp4, Mp6 (grid end by
CLK control) and Mn3, Mn5 (grid end is controlled by CLK ')；Mp3, Mn4 and Mp5, the grid end of Mn6 are separately connected Q ' and Q node, when
Clock tubulation Mp4, Mn3 and Mp6, Mn5 drain terminal are respectively connected in Q and Q ' access is deposited to constitute clock lockmaking at that time.
The course of work of above-mentioned sense amplifier is: when clock be low level when, first order pulse generator preliminary filling, S ' and
R ' is placed in high level, Mn1, Mn2, and Mp1, Mp2 are closed, and Mn3, Mn4, Mp5, Mp6 are opened, and rear class latch work at this time is being latched
State.When clock is high level, first order pulse generator starts evaluation, is respectively placed in height electricity by adjudicating S ' and R '
Flat, Mn3, Mn4, Mp5, Mp6 are closed, and rear class latch works in SM set mode.
In above-mentioned sensitive amplifier structure, if Mp4 and Mp6 moved on to above Mp3 and Mp5, connection VDD, Mp4 and Mp6 can
Merging into a pipe does not influence function, Mn3 and Mn5, so as to save two transistors, sees Fig. 5, but Q and Q ' in this way
Load can become larger to influence speed.
Emulation of three of the above structure under the conditions ofs same technological temperature etc. in the pipe parameter situation all the same of each congenerous
Comparison diagram as shown in fig. 6,1. be traditional structure (structure i.e. shown in FIG. 1), be 2. structure of the invention, be 3. the knot of Nikolic
Structure, curve 1 and curve 2 respectively indicate Q and Q in figure ' output, structure of the invention has most fast speed in contrast.
Fig. 7 is the present invention and traditional structure Single-end output duty ratio comparison diagram, and wherein curve 2 is the present invention, and curve 1 is to pass
System structure.From figure 7 it can be seen that compare with traditional structure, when structure Single-end output of the invention, data 0 and 1 have perfectly
Duty ratio, in this way as the nargin that late-class circuit is left in the raising of speed for can be with adding abundance.Detail parameters comparison is as shown in the table:
Each sense amplifier performance comparison of Table I
| The structure of Nikolic | Traditional structure | The present invention | |
| Technique | 65nm | 65nm | 65nm |
| Number of transistors | 25 | 17 | 25 |
| Rising edge delay C-Q* | 77ps | 75ps | 74ps |
| Failing edge delay C-Q* | 79ps | 98ps | 73ps |
| Power consumption * | 70uW | 61uW | 67uW |
| Sensitivity when 5GHz clock frequency | 5mV | 11mV | 0.3mV |
* condition: TT corner, 27 DEG C, Vdd=1.2V, 40mV input the amplitude of oscillation
Through simulation comparison, when clock frequency is 5GHz, when the Differential Input amplitude of oscillation is lower than 11mV, traditional structure no longer can
It works normally, the structure of Nikolic can be worked normally when differential swings are higher than 5mV, and structure proposed by the present invention is in difference
It still can work normally when the amplitude of oscillation is lower than 0.3mV.The sensitivity of structure of the invention is about promoted relative to the structure of Nikolic
It 20 times, has combined it and has exported rising edge and failing edge symmetrical excellent performance without sacrificing power consumption, speed and area,
Its excellent performance is shown.
The above embodiments are merely illustrative of the technical solutions of the present invention rather than is limited, the ordinary skill of this field
Personnel can be with modification or equivalent replacement of the technical solution of the present invention are made, without departing from the spirit and scope of the present invention, this
The protection scope of invention should be subject to described in claims.
Claims (3)
1. a kind of output is along symmetrical highly sensitive sense amplifier, the SR lock of pulse generator and the second level including the first order
Storage, which is characterized in that the S/R latch includes two phase inverters, six PMOS transistor Mp1~Mp6, six NMOS crystalline substances
Body pipe Mn1~Mn6 and two-phase complementary clock CLK, CLKB；The input node S ' and R ' of the S/R latch are separately connected PMOS crystalline substance
The gate terminal of body pipe Mp1, Mp2；Input node S ' and R ' are also respectively connected with two phase inverters, the inversion signal of inverted device output
It is separately connected the gate terminal of NMOS transistor Mn2, Mn1；The source terminal of PMOS transistor Mp1, Mp2 connects power supply, NMOS crystal
The source terminal of pipe Mn1, Mn2 are grounded；PMOS transistor Mp1, the drain electrode end of NMOS transistor Mn1 are connected, PMOS transistor Mp2,
The drain electrode end of NMOS transistor Mn2 is connected, respectively as output node Q and Q '；The source terminal of PMOS transistor Mp3, Mp5 connects
Power supply, the drain electrode end of PMOS transistor Mp3, Mp5 are separately connected the source electrode of PMOS transistor Mp4, Mp6 as clock control pipe
End, the gate terminal of PMOS transistor Mp4, Mp6 are controlled by CLK；The source terminal of NMOS transistor Mn4, Mn6 are grounded, NMOS crystal
The drain electrode end of pipe Mn4, Mn6 are separately connected the source terminal of NMOS transistor Mn3, Mn5 as clock control pipe, NMOS transistor
The gate terminal of Mn3, Mn5 are controlled by CLKB；The gate terminal connection Q ' node of PMOS transistor Mp3, NMOS transistor Mn4, PMOS
The gate terminal connection Q node of transistor Mp5, NMOS transistor Mn6；PMOS transistor Mp4, NMOS as clock control pipe is brilliant
The drain electrode end of body pipe Mn3 connects Q node, the drain electrode end as the PMOS transistor Mp6 of clock control pipe, NMOS transistor Mn5
Connect Q ' node.
2. high sensitivity sense amplifier as described in claim 1, it is characterised in that: be used for when in the two-phase complementary clock
When the clock of the pulse generator of the first order is low level, the pulse generator preliminary filling of the first order, S ' and R ' are placed in high level,
NMOS transistor Mn1, NMOS transistor Mn2, PMOS transistor Mp1, PMOS transistor Mp2 are closed, NMOS transistor Mn3,
NMOS transistor Mn4, PMOS transistor Mp5, PMOS transistor Mp6 are opened, and the S/R latch of the second level works in latch mode；
When being used for the clock of pulse generator of the first order in the two-phase complementary clock is high level, the pulse generator of the first order
Start evaluation, is respectively placed in low and high level, NMOS transistor Mn3, NMOS transistor Mn4, PMOS crystal by adjudicating S ' and R '
Pipe Mp5, PMOS transistor Mp6 are closed, and the S/R latch of the second level works in SM set mode.
3. high sensitivity sense amplifier as claimed in claim 1 or 2, it is characterised in that: by PMOS transistor Mp4, Mp6 with
PMOS transistor Mp3, Mp5 transposition, and PMOS transistor Mp4, Mp6 is merged into a PMOS transistor, source terminal
Connect power supply；By NMOS transistor Mn3, Mn5 and NMOS transistor Mn4, Mn6 transposition, and by NMOS transistor Mn3, Mn5
Merge into a NMOS transistor, source terminal ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610102425.2A CN105788624B (en) | 2016-02-23 | 2016-02-23 | A kind of novel output is along symmetrical highly sensitive sense amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610102425.2A CN105788624B (en) | 2016-02-23 | 2016-02-23 | A kind of novel output is along symmetrical highly sensitive sense amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105788624A CN105788624A (en) | 2016-07-20 |
| CN105788624B true CN105788624B (en) | 2019-01-04 |
Family
ID=56403601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610102425.2A Active CN105788624B (en) | 2016-02-23 | 2016-02-23 | A kind of novel output is along symmetrical highly sensitive sense amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105788624B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769807A (en) * | 2020-06-11 | 2020-10-13 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifying type D trigger |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6633188B1 (en) * | 1999-02-12 | 2003-10-14 | Texas Instruments Incorporated | Sense amplifier-based flip-flop with asynchronous set and reset |
| US8536919B1 (en) * | 2010-10-21 | 2013-09-17 | Altera Corporation | Integrated circuits with delay matching circuitry |
| CN104506168A (en) * | 2014-12-10 | 2015-04-08 | 深圳市国微电子有限公司 | Radiation-proof ultrahigh-speed triggering circuit and spaceflight ultrahigh-speed trigger |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100425474B1 (en) * | 2001-11-21 | 2004-03-30 | 삼성전자주식회사 | Data output method and data output circuit for applying reduced precharge level |
-
2016
- 2016-02-23 CN CN201610102425.2A patent/CN105788624B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6633188B1 (en) * | 1999-02-12 | 2003-10-14 | Texas Instruments Incorporated | Sense amplifier-based flip-flop with asynchronous set and reset |
| US8536919B1 (en) * | 2010-10-21 | 2013-09-17 | Altera Corporation | Integrated circuits with delay matching circuitry |
| CN104506168A (en) * | 2014-12-10 | 2015-04-08 | 深圳市国微电子有限公司 | Radiation-proof ultrahigh-speed triggering circuit and spaceflight ultrahigh-speed trigger |
Non-Patent Citations (1)
| Title |
|---|
| 一种高速片上互连接收电路设计;鲁晟,蒋剑飞,何卫锋,毛志刚;《微电子学与计算机》;20130228;103-107页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105788624A (en) | 2016-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10666243B2 (en) | High-speed low-power-consumption dynamic comparator | |
| CN104617925B (en) | Latch cicuit | |
| CN103856206A (en) | Low-to-high logic level conversion circuit | |
| US6922083B2 (en) | High speed sampling receiver with reduced output impedance | |
| CN106560999A (en) | Apparatus For Low-power And High-speed Integrated Clock Gating Cell | |
| CN105099159B (en) | A kind of fast start circuit for DC DC converters | |
| TW201505372A (en) | Low power master-slave flip-flop | |
| CN108494388A (en) | A kind of high-speed low-noise dynamic comparer | |
| CN104202032B (en) | Single-phase clock low-level asynchronous reset low-power consumption trigger and control method thereof | |
| CN108270420A (en) | A kind of comparator and successive approximation analog-digital converter | |
| Li et al. | An ultra-low voltage comparator with improved comparison time and reduced offset voltage | |
| US10447251B2 (en) | Power efficient high speed latch circuits and systems | |
| CN104506168B (en) | A kind of Flouride-resistani acid phesphatase ultrahigh speed triggers circuit and space flight ultrahigh speed trigger | |
| CN109639268A (en) | D type flip flop and phase frequency detector circuit | |
| CN105788624B (en) | A kind of novel output is along symmetrical highly sensitive sense amplifier | |
| CN109547191B (en) | Dual rail precharge logic device | |
| CN102339637B (en) | Condition-precharged sense-amplifier-based flip flop | |
| CN104205650B (en) | Squelch detector apparatus and method based on phase inverter and switched capacitor | |
| US9418713B2 (en) | Apparatus and method for sense amplifying | |
| TWI828629B (en) | Level shifter with bypass control | |
| CN102843130B (en) | Phase detector based on CML (Current Mode Logic) | |
| CN103326707B (en) | The input receiving circuit of the multiple DDR of a kind of compatibility | |
| CN1835402B (en) | Self bias high frequency logical gate and nor gate and NAND gate applied the same | |
| CN103856189A (en) | Pulse-based flip-flop | |
| CN104333366B (en) | A kind of Digital I/O Circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |