CN103326707B - The input receiving circuit of the multiple DDR of a kind of compatibility - Google Patents
The input receiving circuit of the multiple DDR of a kind of compatibility Download PDFInfo
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- CN103326707B CN103326707B CN201310192228.0A CN201310192228A CN103326707B CN 103326707 B CN103326707 B CN 103326707B CN 201310192228 A CN201310192228 A CN 201310192228A CN 103326707 B CN103326707 B CN 103326707B
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Abstract
The invention discloses a kind of wide input range and in receiving course, ensure the input receiving circuit of input signal duty ratio, input receiving circuit provided by the invention comprises: 6 NMOS tube, comprise 4 PMOS, comprise 1 inverter, comprise the first input signal, second input signal, output signal.The present invention has the input range of Width funtion, simultaneously the lower edges change-over time of the good balanced input signal of energy.
Description
Technical field
The present invention relates to microelectronic integrated circuit field, particularly relate to the input receiving circuit of the multiple DDR of a kind of compatibility.
Background technology
Input receiving circuit is used for the pcb board level input signal of receiving chip outside, and input signal is converted into the accessible low and high level of chip internal.Input receiving circuit, as chip internal and outside interface circuit, directly processes the non-ideal signal of external plates level.Because the non-ideal signal of plate level receive crosstalk, reflection, power-supply fluctuation, the impact of the many factors such as bullet, intersymbol interference, the input signal quality arriving chip becomes severe, affects the further process of chip internal.Special in different DDR standards, the interface voltage of various criterion is different, in time needing compatible different DDR standards, input receiving circuit needs the voltage swing difference of input signal to be processed larger, and this has higher requirement to the performance of input receiving circuit.In addition, all sample because DDR is the rising edge of signal and trailing edge, therefore, input receiving circuit needs there is approximately uniform transfer delay to the rising edge of external signal and trailing edge, and rising edge transforms the sampling nargin difference directly decreasing chip internal of time delay with trailing edge.
Fig. 1 shows a kind of traditional input receiving circuit, wherein, MN1 provides tail current source for whole input receiving circuit, MN2 and MN3 two NMOS tube are Differential Input receiving terminal, Vref is input reference voltage, its value is the half of supply voltage VCC, and IN is input signal, MP1 and MP2 two PMOS form the current mirror load of input receiving circuit.When IN is higher than Vref time, the pull-down current of MN3 is greater than the pull-up current of MP2, and the input step-down of inverter INV1, OUT uprises.When IN is lower than Vref time, the pull-down current of MN3 is less than the pull-up current of MP2, and the input of inverter INV1 uprises, OUT step-down.
Tradition input receiving circuit shown in Fig. 1 has two shortcomings: first, open input to pipe MN2, the common-mode voltage of MN3 is too high, MN2 is opened, the threshold voltage that then voltage of Vref is at least MN2 adds the overdrive voltage of MN1, generally, the threshold voltage of MN2 is about 0.6V, MN1 overdrive voltage is at about 0.15V, the minimum gate voltage of such unlatching MN2 and MN3 is about 0.75V, under DDR2 standard, Vref is 0.9V, this circuit can work, under DDR3 and LPDDR2, Vref is 0.75V and 0.6V, such structure cannot meet the demands, when with PMOS as input to pipe time, also same problem is had.Second, even if time under DDR2, Vref is 0.9V, when IN current potential is less than 0.75V time, MN3 is cut-off state, and when IN is greater than 0.9V time, MN3 is in opening always, the consequence caused like this be input receiving circuit to the rising edge of IN and the gain of trailing edge greatly different, and when be IN being rising edge, MN3 mono-direct-open, the time delay of IN to OUT is less, time IN is trailing edge, MN3 is in off state time most, the time delay of IN to OUT is larger, so just cause input receiving circuit and have different reception delays to lower edges, thus cause the duty ratio of OUT signal low and high level to change, because DDR is bilateral along standard for manual sampling, change in duty cycle directly reduces sampling window.Analysis above shows equally, and in time inputting receiving circuit and need the DDR of compatible many standards, it is more obvious that two above-mentioned shortcomings show.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of guard method and circuit of multiple voltage domain power supply adjusting type voltage controlled oscillator.
For achieving the above object, technical scheme provided by the invention is: the input receiving circuit that the present invention relates to the multiple DDR of a kind of compatibility, comprising: the first NMOS tube (MN1), and its grid connects a bias voltage, source ground current potential; Second NMOS tube (MN2), its grid connects above-mentioned identical bias voltage, source ground current potential; 3rd NMOS tube (MN3), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1); 4th NMOS tube (MN4), its grid connects the drain electrode of the 3rd NMOS tube (MN3), and source electrode connects the drain electrode of the first NMOS tube (MN1), and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3); 5th NMOS tube (MN5), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the second NMOS tube (MN2); First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3); Second PMOS (MP2), its grid connects the drain electrode of the first PMOS (MP1), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the first PMOS (MP1); 3rd PMOS (MP3), its grid connects the grid of the second PMOS (MP2), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 5th NMOS tube (MN5); 4th PMOS (MP4), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd PMOS (MP3).
Preferably, comprise further: the first inverter (INV1), its input connects the drain electrode of the 4th PMOS (MP4), exports the output signal OUT into described input receiving circuit.
Preferably, the breadth length ratio of described 5th NMOS tube (MN5) is the breadth length ratio of described 3rd NMOS tube (MN3) and the breadth length ratio sum of described 4th NMOS tube (MN4).
Another technical scheme provided by the invention is: the input receiving circuit of the multiple DDR of a kind of compatibility, comprising: the first NMOS tube (MN1), and its grid connects a bias voltage, source ground current potential;
Second NMOS tube (MN2), its grid connects above-mentioned identical bias voltage, source ground current potential; 3rd NMOS tube (MN3), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1); 4th NMOS tube (MN4), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the second NMOS tube (MN2); First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3); Second PMOS (MP2), its grid connects the drain electrode of the first PMOS (MP1), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the first PMOS (MP1); 3rd PMOS (MP3), its grid connects the grid of the second PMOS (MP2), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 4th NMOS tube (MN4); 4th PMOS (MP4), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd PMOS (MP3).
Preferably, comprise further: the first inverter (INV1), its input connects the drain electrode of the 4th PMOS (MP4), exports the output signal OUT into described input receiving circuit.
Another technical scheme provided by the invention is: the input receiving circuit of the multiple DDR of a kind of compatibility, is characterized in that, comprising: the first NMOS tube (MN1), and its grid connects a bias voltage, source ground current potential; Second NMOS tube (MN2), its grid connects above-mentioned identical bias voltage, source ground current potential; 3rd NMOS tube (MN3), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1); 4th NMOS tube (MN4), its grid connects its drain electrode and connects with the drain electrode of the 3rd NMOS tube (MN3), the drain electrode of source electrode first NMOS tube (MN1); 5th NMOS tube (MN5), its grid connects the grid of the 4th NMOS tube (MN4), and source electrode connects the drain electrode of the second NMOS tube (MN2); 6th NMOS tube (MN6), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the second NMOS tube (MN2), and drain electrode connects the drain electrode of the 5th NMOS tube (MN5); First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3); Second PMOS (MP2), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 6th NMOS tube (MN6).
Preferably, comprise further: the first inverter (INV1), its input connects the drain electrode of the second PMOS (MP2), exports the output signal OUT into described input receiving circuit.
Another technical scheme provided by the invention is: the input receiving circuit of the multiple DDR of a kind of compatibility, is characterized in that, comprising: the first NMOS tube (MN1), and its grid connects a bias voltage, source ground current potential; Second NMOS tube (MN2), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1); 3rd NMOS tube (MN3), its grid connects the drain electrode of the second NMOS tube (MN2), and source electrode connects the drain electrode of the first NMOS tube (MN1), and drain electrode connects the drain electrode of the second NMOS tube (MN2); 4th NMOS tube (MN4), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the first NMOS tube (MN1); First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the second NMOS tube (MN2); Second PMOS (MP2), its grid connects the first PMOS (MP1) drain electrode, and source electrode connects supply voltage, and drain electrode connects the first PMOS (MP1) drain electrode; 3rd PMOS (MP3), its grid connects the grid of the second PMOS (MP2), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 4th NMOS tube (MN4); 4th PMOS (MP4), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd PMOS (MP3).
Preferably, comprise further: the first inverter (INV1), its input connects the drain electrode of the 4th PMOS (MP4), exports the output signal OUT into described input receiving circuit.
Preferably, the breadth length ratio of described 4th NMOS tube (MN4) is the breadth length ratio of the second NMOS tube (MN2) and the breadth length ratio sum of the 3rd NMOS tube (MN3).
Relative to prior art, input receiving circuit provided by the invention, has the input range of Width funtion, simultaneously the lower edges change-over time of the good balanced input signal of energy.
Accompanying drawing explanation
Below in conjunction with drawings and embodiments, the invention will be further described:
Fig. 1 is a kind of traditional input receiving circuit;
The input receiving circuit of the multiple DDR of compatibility that Fig. 2 provides for first embodiment of the invention;
The input receiving circuit of the multiple DDR of compatibility that Fig. 3 provides for second embodiment of the invention;
The input receiving circuit of the multiple DDR of compatibility that Fig. 4 provides for third embodiment of the invention;
The input receiving circuit of the multiple DDR of compatibility that Fig. 5 provides for four embodiment of the invention.
Embodiment
Describe the present invention below with reference to each execution mode shown in the drawings.But these execution modes do not limit the present invention, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection scope of the present invention.
As shown in Figure 2, input receiving circuit provided by the invention comprises NMOS tube MN1, MN2, MN3, MN4, MN5, comprises PMOS MP1, MP2, MP3, MP4, comprises an inverter INV1, comprises the first input signal Vref, the second input signal IN, output signal OUT.
The grid of NMOS tube MN1 and NMOS tube MN2 connects a bias voltage, MN1 and MN2 provides bias current for inputting receiving circuit, and when inputting receiving circuit and not working, bias voltage can be pulled to ground level, thus realizes low-power consumption.
The source ground current potential of NMOS tube MN1 and NMOS tube MN2, the drain electrode of NMOS tube MN1 is connected with the source electrode of the source electrode of NMOS tube MN3 and NMOS tube MN4, the grid of NMOS tube MN3 meets the first input signal Vref of input receiving circuit, the drain electrode of NMOS tube MN3 meets node P1, grid and the drain electrode of NMOS tube MN4 all meet node P1, form diode structure.The source electrode of NMOS tube MN5 connects the drain electrode of NMOS tube MN2, the grid of NMOS tube MN5 meets the second input signal IN of input receiving circuit, the drain electrode of NMOS tube MN5 connects the input of inverter INV1, and in order to ensure the balance of DC point, the breadth length ratio of MN5 should be MN3 and MN4 sum.The grid of PMOS MP1 meets the first input signal Vref of input receiving circuit, the source electrode of PMOS MP1 meets supply voltage VCC, the drain electrode of PMOS MP1 meets node P1, the drain electrode of the grid of PMOS MP2 all meets node P1, form diode structure, the source electrode of PMOS MP2 meets supply voltage VCC, the grid of PMOS MP3 meets node P1, thus form the current mirror of MP2 to MP3, the source electrode of PMOS MP3 meets supply voltage VCC, together with the drain electrode of PMOS MP3 connects with the drain electrode of PMOS MP4 simultaneously and the input of inverter INV1 connect, the source electrode of PMOS MP4 meets supply voltage VCC, the grid of PMOS MP4 meets the second input signal IN of input receiving circuit, the output signal OUT of inverter INV1 is the output of input receiving circuit.
The PMOS MP1 that the first input signal Vref inputting receiving circuit connects and NMOS tube MN3 forms the first input end of input receiving circuit, PMOS MP2 and PMOS MP1 is connected in parallel, and the grid of PMOS MP2 forms diode structure together with connecing with drain electrode, NMOS tube MN4 and NMOS tube MN3 is connected in parallel, and the grid of NMOS tube MN4 and drain electrode are connected to form diode structure.The PMOS MP2 of diode form and NMOS tube MN4 as the load of Vref input pipe MP1 and MN3, for PMOS MP3 provides a suitable gate bias voltage.By NMOS tube MN1, MN3, MN4 and PMOS MP1, the branch road that MP2 is formed, when in order to the different standard of compatibility, Vref voltage have larger different time, in PMOS MP1 and NMOS tube MN3, a pipe is had at least to be conducting, namely this branch road still can normally work, and by PMOS MP3.MP4, and the branch road be made up of NMOS tube MN2.MN5 also has same effect, the input voltage range that this guarantees input receiving circuit of the present invention is very wide, voltage standard that can be compatible different.
PMOS MP3 injects the electric current relevant with Vref to the drain electrode of PMOS MP4 and the drain electrode of NMOS tube MN5, thus the turnover voltage point ensureing the input of inverter INV1 is the result that IN and Vref compares, namely when IN is greater than Vref, being input as of inverter INV1 is low, when IN is less than Vref, inverter INV1 is input as height.The pull-up of inverter INV1 input is by PMOS MP4 charging complete, the drop-down electric discharge by NMOS tube MN5 of inverter INV1 input completes, and PMOS and NMOS tube have same current-voltage characteristic, thus ensure that the pull-up of inverter INV1 input and the approximate equilibrium of pull-down current, and input signal IN only has the time delay of a MOS device to the input of inverter, and then ensure that the balance of lower edges transfer delay, the duty ratio of signal from IN to OUT is not changed substantially.
When with Vref being 0.9V and 0.6V below, IN is uprised as example is to elaborate advantage of the present invention and operation principle by low.When VCC is 1.8V, Vref is 0.9V, NMOS tube MN3 and PMOS MP1 is in conducting state, P1 node voltage is by the PMOS MP1 of parallel connection and MP2, and the NMOS tube MN3 of parallel connection and MN4 dividing potential drop obtain, the voltage that P1 obtains is used for the grid of bias PMOS pipe MP3, size like this as PMOS MP2 and MP3 is equal, the size of PMOS MP1 and MP4 is equal, NMOS tube MN5 is of a size of MN3 and MN4 sum, and when NMOS tube MN1 is the same with MN2 bias current, article two, branch road has structure and the size of balance, the turnover voltage point of now this input receiving circuit is just in time the electrical voltage point that IN and Vref is equal.When IN rises to Vref by low level, the pull-down current of NMOS tube MN5 is less than the pull-up current sum of PMOS MP3 and MP4, and the input of inverter INV1 is high level, and OUT exports as low level.When IN rises to high level by Vref, the pull-down current of NMOS tube MN5 is greater than the pull-up current sum of PMOS MP3 and MP4, and the input of inverter INV1 becomes low level, and OUT exports as high level.When input signal IN is by there being similar analysis when high step-down, do not introduce here.
When VCC is 1.2V, Vref is 0.6V, because the voltage opening NMOS tube MN3 is about 0.75V, NMOS tube MN3 turns off, PMOS MP1 is in critical conduction mode, P1 node voltage is by the PMOS MP1 of parallel connection and MP2, and NMOS tube MN4 dividing potential drop obtains, the voltage that P1 obtains is used for the grid of bias PMOS pipe MP3, size like this as PMOS MP2 and MP3 is equal, the size of PMOS MP1 and MP4 is equal, NMOS tube MN5 is of a size of MN3 and MN4 sum, and when NMOS tube MN1 is the same with MN2 bias current, article two, branch road has structure and the size of balance, the turnover voltage point of now this input receiving circuit is just in time the electrical voltage point that IN and Vref is equal.When IN rises to Vref by low level, the pull-down current of NMOS tube MN5 is less than the pull-up current sum of PMOS MP3 and MP4, and the input of inverter INV1 is high level, and OUT exports as low level.When IN rises to high level by Vref, the pull-down current of NMOS tube MN5 is greater than the pull-up current sum of PMOS MP3 and MP4, and the input of inverter INV1 becomes low level, and OUT exports as high level.When input signal IN is by there being similar analysis when high step-down, do not introduce here.
In the present invention, the one end of the input receiving circuit be made up of PMOS MP1 and NMOS tube MN3, the other end of the input receiving circuit be made up of PMOS MP4 and NMOS tube MN5, such input structure, can ensure that the voltage of input also can normally work in large excursion on the one hand, because two inputs of the present invention are all made up of a PMOS and a NMOS tube, when voltage compare is low, PMOS input pipe can normally work, when voltage compare height, NMOS input pipe can form work.On the other hand, the input exporting inverter INV1 is by the drain electrode of PMOS MP4 and the drain drives of NMOS tube MN5, when IN rises, NMOS tube MN5 is drop-down, form the low level of INV1 input, when IN declines, PMOS MP4 pull-up, form the high level of INV1 input, therefore, the formation of INV1 input low and high level is all by the upper and lower pull-shaped one-tenth of PMOS MP4 or NMOS tube MN5, again because PMOS and NMOS tube have identical current-voltage characteristic, this compares balance with regard to making the charging and discharging currents of INV1 input, thus ensure INV1 input, and there is identical transit time on the edge up and down of INV1 output end signal, namely there is approximate same low and high level change-over time, ensure that the output signal that the present invention inputs receiving circuit has approximate identical with input signal duty ratio.
Referring to Fig. 3, is the circuit diagram of the input receiving circuit that second embodiment of the invention provides, and compared with the first execution mode, difference is to delete the NMOS tube MN4 in the first execution mode.In this embodiment, the voltage of P1 node is obtained by PMOS MP1, MP2 and NMOS tube MN3 parallel connection, such structure still can provide suitable bias voltage for PMOS MP3, makes the turnover voltage of this input receiving circuit point be the point that input signal IN and Vref is equal.The discharge and recharge of inverter INV1 input is identical with the first execution mode, so the edge transfer delay from input signal IN to inverter input is approximate equilibrium, rising edge and trailing edge all only have the time delay of a MOS device, so the input receiving circuit that the second execution mode provides, there is the input range of Width funtion equally, simultaneously can the advantage of good lower edges change-over time of balanced input signal.
Referring to Fig. 4, is the circuit diagram of the input receiving circuit that third embodiment of the invention provides, and compared with the first execution mode, difference is to delete the PMOS MP2 in the first execution mode and MP3.The voltage of P1 node is obtained by PMOS MP1 and NMOS tube MN3, MN4 dividing potential drop, and P1 node can provide suitable bias voltage for NMOS tube MN5, makes the turnover voltage point of this input receiving circuit be the point that input signal IN and Vref is equal.The discharge and recharge of inverter INV1 input is still direct to be completed by PMOS MP2 and NMOS tube MN6, so the edge transfer delay from input signal IN to inverter input is approximate equilibrium, rising edge and trailing edge all only have the time delay of a MOS device, so the input receiving circuit that the 3rd execution mode provides, there is the input range of Width funtion equally, simultaneously can the advantage of good lower edges change-over time of balanced input signal.
Refer to Fig. 5, it is the circuit diagram of the input receiving circuit that four embodiment of the invention provides, compared with the first execution mode, difference is the NMOS tube MN1 in the first structure chart and MN2 to merge into a NMOS tube, and the NMOS tube after merging provides tail current for whole input receiving circuit.Input receiving circuit does not have difference with the first execution mode in operation principle and circuit characteristic, so the input receiving circuit that the 4th execution mode provides, there is the input range of Width funtion equally, simultaneously can the advantage of good lower edges change-over time of balanced input signal.Certainly, first embodiment of the invention, the second execution mode, in the 3rd execution mode, also can replace to a NMOS tube by NMOS tube MN1 and MN2 thus obtain other example that the present invention comprises.
Those skilled in the art it is also contemplated that, the PMOS of relevant position in embodiment of the present invention is replaced to NMOS tube, the NMOS tube of relevant position is replaced to PMOS, and is exchanged by VDD-to-VSS, the input receiving circuit obtained has the advantage identical with the present invention and characteristic.
Input signal Vref and IN of input receiving circuit described in the invention, Vref are not limited to a fixed reference level, and such as, Vref and IN can be a pair differential small-signal, also can be a pair differential clock signal.The application of input receiving circuit described in the invention is also not limited to the relevant application of DDR memory.
What it may occur to persons skilled in the art that is; the present invention can also have other implementation; as long as but its technical spirit adopted is identical or close in the present invention, or any easy full of beard of making based on the present invention and change and replace all within protection scope of the present invention.
Claims (10)
1. an input receiving circuit of the multiple DDR of compatibility, is characterized in that, comprising:
First NMOS tube (MN1), its grid connects a bias voltage, source ground current potential;
Second NMOS tube (MN2), its grid connects described bias voltage, source ground current potential;
3rd NMOS tube (MN3), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1);
4th NMOS tube (MN4), its grid connects the drain electrode of the 3rd NMOS tube (MN3), and source electrode connects the drain electrode of the first NMOS tube (MN1), and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3);
5th NMOS tube (MN5), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the second NMOS tube (MN2);
First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3);
Second PMOS (MP2), its grid connects the drain electrode of the first PMOS (MP1), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the first PMOS (MP1);
3rd PMOS (MP3), its grid connects the grid of the second PMOS (MP2), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 5th NMOS tube (MN5);
4th PMOS (MP4), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd PMOS (MP3).
2. the input receiving circuit of the multiple DDR of compatibility according to claim 1, is characterized in that: comprise further: the first inverter (INV1), and its input connects the drain electrode of the 4th PMOS (MP4), exports the output signal OUT into described input receiving circuit.
3. the input receiving circuit of the multiple DDR of compatibility according to claim 1, is characterized in that: the breadth length ratio of described 5th NMOS tube (MN5) is the breadth length ratio of described 3rd NMOS tube (MN3) and the breadth length ratio sum of described 4th NMOS tube (MN4).
4. an input receiving circuit of the multiple DDR of compatibility, is characterized in that, comprising:
First NMOS tube (MN1), its grid connects a bias voltage, source ground current potential;
Second NMOS tube (MN2), its grid connects described bias voltage, source ground current potential;
3rd NMOS tube (MN3), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1);
4th NMOS tube (MN4), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the second NMOS tube (MN2);
First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3);
Second PMOS (MP2), its grid connects the drain electrode of the first PMOS (MP1), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the first PMOS (MP1);
3rd PMOS (MP3), its grid connects the grid of the second PMOS (MP2), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 4th NMOS tube (MN4);
4th PMOS (MP4), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd PMOS (MP3).
5. the input receiving circuit of the multiple DDR of compatibility according to claim 4, is characterized in that: comprise further: the first inverter (INV1), and its input connects the drain electrode of the 4th PMOS (MP4), exports the output signal OUT into described input receiving circuit.
6. an input receiving circuit of the multiple DDR of compatibility, is characterized in that, comprising:
First NMOS tube (MN1), its grid connects a bias voltage, source ground current potential;
Second NMOS tube (MN2), its grid connects described bias voltage, source ground current potential;
3rd NMOS tube (MN3), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1);
4th NMOS tube (MN4), its grid connects its drain electrode and connects with the drain electrode of the 3rd NMOS tube (MN3), the drain electrode of source electrode first NMOS tube (MN1);
5th NMOS tube (MN5), its grid connects the grid of the 4th NMOS tube (MN4), and source electrode connects the drain electrode of the second NMOS tube (MN2);
6th NMOS tube (MN6), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the second NMOS tube (MN2), and drain electrode connects the drain electrode of the 5th NMOS tube (MN5);
First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd NMOS tube (MN3);
Second PMOS (MP2), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 6th NMOS tube (MN6).
7. the input receiving circuit of the multiple DDR of compatibility according to claim 6, is characterized in that: comprise further: the first inverter (INV1), and its input connects the drain electrode of the second PMOS (MP2), exports the output signal OUT into described input receiving circuit.
8. an input receiving circuit of the multiple DDR of compatibility, is characterized in that, comprising:
First NMOS tube (MN1), its grid connects a bias voltage, source ground current potential;
Second NMOS tube (MN2), its grid connects the first input signal (Vref), and source electrode connects the drain electrode of the first NMOS tube (MN1);
3rd NMOS tube (MN3), its grid connects the drain electrode of the second NMOS tube (MN2), and source electrode connects the drain electrode of the first NMOS tube (MN1), and drain electrode connects the drain electrode of the second NMOS tube (MN2);
4th NMOS tube (MN4), its grid connects the second input signal (IN), and source electrode connects the drain electrode of the first NMOS tube (MN1);
First PMOS (MP1), its grid connects the first input signal (Vref), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the second NMOS tube (MN2);
Second PMOS (MP2), its grid connects the first PMOS (MP1) drain electrode, and source electrode connects supply voltage, and drain electrode connects the first PMOS (MP1) drain electrode;
3rd PMOS (MP3), its grid connects the grid of the second PMOS (MP2), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 4th NMOS tube (MN4);
4th PMOS (MP4), its grid connects the second input signal (IN), and source electrode connects supply voltage, and drain electrode connects the drain electrode of the 3rd PMOS (MP3).
9. the input receiving circuit of the multiple DDR of compatibility according to claim 8, is characterized in that: comprise further: the first inverter (INV1), and its input connects the drain electrode of the 4th PMOS (MP4), exports the output signal OUT into described input receiving circuit.
10. the input receiving circuit of the multiple DDR of compatibility according to claim 8, is characterized in that: the breadth length ratio of described 4th NMOS tube (MN4) is the breadth length ratio of the second NMOS tube (MN2) and the breadth length ratio sum of the 3rd NMOS tube (MN3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310192228.0A CN103326707B (en) | 2013-05-23 | 2013-05-23 | The input receiving circuit of the multiple DDR of a kind of compatibility |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310192228.0A CN103326707B (en) | 2013-05-23 | 2013-05-23 | The input receiving circuit of the multiple DDR of a kind of compatibility |
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| CN103326707A CN103326707A (en) | 2013-09-25 |
| CN103326707B true CN103326707B (en) | 2016-02-10 |
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| CN201310192228.0A Active CN103326707B (en) | 2013-05-23 | 2013-05-23 | The input receiving circuit of the multiple DDR of a kind of compatibility |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107623518B (en) * | 2017-09-26 | 2024-05-14 | 北京集创北方科技股份有限公司 | Level shifter circuit and method for applying level shifter circuit |
| CN108718194B (en) * | 2018-08-01 | 2023-11-03 | 灿芯半导体(上海)股份有限公司 | Reference level circuit for DDR receiver |
| CN109004943B (en) * | 2018-08-03 | 2019-11-01 | 陶伟珍 | A kind of method and system for the reconstruction common mode in transmitter apparatus |
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| CN1246710A (en) * | 1998-07-13 | 2000-03-08 | 三星电子株式会社 | Integrated circuit device with sychronous signal generator |
| US6507229B1 (en) * | 1999-09-24 | 2003-01-14 | Kabushiki Kaisha Toshiba | Voltage controlled delay circuit |
| CN101930787A (en) * | 2009-06-24 | 2010-12-29 | 合肥力杰半导体科技有限公司 | Internal memory interface circuit framework supporting multi-internal memory standard and implementation thereof on metal oxide semiconductor (MOS) process |
| CN102545780A (en) * | 2010-12-23 | 2012-07-04 | 鼎亿数码科技(上海)有限公司 | Biasing circuit of voltage-controlled oscillator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100366626B1 (en) * | 2000-08-14 | 2003-01-09 | 삼성전자 주식회사 | Mismatch immune duty cycle detection circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1246710A (en) * | 1998-07-13 | 2000-03-08 | 三星电子株式会社 | Integrated circuit device with sychronous signal generator |
| US6507229B1 (en) * | 1999-09-24 | 2003-01-14 | Kabushiki Kaisha Toshiba | Voltage controlled delay circuit |
| CN101930787A (en) * | 2009-06-24 | 2010-12-29 | 合肥力杰半导体科技有限公司 | Internal memory interface circuit framework supporting multi-internal memory standard and implementation thereof on metal oxide semiconductor (MOS) process |
| CN102545780A (en) * | 2010-12-23 | 2012-07-04 | 鼎亿数码科技(上海)有限公司 | Biasing circuit of voltage-controlled oscillator |
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