CN103856206A - Low-to-high logic level conversion circuit - Google Patents
Low-to-high logic level conversion circuit Download PDFInfo
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- CN103856206A CN103856206A CN201210520073.4A CN201210520073A CN103856206A CN 103856206 A CN103856206 A CN 103856206A CN 201210520073 A CN201210520073 A CN 201210520073A CN 103856206 A CN103856206 A CN 103856206A
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Abstract
The invention discloses a low-to-high logic level conversion circuit which comprises a latch, an actuator, a phase inverter and a feedback pipe. The input of the latch is a differential pair pipe which is formed by a first NMOS transistor and a second NMOS transistor, and a load of the latch is a cross coupling pair pipe which is formed by a first PMOS transistor and a second PMOS transistor. The actuator is arranged in the latch and helps the latch to be quickly turned over. The phase inverter and the feedback pipe are arranged at the output end of the latch, the feedback pipe enables a circuit output to be in a steady state when a low-voltage area is not powered, and when the low-voltage area is normally powered, normal work of the latch is not affected. By means of the low-to-high logic level conversion circuit, the probability that logic level is in an unsteady state when being converted to power level is avoided, and power consumption is reduced.
Description
Technical field
The present invention relates to mixed-signal circuit design field, particularly relate to one logic level converting circuit from low to high.
Background technology
Along with the fast development of integrated circuit technology, analog circuit and digital circuit are often integrated in same chip.Conventionally, analog circuit, for guaranteed performance, can adopt high power supply voltage; And digital circuit is in order to save power consumption, can adopt low supply voltage.In the time that logical signal is transferred to digital circuit from analog circuit, or while being transferred to analog circuit from digital circuit, just need to carry out level conversion.
In the time that logical signal is transferred to low voltage domain from high voltage domain, can adopt logic level converting circuit from high to low, common one adopts the inverter of low supply voltage just can realize.But in the time that logical signal is transferred to high voltage domain from low voltage domain, level shifting circuit is than inverter complexity, conventionally adopt one and be input as differential pair tube, load is the latch of cross-coupled pair pipe, and the latch being made up of four MOS transistor forms, as shown in Figure 1.
Referring to Fig. 1, the operation principle of traditional logic level converting circuit is from low to high as follows: when positive input terminal IN+ is low logic voltage high level, when negative input end IN-is low logic voltage low level, the first nmos pass transistor MN1 opens, and the second nmos pass transistor MN2 closes, making negative output terminal OUT-is VSS, be high voltage logic low level, positive output end OUT+ is VDD, i.e. high voltage logic high level, make the second nmos pass transistor MN2 open, the first nmos pass transistor MN1 closes simultaneously.
When input IN-is from high step-down, input IN+ is during from low uprising, because the breadth length ratio of the first nmos pass transistor MN1 and the second nmos pass transistor MN2 is than the breadth length ratio of a PMOS transistor MP1 and the 2nd PMOS transistor MP2 much larger (ratio the one PMOS transistor MP1 that driving force of the first nmos pass transistor MN1 and the second nmos pass transistor MN2 will be done and the 2nd PMOS transistor MP2 driving force are strong), the second nmos pass transistor MN2 can first drag down positive output end OUT+, has opened a PMOS transistor MP1 simultaneously.Because now the first nmos pass transistor MN1 is switched off, so a PMOS transistor MP1 can draw high negative output terminal OUT-, further turned off the 2nd PMOS transistor MP2, made positive output end OUT+ finally be pulled to VSS, negative output terminal OUT-is finally pulled to VDD.
There is following shortcoming in traditional logic level converting circuit from low to high: when high power supply voltage territory, (being VDD and VSS) establishes, but when low supply voltage territory not yet establishes (often appearing in the situation that low supply voltage territory produces by chip internal), positive input terminal IN+ and negative input end IN-are logic low, make positive output end OUT+ and negative output terminal OUT-occur not stationary state, its level may be on any level between VDD and VSS.This not stationary state may cause the subsequent conditioning circuit of its control to occur logical miss, even may cause subsequent conditioning circuit to occur significantly electric leakage.
Summary of the invention
The technical problem to be solved in the present invention is to provide one logic level converting circuit from low to high, the not stationary state that may occur can avoid logic level to be switched to power level time, and save power consumption.
For solving the problems of the technologies described above, logic level converting circuit from low to high of the present invention, comprising: a latch, and it is input as differential pair tube, and load is cross-coupled pair pipe; Described differential pair tube is made up of the first nmos pass transistor and the second nmos pass transistor, and the source electrode of the first nmos pass transistor and the second nmos pass transistor is connected with high voltage logic low level end, and this high voltage logic low level end is designated as VSS; Described cross-coupled pair pipe is made up of a PMOS transistor and the 2nd PMOS transistor, and a PMOS transistor is connected with high voltage logic high level end with the transistorized source electrode of the 2nd PMOS, and this high voltage logic high level end is designated as VDD;
Wherein, also comprise: a driver, one first inverter, one first feedback pipe;
Described driver is made up of the 3rd PMOS transistor and the 4th PMOS transistor; The transistorized source electrode of the 3rd PMOS is connected with the transistorized drain electrode of a PMOS, and its drain electrode is connected with the transistorized grid of the 2nd PMOS with the drain electrode of the first nmos pass transistor, the node note A point of this connection; The transistorized grid of the 3rd PMOS is connected with positive input terminal with the grid of the first nmos pass transistor; The transistorized source electrode of the 4th PMOS is connected with the transistorized drain electrode of the 2nd PMOS, and its drain electrode is connected with the transistorized grid of a PMOS with the drain electrode of the second nmos pass transistor, the node note B point of this connection; The transistorized grid of the 4th PMOS is connected with negative input end with the grid of the second nmos pass transistor;
Described the first feedback Guan You six PMOS transistors form, and its source electrode is connected with VDD, and its drain electrode is connected with A point, and its grid is connected with positive output end;
Described the first inverter is made up of the 3rd nmos pass transistor and the 5th PMOS transistor; The transistorized source electrode of the 5th PMOS is connected with VDD, and its drain electrode is connected with the drain electrode of the 3rd nmos pass transistor, and the node of this connection is as positive output end, and the source electrode of the 3rd nmos pass transistor is connected with VSS.
The present invention improves logic level converting circuit from low to high from structure, can eliminate the not stationary state that high voltage domain output may exist, make high voltage domain output there is definite state, guarantee that subsequent logic circuit there will not be unknown logic state, also there will not be electric leakage, thereby guaranteed the normal work of chip.Meanwhile, reversal rate of the present invention is faster, thereby has reduced its power consumption.The present invention can be applied to the mixed signal circuit under various technique.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is existing tradition logic level converting circuit schematic diagram from low to high;
Fig. 2 is the one embodiment schematic diagram of logic level converting circuit from low to high of the present invention;
Fig. 3 is another embodiment schematic diagram of logic level converting circuit from low to high of the present invention.
Embodiment
Shown in Figure 2, logic level converting circuit from low to high of the present invention in the following embodiments, comprising: a latch, and one helps described latch to realize the driver of upset rapidly, an inverter, one realizes the feedback pipe that powers on and automatically lock.
Described latch be input as differential pair tube, load is cross-coupled pair pipe (the load pipe of negative resistance form).
Described differential pair tube is made up of the first nmos pass transistor and the second nmos pass transistor, and the source electrode of the first nmos pass transistor and the second nmos pass transistor is connected with high voltage logic low level end, and this high voltage logic low level end is designated as VSS.
Described cross-coupled pair pipe is made up of a PMOS transistor MP1 and the 2nd PMOS transistor MP2, and the source electrode of a PMOS transistor MP1 and the 2nd PMOS transistor MP2 is connected with high voltage logic high level end, and this high voltage logic high level end is designated as VDD.
Described driver is made up of the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4.The source electrode of the 3rd PMOS transistor MP3 is connected with the drain electrode of a PMOS transistor MP1; The 3rd drain electrode of PMOS transistor MP3 and the drain electrode of the first nmos pass transistor MN1 are connected with the grid of the 2nd PMOS transistor MP2, the node note A point of this connection; The 3rd grid of PMOS transistor MP3 and the grid of the first nmos pass transistor MN1 are connected with positive input terminal IN+.
The source electrode of the 4th PMOS transistor MP4 is connected with the drain electrode of the 2nd PMOS transistor MP2; The 4th drain electrode of PMOS transistor MP4 and the drain electrode of the second nmos pass transistor MN2 are connected with the grid of a PMOS transistor MP1, the node note B point of this connection; The 4th grid of PMOS transistor MP4 and the grid of the second nmos pass transistor MN2 are connected with negative input end IN-.
Described feedback Guan You six PMOS transistor MP6 form, and its source electrode is connected with VDD, and its drain electrode is connected with A point, and its grid is connected with positive output end OUT+.Even if low voltage domain does not power on, described feedback pipe also can make the output of logic level converting circuit from low to high remain on stationary state; In the time that low voltage domain normally powers on, this feedback Guan Buhui affects the normal work of latch simultaneously.
Described inverter is made up of the 3rd nmos pass transistor MN3 and the 5th PMOS transistor MP5, and the source electrode of the 5th PMOS transistor MP5 is connected with VDD; The drain electrode of the 5th PMOS transistor MP5 is connected with the drain electrode of the 3rd nmos pass transistor MN3, and the node of this connection is as positive output end OUT+, and the source electrode of the 3rd nmos pass transistor MN3 is connected with VSS.
When positive input terminal IN+ is low logic voltage high level, when negative input end IN-low logic voltage low level, the first nmos pass transistor MN1 opens, and the second nmos pass transistor MN2 closes, and makes A point for low level; The 2nd PMOS transistor MP2 and the 4th PMOS transistor MP4 open, and making B point is high level, and positive output end OUT+ is high level, and the 6th PMOS transistor MP6 closes inoperative.
When positive input terminal, IN+ becomes low level from high level, when negative input end IN-becomes high level from low level, the first nmos pass transistor MN1 closes, the second nmos pass transistor MN2 opens, simultaneously because the grid voltage (being negative input end IN-) of the 4th PMOS transistor MP4 becomes high level from low level, the driving force of the 4th PMOS transistor MP4 has been weakened, drag down B point (the same with traditional logic level converting circuit from low to high, the first nmos pass transistor MN1 and the second nmos pass transistor MN2 are stronger than the driving force of a PMOS transistor MP1 and the 2nd PMOS transistor MP2), then a PMOS transistor MP1 opens.The also grow of driving force of the 3rd PMOS transistor MP3, the potential rise that A is ordered, turns off the 2nd PMOS transistor MP2, and B point current potential is further reduced, and finally makes the current potential that A is ordered become VDD, and the current potential that B is ordered becomes VSS.Positive output end OUT+ is VSS, and the 6th PMOS transistor MP6 opens.
The advantage of logic level converting circuit from low to high of the present invention is: in the time that VDD and VSS start to power on, the inverter that the 3rd nmos pass transistor MN3 and the 5th PMOS transistor MP5 form, and the 6th PMOS transistor MP6 form feedback pipe can be positive output end OUT+ clamper at VSS, A point current potential clamper is at VDD.Establish if there is high power supply voltage territory (being VDD and VSS), but the situation that low supply voltage territory not yet establishes, the first nmos pass transistor MN1 and the second nmos pass transistor MN2 close, the two-way of latch does not all have electric current, now the 3rd nmos pass transistor MN3, the 5th PMOS transistor MP5 and the 6th PMOS transistor MP6 can be all the time by positive output end OUT+ clamper at VSS, A point current potential clamper is at VDD, and the output that makes this circuit can not be not stationary state.
After low supply voltage territory establishes, if positive input terminal IN+ is low level, when negative input end IN-is high level, it is low level that its output state still keeps positive output end OUT+, and A point is high level, and B point is low level.If positive input terminal IN+ is high level, negative input end IN-is low level, the process that there will be the first of short duration nmos pass transistor MN1 and the 6th PMOS transistor MP6 simultaneously to open, but the driving force of the 6th PMOS transistor MP6 very little (conventionally making down than pipe), the first nmos pass transistor MN1 still can drag down A point current potential, and then the 4th PMOS transistor MP4 opens, and draws high B point current potential, the one PMOS transistor MP1 turns off, and further makes A point current potential reduce.In the time that A point current potential is reduced to below the turn threshold of phase-reversing tube of the 3rd nmos pass transistor MN3 and the 5th PMOS transistor MP5 composition, positive output end OUT+ becomes high level, turns off the 6th PMOS transistor MP6.
Another advantage of the present invention is, the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4 add.In traditional low to high logic level converting circuit, in the time that positive input terminal IN+ becomes high level from low level, there is the process of opening of short duration time in the first nmos pass transistor MN1 and a PMOS transistor MP1, because the grid of a PMOS transistor MP1 (being positive output end OUT+) is also in the low level of preceding state, the first nmos pass transistor MN1 can spend the long time could output OUT-pull into low level, and then open the 2nd PMOS transistor MP2, positive output end OUT+ is pulled into high level.And the present invention is after adding the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4, in the time that positive input terminal IN+ becomes high level from low level, the grid potential of the 3rd PMOS transistor MP3 raises, and makes its electric conduction resistive large, on the electric current that draws diminish, A point current potential reduces rapidly.The 2nd PMOS transistor MP2 opens, draw high B point current potential (because the breadth length ratio of the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4 is larger than the breadth length ratio of a PMOS transistor MP1 and the 2nd PMOS transistor MP2, the pull-up current when conducting resistance that the 4th PMOS transistor MP4 introduces can significantly not reduce the 2nd PMOS transistor MP2 unlatching, can not reduce pulling rate degree on current potential that B orders), the one PMOS transistor MP1 closes, and makes A point current potential further be reduced to VSS.
Shown in Figure 3, another embodiment of logic level converting circuit from low to high of the present invention is, on the basis of superincumbent embodiment, increase an inverter and a feedback pipe, be arranged on another output of latch, thus make this from low to high logic level converting circuit become both-end output from Single-end output.
The feedback Guan You eight PMOS transistor MP8 that increase form, and its source electrode is connected with VDD, and its drain electrode is connected with A point, and its grid is connected with negative output terminal OUT-.
The inverter increasing is made up of the 4th nmos pass transistor MN4 and the 7th PMOS transistor MP7, and the source electrode of the 7th PMOS transistor MP7 is connected with VDD; The drain electrode of the 7th PMOS transistor MP7 is connected with the drain electrode of the 4th nmos pass transistor MN4, and the node of this connection is as negative output terminal OUT-, and the source electrode of the 4th nmos pass transistor MN4 is connected with VSS.
By specific embodiment, the present invention is described in detail to explanation above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can also make many improvement and distortion, and these are all considered as protection scope of the present invention.
Claims (2)
1. a logic level converting circuit from low to high, comprises; One latch, it is input as differential pair tube, and load is cross-coupled pair pipe; Described differential pair tube is made up of the first nmos pass transistor and the second nmos pass transistor, and the source electrode of the first nmos pass transistor and the second nmos pass transistor is connected with high voltage logic low level end, and this high voltage logic low level end is designated as VSS; Described cross-coupled pair pipe is made up of a PMOS transistor and the 2nd PMOS transistor, and a PMOS transistor is connected with high voltage logic high level end with the transistorized source electrode of the 2nd PMOS, and this high voltage logic high level end is designated as VDD;
It is characterized in that, also comprise: a driver, one first inverter, one first feedback pipe;
Described driver is made up of the 3rd PMOS transistor and the 4th PMOS transistor; The transistorized source electrode of the 3rd PMOS is connected with the transistorized drain electrode of a PMOS, and its drain electrode is connected with the transistorized grid of the 2nd PMOS with the drain electrode of the first nmos pass transistor, the node note A point of this connection; The transistorized grid of the 3rd PMOS is connected with positive input terminal with the grid of the first nmos pass transistor; The transistorized source electrode of the 4th PMOS is connected with the transistorized drain electrode of the 2nd PMOS, and its drain electrode is connected with the transistorized grid of a PMOS with the drain electrode of the second nmos pass transistor, the node note B point of this connection; The transistorized grid of the 4th PMOS is connected with negative input end with the grid of the second nmos pass transistor;
Described the first feedback Guan You six PMOS transistors form, and its source electrode is connected with VDD, and its drain electrode is connected with A point, and its grid is connected with positive output end;
Described the first inverter is made up of the 3rd nmos pass transistor and the 5th PMOS transistor; The transistorized source electrode of the 5th PMOS is connected with VDD, and its drain electrode is connected with the drain electrode of the 3rd nmos pass transistor, and the node of this connection is as positive output end, and the source electrode of the 3rd nmos pass transistor is connected with VSS.
2. the circuit as described in right 1, is characterized in that: also comprise one second inverter and one second feedback pipe, be arranged on another output of described latch; Make described circuit become both-end output from Single-end output;
Described the second feedback Guan You eight PMOS transistors form, and its source electrode is connected with VDD, and its drain electrode is connected with A point, and its grid is connected with negative output terminal;
Described the second inverter is made up of the 4th nmos pass transistor and the 7th PMOS transistor, the transistorized source electrode of the 7th PMOS is connected with VDD, its drain electrode is connected with the drain electrode of the 4th nmos pass transistor, and the node of this connection is as negative output terminal, and the source electrode of the 4th nmos pass transistor is connected with VSS.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221206A (en) * | 1997-12-26 | 1999-06-30 | 株式会社日立制作所 | Level conversion circuit and semiconductor integrated circuit device employing level conversion circuit |
| CN1229248A (en) * | 1997-12-24 | 1999-09-22 | 日本电气株式会社 | Voltage converting buffer circuit |
| US6407579B1 (en) * | 2000-01-20 | 2002-06-18 | Koninklijke Philips Electronics N.V. | Fast high voltage level shifter with gate oxide protection |
| US20060197579A1 (en) * | 2000-01-27 | 2006-09-07 | Renesas Technology Corporation | Semiconductor device with level converter having signal-level shifting block and signal-level determination block |
| CN101335518A (en) * | 2007-06-29 | 2008-12-31 | 株式会社瑞萨科技 | Semiconductor device |
-
2012
- 2012-12-06 CN CN201210520073.4A patent/CN103856206A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1229248A (en) * | 1997-12-24 | 1999-09-22 | 日本电气株式会社 | Voltage converting buffer circuit |
| CN1221206A (en) * | 1997-12-26 | 1999-06-30 | 株式会社日立制作所 | Level conversion circuit and semiconductor integrated circuit device employing level conversion circuit |
| US6407579B1 (en) * | 2000-01-20 | 2002-06-18 | Koninklijke Philips Electronics N.V. | Fast high voltage level shifter with gate oxide protection |
| US20060197579A1 (en) * | 2000-01-27 | 2006-09-07 | Renesas Technology Corporation | Semiconductor device with level converter having signal-level shifting block and signal-level determination block |
| CN101335518A (en) * | 2007-06-29 | 2008-12-31 | 株式会社瑞萨科技 | Semiconductor device |
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| CN104333366A (en) * | 2014-10-30 | 2015-02-04 | 深圳市国微电子有限公司 | Digital IO circuit |
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| CN104467796A (en) * | 2014-11-07 | 2015-03-25 | 深圳市国微电子有限公司 | Slew-rate-limited driver |
| CN104868907B (en) * | 2015-05-08 | 2017-10-31 | 宁波大学 | A kind of low-voltage high-performance low-power-consumption C cell |
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| CN114640339A (en) * | 2022-03-25 | 2022-06-17 | 温州大学 | Level conversion circuit without power-on unsteady state |
| CN114640339B (en) * | 2022-03-25 | 2024-06-11 | 温州大学 | Level conversion circuit without power-on indefinite state |
| CN114978151A (en) * | 2022-05-25 | 2022-08-30 | 西安电子科技大学 | Cross coupling type level conversion circuit with pull-down structure |
| CN114978151B (en) * | 2022-05-25 | 2023-03-21 | 西安电子科技大学 | Cross coupling type level conversion circuit with pull-down structure |
| CN116366051A (en) * | 2023-03-21 | 2023-06-30 | 辰芯半导体（深圳）有限公司 | Level shift circuit and level shifter |
| CN116366051B (en) * | 2023-03-21 | 2024-02-13 | 辰芯半导体（深圳）有限公司 | Level shift circuit and level shifter |
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Application publication date: 20140611 |
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