CN106899288B - Level conversion circuit - Google Patents
Level conversion circuit Download PDFInfo
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- CN106899288B CN106899288B CN201710092872.9A CN201710092872A CN106899288B CN 106899288 B CN106899288 B CN 106899288B CN 201710092872 A CN201710092872 A CN 201710092872A CN 106899288 B CN106899288 B CN 106899288B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The invention relates to a level switching circuit, wherein a source electrode of a first PMOS (P-channel metal oxide semiconductor) tube is connected with an external power supply, a drain electrode of the first PMOS tube is connected with a source electrode of a third PMOS tube, and a grid electrode of the first PMOS tube is connected with a drain electrode of a fourth PMOS tube; the source electrode of the second PMOS tube is connected with an external power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube; the drain electrode of a third PMOS tube is connected with the source electrode of a first NMOS tube, the drain electrode of a fourth PMOS tube is connected with the source electrode of a second NMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth PMOS tube are connected with a phase inverter, input signals of the grid electrode of the second NMOS tube and the grid electrode of the fourth PMOS tube are the same as input signals of the phase inverter, the input signals of the grid electrode of the third PMOS tube and the grid electrode of the first NMOS tube are opposite, the control end of the latch module receives an external threshold signal, the first end of the latch module is grounded, and the second end of the latch module is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube and the.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a level shifter circuit.
Background
In many semiconductor integrated circuits, circuit signals are not very stable, and when interference or an error signal of a previous stage circuit is received, a next stage circuit is easy to malfunction, which is particularly obvious in a level conversion circuit. The level shift circuit is to convert a low level signal to a high level signal or convert a high level signal to a low level signal, and when the power supply of the low level signal is powered down, the signal cannot be normally transmitted, so that the received signal of a high voltage power supply domain is wrong, and a large leakage problem may occur.
The conventional level shift circuit has the above-mentioned problem that when the low-level signal power supply is powered off, an uncertain level value is output, that is, the input state of the lower-level circuit is neither a high level nor a low level but an intermediate value between the high level and the low level, so that the lower-level logic circuit is easy to generate a large current and damage related devices.
Disclosure of Invention
Therefore, it is necessary to provide a level shift circuit capable of ensuring a stable output signal and stabilizing an input state of a lower circuit, in order to solve the problem of unstable output caused by instantaneous power failure or power failure of the conventional level shift circuit.
A level switching circuit comprises a phase inverter, a level converter and a latch module which are connected in sequence;
the level shifter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube; the source electrode of the first PMOS tube is connected with an external power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube; the source electrode of the second PMOS tube is connected with an external power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube; the drain electrode of a third PMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth PMOS tube are connected with the phase inverter, the input signal of the grid electrode of the second NMOS tube and the input signal of the grid electrode of the fourth PMOS tube are the same as the input end signal of the phase inverter, and the input signal of the grid electrode of the third PMOS tube and the input signal of the grid electrode of the first NMOS tube are the same as the output end signal of the phase inverter; the drain electrode of the fourth PMOS tube is connected with the source electrode of the second NMOS tube, the input end of the phase inverter is used as the input end of the level conversion circuit, and the source electrode of the first NMOS tube is used as the output end of the level conversion circuit;
the control end of the latch module receives an external threshold signal, the first end of the latch module is grounded, and the second end of the latch module is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube.
The level conversion circuit comprises a phase inverter, a level converter and a latch module which are sequentially connected, wherein the level converter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube, the control end of the latch module receives an external threshold signal, the first end of the latch module is grounded, the second end of the latch module is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube, the latch module is started through the external threshold signal, and the voltage of the output end of the level conversion circuit is still stable when the level conversion circuit is powered off or powered down instantly.
Drawings
FIG. 1 is a schematic circuit diagram of a level shifter module of a level shifter circuit;
FIG. 2 is a circuit diagram of a level shifter circuit in one embodiment;
FIG. 3 is a circuit schematic of a level shifting circuit in one embodiment;
FIG. 4 is a diagram illustrating the potential of each node in the level shifter circuit shown in FIG. 3 according to an embodiment.
Detailed Description
A level shift module of a level shift circuit is shown in fig. 1, and the level shift circuit includes 4 PMOS transistors (MP1, MP2, MP3, and MP4), 2 NMOS transistors (MN1 and MN2), 2 inverters (VD1 and VD2), 1 input voltage port Vin, and 1 output voltage port Vout.
When the input voltage of the input voltage port Vin is at a logic low level 0, for example, ground, a logic high level 1 is output to the gate of the first NMOS transistor MN1 through the inverter VD1, so that the first NMOS transistor MN1 is turned on, and the output voltage of the output voltage port Vout is 0V under the pull-down action of MN 1.
When the input voltage of the input voltage port Vin is a logic high level 1, for example, a voltage V11, a logic low level is output to the gate of the first NMOS transistor MN1 and the gate of the third PMOS transistor MP3 after passing through the inverter VD1, so that the first NMOS transistor MN1 is turned off, the gate of the third PMOS transistor MP3 is a logic low level, so that the third PMOS transistor MP3 is turned on, a logic high level is output to the gate of the second NMOS transistor MN2 and the gate of the fourth PMOS transistor MP4 after passing through the inverter VD2, the second NMOS transistor MN2 is turned on, the fourth PMOS transistor MP4 is turned off, the gate of the first PMOS transistor MP1 is connected to the source of the second NMOS transistor MN2, that is, the gate of the MP1 is a logic low level, so that the first PMOS transistor MP1 is turned on, and the output voltage Vout of the level conversion circuit is a voltage V22, so that the voltage V22 is converted from the voltage V22.
When the first voltage is suddenly powered off, the first voltage is 0, the inverter stops working, so that the gate voltages of MN1 and MN2 are both 0, and the gate voltages of MP1 and MP2 are in an unstable state, in which case, the output voltage of the output voltage port of the level conversion circuit may be logic low level 0, logic high level 1 or an intermediate state, thereby affecting the stable state of the subsequent circuit.
In one embodiment, as shown in fig. 2, a level shifter circuit includes an inverter, a level shifter and a latch module connected in sequence;
the level shifter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube; the source electrode of the first PMOS tube is connected with an external power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube; the source electrode of the second PMOS tube is connected with an external power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube; the drain electrode of a third PMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth PMOS tube are connected with the phase inverter, the input signal of the grid electrode of the second NMOS tube and the input signal of the grid electrode of the fourth PMOS tube are the same as the input end signal of the phase inverter, and the input signal of the grid electrode of the third PMOS tube and the input signal of the grid electrode of the first NMOS tube are the same as the output end signal of the phase inverter; the drain electrode of the fourth PMOS tube is connected with the source electrode of the second NMOS tube, the input end of the phase inverter is used as the input end of the level conversion circuit, and the source electrode of the first NMOS tube is used as the output end of the level conversion circuit;
the control end of the latch module receives an external threshold signal, the first end of the latch module is grounded, and the second end of the latch module is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube.
The level conversion circuit comprises a phase inverter, a level converter and a latch module which are sequentially connected, wherein the level converter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube, the control end of the latch module receives an external threshold signal, the first end of the latch module is grounded, the second end of the latch module is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube, the latch module is started through the external threshold signal, and the output voltage of the output end of the level conversion circuit is still stable when the level conversion circuit is powered off or loses power instantly.
In one embodiment, the latch module of the level shift circuit comprises a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;
the source electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the third NMOS tube is grounded; the source electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the fourth NMOS tube is grounded; the source electrode of the fifth NMOS tube is respectively connected with the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the drain electrode of the fifth NMOS tube is grounded, and the grid electrode of the fifth NMOS tube receives an external threshold signal.
The level conversion circuit comprises a phase inverter, a level converter and a latch module which are connected in sequence, wherein the level converter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube; the source electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the fourth NMOS tube is grounded; the source electrode of the fifth NMOS tube is connected with the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube respectively, the drain electrode of the fifth NMOS tube is connected with the ground, the grid electrode of the fifth NMOS tube receives an external threshold signal, the latch module is started through the threshold signal, and the output voltage of the output end of the level conversion circuit is still stable when the level conversion circuit is powered off or powered down instantly.
In one embodiment, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor of the level shift circuit are PMOS transistors of the same type, the first NMOS transistor and the second NMOS transistor are NMOS transistors of the same type, and the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor of the level shift circuit latch module are NMOS transistors of the same type, which facilitates the production of the level shift circuit.
In one embodiment, as shown in fig. 2, the inverter of the level shift circuit includes a first CMOS inverter, the gate of the second NMOS transistor and the gate of the fourth PMOS transistor are connected to the input terminal of the first CMOS inverter, and the gate of the third PMOS transistor and the gate of the first NMOS transistor are connected to the output terminal of the first CMOS inverter. In another embodiment, as shown in fig. 3, the inverter of the level shift circuit further includes a second CMOS inverter connected to the first CMOS inverter, an input terminal of the first CMOS inverter is used as an input terminal of the inverter, an output terminal of the second CMOS inverter is used as an output terminal of the inverter, a gate of the third PMOS transistor and a gate of the first NMOS transistor are connected to the output terminal of the first CMOS inverter, and a gate of the second NMOS transistor and a gate of the fourth PMOS transistor are connected to the output terminal of the second CMOS inverter. Specifically, each CMOS inverter includes a fifth PMOS transistor and a sixth NMOS transistor, a source of the fifth PMOS transistor is connected to an external power supply, a gate of the fifth PMOS transistor is connected to a gate of the sixth NMOS transistor and serves as an input terminal of the inverter, a drain of the fifth PMOS transistor is connected to a drain of the sixth NMOS transistor and serves as an output terminal of the inverter, and a source of the sixth NMOS transistor is grounded. The CMOS phase inverter is formed by connecting a PMOS tube and an NMOS tube in series, the PMOS tube is used as a load tube, the NMOS tube is used as an input tube, the power consumption can be greatly reduced due to the configuration, in two logic states, one of the two transistors is always cut off, the processing speed can be well improved, and the resistance of the CMOS phase inverter is relatively lower compared with that of the NMOS type phase inverter and the PMOS type phase inverter.
In one embodiment, the external power supply of the level shift circuit outputs a first voltage, the input terminal of the inverter receives an external voltage, the input range of the external voltage is 0 to a second voltage, the first voltage is greater than the second voltage, the input voltage at the input terminal of the level shift circuit is the second voltage, and the output voltage at the output terminal of the level shift circuit is the first voltage. The level shift circuit comprises a buffer unit, the input end of the level shift circuit is connected with the level shift circuit through the buffer unit, the buffer unit comprises two buffer phase inverters which are connected in sequence, the buffer unit strengthens the driving capability of the level shift circuit, and shapes the input signal of the input end, so that the stability of the input signal can be effectively improved, and the influence of the unstable input signal on the level shift circuit is avoided.
The operation principle of the level shift circuit is explained by taking the level shift circuit with latch shown in fig. 3 as an example, and the circuit structure of the level shift circuit includes: (1) a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3 and a fourth PMOS transistor MP 4; (2) a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN 5; (3) a first inverter VD1, a second inverter VD 2; (4) input voltage port Vin, output voltage port Vout, threshold port Vlatch.
The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the first NMOS transistor MN1, the second NMOS transistor MN2, the first inverter VD1, the second inverter VD2, the input voltage port Vin, and the output voltage port Vout are connected to the same circuit structure of the level shift module of the level shift circuit in fig. 1.
The source electrode of the third NMOS transistor MN3 is connected with the drain electrode of the third PMOS transistor MP3, the grid electrode of the third NMOS transistor MN3 is connected with the drain electrode of the fourth PMOS transistor MP4, and the drain electrode of the third NMOS transistor MN3 is grounded; the source electrode of the fourth NMOS transistor MN4 is connected with the drain electrode of the fourth PMOS transistor MP4, the grid electrode of the fourth NMOS transistor MN4 is connected with the drain electrode of the third PMOS transistor MP3, and the drain electrode of the fourth NMOS transistor MN4 is grounded; the source of the fifth NMOS transistor MN5 is connected to the drain of the first NMOS transistor MN1, the drain of the fifth NMOS transistor MN5 is grounded, and the gate of the fifth NMOS transistor MN5 is connected to the threshold port Vlatch.
The latching process of the level shift circuit is as follows:
when the input signal to the threshold port Vlatch is at logic high 1, MN5 is turned on, node e is pulled low to 0, and the level shift circuit is in the non-latch state. At this time, when the input voltage of the input voltage port Vin is a logic low level 0, the node a passing through the first inverter VD1 is a logic high level 1, the gate of the first NMOS transistor MN1 and the gate of the third PMOS transistor MP3 are logic high levels, the first NMOS transistor MN1 is turned on, the third PMOS transistor MP3 is turned off, the node c is pulled down to be a logic low level 0, and the gate of the fourth NMOS transistor MN4 is a logic low level, so that the fourth NMOS transistor MN4 is turned off; after passing through the second inverter VD2, the node b is at a logic low level 0, the second NMOS transistor MN2 is not turned on, the fourth PMOS transistor MP4 is turned on, and the node d is at a logic high level 1; since the node d is at a logic high level 1 and the gate of the third NMOS transistor MN3 is at a logic high level, the third NMOS transistor MN3 is turned on and grounded, and the node c is at a logic low level 0, at which time the output voltage of the output voltage port Vout is at a logic low level 0.
The input signal of the threshold port Vlatch is changed into a logic low level 0, the fifth NMOS tube MN5 is cut off, the node e is a high level 1, and the level conversion circuit enters a latch state; when the input voltage port has a signal failure, the node b, which is originally at logic low level 0, is changed to logic high level 1, because the node e is at logic high level 1, the node d is still at logic high level 1, the node c is pulled down to logic low level 0, and the output voltage of the output voltage port Vout is still at logic low level 0.
When the input signal of the input voltage port Vin is logic low level 0, the potential conditions of the circuit nodes of the level shift circuit before and after latching are as shown in fig. 4, before latching: in fig. 3, a node a is logic high level 1, a node b is logic low level 0, a node c is logic level 0, a node d is logic high level 1, and a node e is logic low level 0; after latching, in fig. 3, the node a is at logic high level 1, the node b is at logic high level 1, the node c is at logic high level 0, the node d is at logic high level 1, and the node e is at logic high level 1.
Similarly, the same applies to the above analysis when the input signal of the input voltage port Vin is a logic high level 1.
When the input signal to the threshold port Vlatch is at logic high 1, MN5 is turned on, node e is pulled low to 0, and the level shift circuit is in the non-latch state. At this time, when the input voltage of the input voltage port Vin is at a logic high level 1, the node a passing through the first inverter VD1 is at a logic low level 0, the gate of the first NMOS transistor MN1 and the gate of the third PMOS transistor MP3 are at a logic low level, the first NMOS transistor MN1 is turned off, and the third PMOS transistor MP3 is turned on; after passing through the second inverter VD2, the node b is at a logic high level 1, the second NMOS transistor MN2 is turned on, the fourth PMOS transistor MP4 is turned off, and the node d is at a logic low level 0; since the node d is at a logic low level 0 and the gate of the third NMOS transistor MN3 is at a logic low level, the third NMOS transistor MN3 is turned off, the first PMOS transistor MP1 is turned on, and the node c is at a logic high level 1, at which time the output voltage of the output voltage port Vout is at a logic high level 1.
The input signal of the threshold port Vlatch is changed into a logic low level 0, the fifth NMOS tube MN5 is cut off, the node e is a high level 1, and the level conversion circuit enters a latch state; when the input voltage port has a signal failure, the node a, which is originally at the logic low level 0, is turned to the logic high level 1, the third PMOS transistor MP3 is turned off, the first NMOS transistor MN1 is turned on, and the node e is at the logic high level 1, so the node c is at the logic high level 1, and the output voltage of the output voltage port Vout is still at the logic high level 1.
Based on the circuit structure, when the input voltage of the input voltage port Vin is continuously a certain level, the latch module is controlled to be started by the input signal of the threshold value port Vlatch, and after the latch function module is started, the output voltage can be effectively ensured to be continuously stable, so that the input signal of the next stage circuit is kept continuously stable, and the influence of external interference, such as severe Vin change, inverter damage, temporary signal interruption and the like, is avoided.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. A level conversion circuit is characterized by comprising an inverter, a level converter and a latch module which are connected in sequence;
the level shifter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube; the source electrode of the first PMOS tube is connected with an external power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube, and the grid electrode of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube; the source electrode of the second PMOS tube is connected with the external power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube; the drain electrode of the third PMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth PMOS tube are connected with the phase inverter, the input signal of the grid electrode of the second NMOS tube and the input signal of the grid electrode of the fourth PMOS tube are the same as the input end signal of the phase inverter, and the input signal of the grid electrode of the third PMOS tube and the input signal of the grid electrode of the first NMOS tube are the same as the output end signal of the phase inverter; the drain electrode of the fourth PMOS tube is connected with the source electrode of the second NMOS tube, the input end of the phase inverter is used as the input end of the level conversion circuit, and the source electrode of the first NMOS tube is used as the output end of the level conversion circuit;
the control end of the latch module receives an external threshold signal, the first end of the latch module is grounded, and the second end of the latch module is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube;
the latch module comprises a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube;
the source electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the third NMOS tube is grounded; the source electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the fourth NMOS tube is grounded; the source electrode of the fifth NMOS tube is respectively connected with the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the drain electrode of the fifth NMOS tube is grounded, and the grid electrode of the fifth NMOS tube receives an external threshold signal.
2. The circuit of claim 1, wherein the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are NMOS transistors of the same type.
3. The level shift circuit of claim 1, wherein the inverter comprises a first CMOS inverter, the gate of the second NMOS transistor and the gate of the fourth PMOS transistor are connected to the input terminal of the first CMOS inverter, and the gate of the third PMOS transistor and the gate of the first NMOS transistor are connected to the output terminal of the first CMOS inverter.
4. The level shift circuit according to claim 1, wherein the inverter comprises a first CMOS inverter and a second CMOS inverter connected in sequence, an input terminal of the first CMOS inverter serves as an input terminal of the inverter, an output terminal of the second CMOS inverter serves as an output terminal of the inverter, a gate of the third PMOS transistor and a gate of the first NMOS transistor are connected to the output terminal of the first CMOS inverter, and a gate of the second NMOS transistor and a gate of the fourth PMOS transistor are connected to the output terminal of the second CMOS inverter.
5. The circuit according to claim 3 or 4, wherein each of the CMOS inverters comprises a fifth PMOS transistor and a sixth NMOS transistor, a source of the fifth PMOS transistor is connected to the external power supply, a gate of the fifth PMOS transistor is connected to a gate of the sixth NMOS transistor and serves as an input terminal of the inverter, a drain of the fifth PMOS transistor is connected to a drain of the sixth NMOS transistor and serves as an output terminal of the inverter, and a source of the sixth NMOS transistor is grounded.
6. The circuit of claim 1, further comprising an external power source outputting a first voltage, wherein the input of the inverter receives an external voltage, wherein the external voltage ranges from 0 to a second voltage, and wherein the first voltage is greater than the second voltage.
7. The level shift circuit according to claim 1, further comprising a buffer unit, wherein the input terminal of the level shift circuit is connected to the level shift circuit through the buffer unit.
8. The circuit of claim 7, wherein the buffer unit comprises two buffer inverters connected in sequence.
9. The level shift circuit of claim 1, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are PMOS transistors of a same type, and the first NMOS transistor and the second NMOS transistor are NMOS transistors of a same type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107659302A (en) * | 2017-08-28 | 2018-02-02 | 天津大学 | Level shifting circuit with pre-amplification |
| CN109756222B (en) * | 2017-11-03 | 2022-12-20 | 展讯通信（上海）有限公司 | Level conversion circuit and chip system |
| CN108540124A (en) * | 2018-04-16 | 2018-09-14 | 电子科技大学 | A kind of level shifting circuit |
| CN113131917B (en) * | 2019-12-31 | 2022-10-21 | 圣邦微电子（北京）股份有限公司 | High-voltage-resistant high-speed level shifter |
| CN112332833B (en) * | 2020-11-16 | 2022-08-26 | 海光信息技术股份有限公司 | Level conversion circuit and CPU chip with same |
| CN113938126B (en) * | 2021-10-25 | 2023-08-01 | 中国电子科技集团公司第五十八研究所 | Voltage latching type level conversion circuit |
| CN115037292B (en) * | 2022-08-09 | 2022-10-28 | 成都市安比科技有限公司 | High-dropout level transfer circuit with enabling detection and power-down protection |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267201A (en) * | 2008-05-14 | 2008-09-17 | 威盛电子股份有限公司 | Level regulator |
| CN101686047A (en) * | 2008-09-24 | 2010-03-31 | 奕力科技股份有限公司 | Level switching circuit |
| CN103856206A (en) * | 2012-12-06 | 2014-06-11 | 上海华虹集成电路有限责任公司 | Low-to-high logic level conversion circuit |
| US9191007B1 (en) * | 2014-06-20 | 2015-11-17 | Freescale Semiconductor, Inc. | Latching level shifter and method of operation |
| US9461648B1 (en) * | 2015-04-10 | 2016-10-04 | SK Hynix Inc. | Power control device |
-
2017
- 2017-02-21 CN CN201710092872.9A patent/CN106899288B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267201A (en) * | 2008-05-14 | 2008-09-17 | 威盛电子股份有限公司 | Level regulator |
| CN101686047A (en) * | 2008-09-24 | 2010-03-31 | 奕力科技股份有限公司 | Level switching circuit |
| CN103856206A (en) * | 2012-12-06 | 2014-06-11 | 上海华虹集成电路有限责任公司 | Low-to-high logic level conversion circuit |
| US9191007B1 (en) * | 2014-06-20 | 2015-11-17 | Freescale Semiconductor, Inc. | Latching level shifter and method of operation |
| US9461648B1 (en) * | 2015-04-10 | 2016-10-04 | SK Hynix Inc. | Power control device |
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| CN106899288A (en) | 2017-06-27 |
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