JP7127103B2 - interface circuit - Google Patents

Description

The present invention relates to interface circuits.

2. Description of the Related Art In a semiconductor device, an interface circuit is used as a circuit that propagates signals between a plurality of circuit blocks with different operating voltages. In particular, an interface circuit used as an input buffer converts the signal level of an externally input signal from the voltage level of the external power supply to the voltage level of the internal power supply and supplies it to the internal circuit. Such an interface circuit is composed of, for example, a plurality of inverter circuits connected in series. The inverter circuit in the first stage inverts the input signal based on the external power supply voltage supplied from the external power supply, and the inverter circuits in the subsequent stages perform signal level conversion and inversion based on the internal power supply voltage.

The internal power supply voltage is generated by, for example, stepping down the voltage level of the external power supply voltage using a voltage conversion circuit or the like. Therefore, the voltage level of the internal power supply voltage is normally lower than the voltage level of the external power supply voltage. However, immediately after turning off the external power supply or when the supply of the external power supply voltage is stopped due to a power failure, etc., a time lag occurs between the drop in the voltage level of the external power supply voltage and the drop in the voltage level of the internal power supply voltage. The external power supply voltage may fall below the internal power supply voltage. In particular, in the voltage conversion circuit described above, a bypass capacitor is added in parallel between the voltage conversion circuit and the internal circuit in order to prevent transient potential fluctuations in the external power supply voltage from propagating directly to the internal power supply voltage. sometimes. In such a configuration, since the change in the internal power supply voltage cannot keep up with the change in the external power supply voltage, the potential of the external power supply voltage tends to transiently fall below the potential of the internal power supply voltage.

Also, the voltage levels of the external power supply voltage and the internal power supply voltage fluctuate due to the influence of noise and the like. In order to avoid the influence of such fluctuations in the voltage level of the power supply voltage on the operation of the interface circuit, a semiconductor device provided with a circuit breaker that cuts off between the interface circuit and the internal circuit when a voltage fluctuation occurs has been conceived. (For example, Patent Document 1). Further, in an inter-block interface circuit that exchanges signals between a plurality of circuit blocks, it has storage means for holding an output signal from one of the circuit blocks. A configuration has been considered in which an inter-block signal control circuit is provided that interrupts signal transmission between the circuit block and storage means and continues to output the signal stored in the storage means (for example, Patent Document 2).

JP-A-4-47597 JP-A-2003-92359

Immediately after turning off the external power supply or when the supply of the external power supply voltage is stopped due to a power failure, etc., the voltage level of the external power supply voltage drops below the voltage level of the internal power supply voltage, and then further drops to the level of the inverter circuit that constitutes the interface circuit. May fall below logical threshold. In such a case, a so-called erroneous determination occurs in which the inverter circuit determines that the signal level of the input signal, which is actually high level, is low level. Therefore, the interface circuit may malfunction.

In order to avoid the influence of such a malfunction on the internal circuit, it is conceivable to add a circuit such as a circuit breaker or an inter-block signal control circuit to the interface circuit, as in Patent Document 1 and Patent Document 2 above. However, these circuits all have problems of large circuit scale and large power consumption.

SUMMARY OF THE INVENTION In order to solve the above-described problems, it is an object of the present invention to provide an interface circuit capable of preventing malfunction due to voltage fluctuation while suppressing circuit scale and power consumption.

An interface circuit according to the present invention is an interface circuit that generates an interface output signal based on an input signal whose signal level changes between a high level and a low level and the signal level at the high level has a potential of a first voltage. operates upon application of the first voltage, outputs a low-level first output signal when the signal level of the input signal is equal to or higher than the logic threshold, and the signal level of the input signal exceeds the above-described logic threshold. a first semiconductor logic gate that outputs the first output signal having the potential of the first voltage when the voltage is less than the logic threshold; and application of a second voltage generated by stepping down the first voltage. and outputs a low-level second output signal when the signal level of the input signal is greater than or equal to the logic threshold, and when the signal level of the input signal is less than the logic threshold. a second semiconductor logic gate that outputs the second output signal having the potential of the second voltage; and a second semiconductor logic gate that operates upon application of the second voltage so that the signal level of the first output signal is a logic threshold. outputting a third output signal of a low level if the signal level of the first output signal is greater than or equal to the logic threshold, and having the potential of the second voltage if the signal level of the first output signal is less than the logic threshold. a third semiconductor logic gate that outputs a signal; and a semiconductor logic gate that operates upon application of the second voltage and receives inputs of the second output signal and the third output signal to produce a fourth output signal and a fifth output signal. and outputting the fourth output signal or the fifth output signal as the interface output signal, wherein the latch circuit is configured such that the first voltage is the logic of the first semiconductor logic gate. generating said fourth output signal having a signal level inverted from said second output signal and said fifth output signal having a signal level inverted from said third output signal in a first state equal to or greater than a threshold value; and, after the first state, when the voltage level of the first voltage decreases and shifts to a second state in which the voltage level is less than the logic threshold value of the first semiconductor logic gate, the gate shifts to the second state. It is characterized by generating the fourth output signal and the fifth output signal that hold the signal level in the first state immediately before.

Further, the interface circuit according to the present invention operates by receiving application of a first voltage, receives an input signal whose signal level changes between the first voltage and a ground potential, and controls the signal level of the input signal. is equal to or greater than the logic threshold, the signal level becomes low, and when the signal level of the input signal is less than the logic threshold, the signal level becomes the potential level of the first voltage. and a second voltage generated by stepping down the first voltage. The logic gate signal is taken in as a first latch signal. a latch circuit that takes in a signal converted into a signal that changes between a second voltage and a ground voltage or the input signal as a second latch signal, and outputs a first interface output signal and a second interface output signal. , the latch circuit outputs a signal having a signal level obtained by inverting the signal level of the first latch signal to the first interface in a first state in which the first voltage is equal to or higher than the logic threshold of the semiconductor logic gate. output as an output signal, output a signal having a signal level obtained by inverting the signal level of the second latch signal as the second interface output signal, and reduce the voltage level of the first voltage to the logic threshold of the first interface output signal and the second interface output signal holding the signal level in the first state immediately before transitioning to the second state when the transition from the first state to the second state is less than It is characterized by outputting at least one of them.

Further, the interface circuit according to the present invention operates upon application of a second voltage generated by stepping down a first voltage, and receives an input signal whose signal level changes between the first voltage and a ground potential. a latch circuit receiving supply of the first voltage and outputting an output signal, wherein the latch circuit receives the input signal in a first state in which the voltage level of the first voltage is higher than a logic threshold; When a signal whose signal level changes in opposite phase is output as the output signal, and the voltage level of the first voltage is lowered to shift from the first state to a second state which is less than the logic threshold, and outputting the output signal holding the signal level in the first state immediately before shifting to the second state.

Further, an interface circuit according to the present invention includes a latch circuit receiving an input signal whose signal level changes between a first voltage and a ground potential and the first voltage, and outputting an output signal. In a first state in which the voltage level of the first voltage is higher than a logic threshold, the circuit outputs as the output signal a signal whose signal level changes in a phase opposite to that of the input signal. When a transition from the first state to a second state in which the voltage level is less than the logic threshold is performed, the output signal holding the signal level in the first state immediately before transitioning to the second state is output. characterized by

According to the present invention, it is possible to prevent malfunction due to voltage fluctuation while suppressing circuit scale and power consumption.

1 is a block diagram showing the configuration of an interface circuit according to the present invention; FIG. It is a truth table showing the operation of the latch circuit. 4 is a time chart showing an example of signal waveforms of signals in a normal operation state; 5 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold of the inverter while the input signal is at low level; 5 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold of the inverter while the input signal is at high level; 4 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold of the inverter and then rises above the logic threshold again; 4 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold of the inverter and then rises above the logic threshold again; FIG. 4 is a block diagram showing an example in which the interface circuit of the present invention is used in a circuit that switches between two types of circuit blocks according to an input signal from the outside; FIG. 4 is a block diagram showing an example of using the interface circuit of the present invention in a circuit for switching between normal mode and test mode; FIG. 11 is a block diagram showing the configuration of an interface circuit of Example 2; 7 is a truth table showing the operation of the latch circuit of Example 2; 4 is a time chart showing an example of signal waveforms of signals in a normal operation state; 5 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold while the input signal is at low level; 5 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold while the input signal is at high level; FIG. 11 is a block diagram showing the configuration of an interface circuit of Example 3; FIG. 11 is a block diagram showing the configuration of an interface circuit of Example 4; 4 is a time chart showing an example of signal waveforms of signals in a normal operation state; 5 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold while the input signal is at low level; 5 is a time chart showing an example of signal waveforms when the voltage level of the external power supply voltage drops below the logic threshold while the input signal is at high level;

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description of each embodiment and the attached drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

FIG. 1 is a block diagram showing the configuration of an interface circuit 10 according to the present invention. The interface circuit 10 receives an input signal IN, and receives an external power supply voltage Vext supplied from an external power supply (not shown) and an internal power supply voltage Vext generated by converting (stepping down) the external power supply voltage Vext using a voltage converter or the like. Output signals OUTA and OUTB are generated based on the power supply voltage Vint and supplied to a subsequent circuit (not shown) as interface output signals. Note that the internal power supply voltage Vint is a voltage generated by stepping down the external power supply voltage Vext, and is smaller than the external power supply voltage Vext (for example, Vext>Vint>1/2Vext) in the normal operation state of the interface circuit 10. ).

The input signal IN is a rectangular wave signal having a ground potential at a low level and a signal level corresponding to the external power supply voltage Vext (first voltage) at a high level. The output signals OUTA and OUTB are rectangular wave signals having a ground potential at low level and a signal level corresponding to the internal power supply voltage Vint (second voltage) at high level.

The interface circuit 10 includes a first inverter 11 , a second inverter 12 , a third inverter 13 and a latch circuit 14 .

The first inverter 11 is composed of a P-channel (first conductivity type) MOS (Metal-Oxide-Semiconductor) transistor MP1 and an N-channel (second conductivity type) MOS transistor MN1 that operate complementarily. (P-channel MOS transistors are hereinafter referred to as "PMOS transistors", and N-channel MOS transistors are referred to as "NMOS transistors"). A drain terminal of the PMOS transistor MP1 is connected to a drain terminal of the NMOS transistor MN1. An external power supply voltage Vext is applied to the source terminal of the PMOS transistor MP1. The source terminal of the NMOS transistor MN1 is grounded and applied with the ground potential Vss. The PMOS transistor MP1 and the NMOS transistor MN1 are composed of high voltage transistors.

The first inverter 11 is a semiconductor logic gate having a logic threshold TH1. Logic threshold TH1 has a value of, for example, half the power supply voltage applied to first inverter 11, that is, half the voltage level of external power supply voltage Vext. The first inverter 11 receives an input signal IN, is at a low level when the signal level of the input signal IN is equal to or higher than the logic threshold TH1, and the signal level of the input signal IN is less than the logic threshold TH1. In this case, the first output signal S1 of high level is output. The first inverter 11 operates upon application of the external power supply voltage Vext and the ground potential Vss as described above. Therefore, the first output signal S1 becomes a rectangular wave having a potential corresponding to the first voltage at high level and a ground potential at low level.

The second inverter 12 is composed of a PMOS transistor MP2 and an NMOS transistor MN2 that operate complementarily. A drain terminal of the PMOS transistor MP2 is connected to a drain terminal of the NMOS transistor MN2. An internal power supply voltage Vint is applied to the source terminal of the PMOS transistor MP2. The source terminal of the NMOS transistor MN2 is grounded and applied with the ground potential Vss. The PMOS transistor MP2 and the NMOS transistor MN2 are composed of high voltage transistors.

The second inverter 12 is a semiconductor logic gate with a logic threshold TH2. Logic threshold TH2 has a value that is, for example, half the power supply voltage applied to second inverter 12, that is, half the voltage level of internal power supply voltage Vint. The second inverter 12 receives an input signal IN, is low level when the signal level of the input signal IN is equal to or higher than the logic threshold TH2, and is lower than the logic threshold TH2. In this case, it outputs the second output signal S2 of high level. The second inverter 12 operates upon application of the internal power supply voltage Vint and the ground potential Vss as described above. Therefore, the second output signal S2 becomes a rectangular wave having a potential corresponding to the second voltage at high level and a ground potential at low level.

The third inverter 13 is composed of a PMOS transistor MP3 and an NMOS transistor MN3 that operate complementarily. A drain terminal of the PMOS transistor MP3 is connected to a drain terminal of the NMOS transistor MN3. An internal power supply voltage Vint is applied to the source terminal of the PMOS transistor MP3. The source terminal of the NMOS transistor MN3 is grounded and applied with the ground potential Vss. The PMOS transistor MP3 and the NMOS transistor MN3 are composed of high voltage transistors.

The third inverter 13 is a semiconductor logic gate having a logic threshold TH3. Logic threshold TH3 has a value that is, for example, half the power supply voltage applied to third inverter 13, that is, half the voltage level of internal power supply voltage Vint. The third inverter 13 receives the input of the first output signal S1, and when the signal level of the first output signal S1 is equal to or higher than the logic threshold TH3, the signal level of the first output signal S1 is logic low. If it is less than the threshold TH3, it outputs a third output signal S3 of high level. The third inverter 13 operates upon application of the internal power supply voltage Vint and the ground potential Vss as described above. Therefore, the third output signal S3 becomes a rectangular wave having a potential corresponding to the second voltage at high level and a ground potential at low level. That is, the third output signal S3 is a signal obtained by converting the input signal IN into a signal whose signal level changes between the second voltage and the ground potential.

The latch circuit 14 is composed of a NAND gate ND1 and a NAND gate ND2. One input terminal of the NAND gate ND1 is connected to the connection terminal of the PMOS transistor MP2 and NMOS transistor MN2 of the second inverter 12 . The other input terminal of NAND gate ND1 is connected to the output terminal of NAND gate ND2. One input terminal of the NAND gate ND2 is connected to the output terminal of the NAND gate ND1. The other input terminal of the NAND gate ND2 is connected to the connection terminal of the PMOS transistor MP3 and the NMOS transistor MN3 of the third inverter 13 . An internal power supply voltage Vint is applied to the NAND gates ND1 and ND2. Each of the NAND gate ND1 and the NAND gate ND2 is composed of, for example, four low-voltage transistors.

The latch circuit 14 receives inputs of the second output signal S2 and the third output signal S3 and generates output signals OUTA and OUTB. That is, the latch circuit 14 takes in the second output signal S2 as a first latch signal, takes in the third output signal S3 as a second latch signal, and converts the output signals OUTA and OUTB into the first interface output signal and the second interface output signal, respectively. Output as an output signal. FIG. 2 is a truth table showing the relationship between the signal levels of the second output signal S2 and the third output signal S3 and the signal levels of the output signals OUTA and OUTB.

The latch circuit 14 outputs a high level when the second output signal S2 is at low level (shown as 'L' in the drawing) and the third output signal S3 is at high level (shown as 'H' in the drawing). A signal OUTA and a low-level output signal OUTB are generated and output as interface output signals. Further, when the second output signal S2 is at high level and the third output signal S3 is at low level, the latch circuit 14 generates a low level output signal OUTA and a high level output signal OUTB, and outputs them as interface output signals. do. That is, when one of the second output signal S2 and the third output signal S3 is at a low level (first state), the latch circuit 14 outputs the output signal OUTA having a signal level obtained by inverting the second output signal S2. and an output signal OUTB having a signal level obtained by inverting the third output signal S3, and output as an interface output signal.

On the other hand, after the first state, when both the second output signal S2 and the third output signal S3 become high level (second state), the latch circuit 14 changes the signal levels of the output signals OUTA and OUTB just before that. and outputs the output signals OUTA and OUTB having the held signal level as interface output signals.

Next, operation of the interface circuit 10 of the present invention will be described with reference to FIGS. 3 to 7. FIG.

FIG. 3 is a diagram showing an example of signal waveforms of the input signal IN, the first output signal S1, the second output signal S2, the third output signal S3, the output signals OUTA and OUTB in the normal operation state of the interface circuit 10. FIG. . As described above, the internal power supply voltage Vint is generated by stepping down the external power supply voltage Vext using a voltage converter or the like, and therefore is lower than the external power supply voltage Vext in the normal operation state.

The input signal IN is a rectangular wave signal having a signal level corresponding to the ground potential at low level and the external power supply voltage Vext (first voltage) at high level. The first output signal S1 becomes a rectangular wave having a signal waveform that is the inverse of the input signal IN. That is, the input signal IN and the first output signal S1 are complementary high level or low level.

The second output signal S2 is a square wave having a signal waveform obtained by changing the signal level of the high level input signal IN to the voltage level of the internal power supply voltage Vint (second voltage) and inverting it. The third output signal S3 becomes a square wave having a signal waveform obtained by changing the high level signal level of the first output signal S1 to the voltage level of the internal power supply voltage Vint and inverting it. That is, the third output signal S3 becomes a signal having the same logic as the input signal IN (high level when the input signal IN is high level, and low level when the input signal IN is low level). Further, the second output signal S2 becomes a signal having a logic opposite to that of the input signal IN (low level when the input signal IN is high level, and high level when the input signal IN is low level).

The output signals OUTA and OUTB have signal waveforms having signal values according to the truth table shown in FIG. That is, when the second output signal S2 is at low level and the third output signal S3 is at high level, the output signal OUTA is at high level and the output signal OUTB is at low level. When the second output signal S2 is at high level and the third output signal S3 is at low level, the output signal OUTA is at low level and the output signal OUTB is at high level. As a result, a signal having the same logic as the input signal IN (high level when the input signal IN is high level, and low level when the input signal IN is low level) is generated as the output signal OUTA. Also, a signal having logic opposite to that of the input signal IN (low level when the input signal IN is high level, and high level when the input signal IN is low level) is generated as the output signal OUTB.

Next, the voltage level of external power supply voltage Vext decreased to fall below all of logic thresholds TH1 to TH3 (hereinafter collectively referred to simply as "logic threshold TH") of each inverter. The operation of the interface circuit 10 in this case will be described. As described above, the external power supply voltage Vext is higher than the internal power supply voltage Vint during normal operation. There is a time difference between the drop of the potential of Vin and the potential of external power supply voltage Vext may drop below the potential of internal power supply voltage Vin and even drop below logic threshold TH. In such a case, the voltage level of the external power supply voltage Vext actually drops gradually to be less than the logic threshold TH. Assuming that the voltage level of Vext is switched below the logic threshold TH, changes in the signal waveform of each signal will be described.

FIG. 4 is a timing chart showing an example of signal waveforms of each signal when the voltage level of the external power supply voltage Vext drops below the logic threshold TH at the timing when the input signal IN is at low level. be. On the other hand, FIG. 5 shows an example of the signal waveform of each signal when the voltage level of the external power supply voltage Vext drops below the logic threshold TH at the timing when the input signal IN is at high level. Chart. In the figure, section T1 (the section on the left side of the dashed line) indicates a section in which the external power supply voltage Vext is equal to or higher than the logic threshold TH, and section T2 (the section on the right side of the dashed line) indicates that the external power supply voltage Vext is logic. A section below the threshold TH is shown.

In section T1, the voltage level of the external power supply voltage Vext is equal to or higher than the logic threshold TH, so that the input signal IN, the first output signal S1, the second output signal S2, the third output signal S3, the output signals OUTA and OUTB are The signal waveform is similar to the signal waveform in the normal operation state shown in FIG.

In interval T2, when the voltage level of external power supply voltage Vext becomes less than logic threshold TH, the signal level of input signal IN becomes less than logic threshold TH even in the high level state. The inverter 11 determines that a high-level input signal IN is supplied when an input signal IN equal to or higher than the logic threshold TH1 is supplied, and determines that an input signal IN of less than the logic threshold TH1 is supplied. It is determined that a low level input signal IN has been supplied. Therefore, during the section T2, the signal level of the input signal IN is less than the logic threshold TH (that is, less than the logic threshold TH1). judge.

The inverter 11 outputs a high level first output signal S1 when the input signal IN is at a low level. Therefore, the first output signal S1 is at high level during the interval T2. However, the signal level in the high level state of the first output signal S1 is equal to the voltage level of the external power supply voltage Vext. Therefore, the signal level of the first output signal S1 is below the logic threshold TH during the interval T2.

The inverter 12 determines that a high-level input signal IN is supplied when an input signal IN equal to or greater than the logic threshold TH2 is supplied, and determines that an input signal IN of less than the logic threshold TH2 is supplied. It is determined that a low level input signal IN has been supplied. As described above, since the signal level of the input signal IN is less than the logic threshold TH (that is, less than the logic threshold TH2) during the period T2, the inverter 12 receives the low-level input signal IN. determine that there is

The inverter 12 outputs a high-level second output signal S2 when the low-level input signal IN is input. Therefore, the signal level of the second output signal S2 is fixed at a high level during the interval T2. The signal level in the high level state of the second output signal S2 is equal to the voltage level of the internal power supply voltage Vint.

The inverter 13 determines that the high-level first output signal S1 is supplied when the first output signal S1 equal to or greater than the logical threshold TH3 is supplied, and the first output signal S1 equal to or less than the logical threshold TH3 is supplied. If supplied, it is determined that the low-level first output signal S1 has been supplied. As described above, the signal level of the first output signal S1 is less than the logic threshold TH (that is, less than the logic threshold TH3) during the interval T2, so the inverter 13 causes the first output signal S1 to be at a low level. is supplied.

The inverter 13 outputs the third output signal S3 of high level when the first output signal S1 of low level is input. Therefore, the signal level of the third output signal S3 is fixed at high level during the interval T2. The signal level in the high level state of the third output signal S3 is equal to the voltage level of the internal power supply voltage Vint.

As described above, both the second output signal S2 and the third output signal S3 are fixed at a high level during the interval T2. As described above, when both the second output signal S2 and the third output signal S3 become high level (second state), the latch circuit 14 selects one of the immediately preceding second output signal S2 and third output signal S3. The state of the signal levels of the output signals OUTA and OUTB in the state where one is at low level (first state) is held, and the output signals OUTA and OUTB having the held signal levels are output as interface output signals.

For example, in FIG. 4, since the output signal OUTA immediately before the transition from section T1 to section T2 is at low level, the signal level is held during section T2, and the low level output signal OUTA is used as the interface output signal. keep outputting. In addition, since the output signal OUTB immediately before the transition from the section T1 to the section T2 is at high level, the signal level is maintained during the section T2, and the high level output signal OUTB is continuously output as the interface output signal.

On the other hand, in FIG. 5, since the output signal OUTA immediately before the transition from section T1 to section T2 is at a high level, the signal level is held during section T2, and the high level output signal OUTA is used as an interface output signal. keep outputting. In addition, since the output signal OUTB immediately before the transition from the section T1 to the section T2 is at low level, the signal level is held during the section T2, and the low level output signal OUTB is continuously output as the interface output signal.

FIG. 6 shows that at the timing when the input signal IN is at the low level as shown in FIG. 5 is a time chart showing an example of signal waveforms of each signal when the level becomes equal to or higher than the logic threshold TH; FIG. 7 shows that at the timing when the input signal IN is at the high level as shown in FIG. 5 is a time chart showing an example of signal waveforms of each signal when the level becomes equal to or higher than the logic threshold TH;

6 and 7, section T3 is a section in which the external power supply voltage Vext again exceeds the logic threshold value TH after section T2 (that is, it exceeds all of the logic threshold values TH1 to TH3). section) is shown. In the section T3, the signal level of the input signal IN becomes equal to or higher than the logic threshold TH at high level. Similarly, the signal level of the first output signal S1 is also higher than the logic threshold TH at high level. Therefore, the second output signal S2 becomes a signal having logic opposite to that of the input signal IN, and the third output signal S3 becomes a signal having the same logic as that of the input signal IN. As a result, in section T3, output signals OUTA and OUTB reflecting the input signal IN are generated and output as interface output signals.

As described above, in the interface circuit 10 of the present invention, when the voltage level of the external power supply voltage Vext falls below the logic threshold TH (TH1 to TH3) of each inverter, the latch circuit 14 detects that the external power supply voltage Vext is The signal levels of the output signals OUTA and OUTB before they drop are held and continue to be output as interface output signals. Therefore, it is possible to prevent the interface circuit from malfunctioning due to an erroneous determination (specifically, determination of a high level signal lower than the logic threshold TH as a low level) in each inverter.

That is, both the second output signal S2 and the third output signal S3 become high level due to the erroneous determination in the inverter 12 and the inverter 13, but the values of the output signals OUTA and OUTB in the previous state are latched. The circuit 14 holds the signal and continues to output it as the interface output signal, so that the input signal IN and the interface output signal can be temporarily separated, and the result of an erroneous determination can be prevented from propagating to the subsequent circuit. .

Further, according to the present invention, in order to prevent malfunction, it is not necessary to separately provide a circuit, such as a cutoff signal generating circuit, which consumes a large circuit area and consumes a large amount of power, in addition to the interface circuit. Therefore, it is possible to prevent malfunction due to a drop in the power supply voltage while suppressing the circuit scale and power consumption.

The interface circuit 10 of the present invention is used, for example, in a circuit that switches between two types of circuit blocks according to an input signal from the outside. As shown in FIG. 8, the interface circuit 10 receives an input signal IN and supplies an output signal OUTA (or OUTB) to the selector SL as an interface output signal. The selector SL switches between the circuit block CA and the circuit block CB depending on whether the output signal OUTA (or OUTB) is at high level or low level. According to the interface circuit 10 of the present invention, even if an erroneous determination of the inverter occurs due to fluctuations in the power supply voltage, the result of the erroneous determination is not propagated to the selector SL. Circuit block switching can be performed.

Further, the interface circuit 10 of the present invention is used in a circuit that switches between normal mode and test mode, for example. As shown in FIG. 9, the interface circuit 10 receives an input signal IN and supplies an output signal OUTA (or OUTB) to the selector SL as an interface output signal. The selector SL switches between the operating signal AS in the normal mode and the test signal TS from the test circuit TC according to whether the output signal OUTA (or OUTB) is at high level or low level, and internally outputs the operating signal AS or the test signal TS. It feeds the circuit NC. According to the interface circuit 10 of the present invention, even if an erroneous determination of the inverter occurs due to fluctuations in the power supply voltage, the result of the erroneous determination is not propagated to the selector SL. It is possible to switch between normal mode and test mode.

In addition, in the present invention, two signal lines, a first signal line connecting the inverter 12 and the NAND gate ND1 and a second signal line connecting the inverter 11, the inverter 13 and the NAND gate ND2, provide a complementary signal line. transmitting a signal. Therefore, when a signal is transmitted through a single signal line, only two types of output values, ie, 'H' and 'L', can be obtained. ('H' and 'H', 'H' and 'L', 'L' and 'H', 'L' and 'L') can be obtained. Then, by using a combination of output values ('H' and 'H') different from the combination of output values ('H' and 'L', 'L' and 'H') obtained during normal operation, By holding the value, it is possible to transmit and output the input signal as intended even in a situation where an erroneous determination of the inverter may occur due to fluctuations in the power supply voltage.

FIG. 10 is a block diagram showing the configuration of the interface circuit 20 according to the second embodiment. Similar to the interface circuit 10 of the first embodiment, the interface circuit 20 receives the input signal IN, generates the output signals OUTA and OUTB based on the external power supply voltage Vext and the internal power supply voltage Vint, and outputs them as interface output signals. feed the circuit. Interface circuit 20 includes inverter 21 and latch circuit 24 .

Inverter 21 is a semiconductor logic gate having a logic threshold TH4 which is half the voltage level of external power supply voltage Vext, and when the signal level of input signal IN is equal to or higher than logic threshold TH4. is low level, and outputs a logic gate signal LS which is high level when the signal level of the input signal IN is less than the logic threshold TH4. Since the inverter 21 operates upon application of the external power supply voltage Vext and the ground potential Vss, the logic gate signal LS has a potential corresponding to the external power supply voltage Vext (first voltage) at high level and the ground potential at low level. It becomes a square wave with

The latch circuit 24 is composed of a NOR gate NR1 and a NOR gate NR2. The latch circuit 24 takes in the logic gate signal LS and the input signal IN as a first latch signal and a second latch signal, and outputs output signals OUTA and OUTB.

The NOR gate NR1 is composed of a PMOS transistor MP4, a PMOS transistor MP5, an NMOS transistor MN4 and an NMOS transistor MN5. The PMOS transistor MP4 and the NMOS transistor MN4 are composed of high voltage transistors. On the other hand, the PMOS transistor MP5 and the NMOS transistor MN5 are composed of low-voltage transistors.

An internal power supply voltage Vint is applied to the source terminal of the PMOS transistor MP4. The drain terminal of the PMOS transistor MP4 is connected to the source terminal of the PMOS transistor MP5. The drain terminal of the PMOS transistor MP5 is connected to the drain terminals of the NMOS transistors MN4 and MN5. The source terminals of the NMOS transistor MN4 and the NMOS transistor MN5 are grounded and applied with the ground potential Vss. A gate terminal of the PMOS transistor MP4 and a gate terminal of the NMOS transistor MN4 are connected to each other and receive an input signal IN. Gate terminals of the PMOS transistor MP5 and the NMOS transistor MN5 are connected to each other and receive the output signal OUTA from the NOR gate NR2.

The NOR gate NR2 is composed of a PMOS transistor MP6, a PMOS transistor MP7, an NMOS transistor MN6 and an NMOS transistor MN7. The PMOS transistor MP6 and the NMOS transistor MN6 are composed of high voltage transistors. On the other hand, the PMOS transistor MP7 and the NMOS transistor MN7 are composed of low withstand voltage transistors.

An internal power supply voltage Vint is applied to the source terminal of the PMOS transistor MP6. The drain terminal of the PMOS transistor MP6 is connected to the source terminal of the PMOS transistor MP7. The drain terminal of the PMOS transistor MP7 is connected to the drain terminals of the NMOS transistors MN6 and MN7. The source terminals of the NMOS transistor MN6 and the NMOS transistor MN7 are grounded and applied with the ground potential Vss. The gate terminal of the PMOS transistor MP6 and the gate terminal of the NMOS transistor MN6 are connected to each other and receive the input of the logic gate signal LS from the inverter 21 . Gate terminals of the PMOS transistor MP7 and the NMOS transistor MN7 are connected to each other and receive the output signal OUTB from the NOR gate NR1.

Latch circuit 24 is a semiconductor logic gate having a logic threshold (latch threshold) TH5. Logic threshold TH5 has a value that is half the voltage level of internal power supply voltage Vint applied to NOR gates NR1 and NR2. The latch circuit 24 receives the input signal IN and the logic gate signal LS and generates output signals OUTA and OUTB.

FIG. 11 is a truth table showing the relationship between the signal levels of the input signal IN and the logic gate signal LS and the signal levels of the output signals OUTA and OUTB. Output signals OUTA and OUTB having signal levels shown in the truth table according to whether the signal levels of the input signal IN and the logic gate signal LS are higher (high level) or lower (low level) than the logic threshold TH5. to generate

The latch circuit 24 outputs a low level output signal OUTA when the input signal IN is at low level (shown as 'L' in the figure) and the logic gate signal LS is at high level (shown as 'H' in the figure). and outputs a high level output signal OUTB. On the other hand, when the input signal IN is at high level and the logic gate signal LS is at low level, it outputs the output signal OUTA at high level and the output signal OUTB at low level. When the input signal IN is at low level and the logic gate signal LS is at low level, the state of the signal levels of the output signals OUTA and OUTB immediately before that is held, and the output signals OUTA and OUTB having the held signal levels are output. Output as an interface output signal.

Next, operation of the interface circuit 20 of the present invention will be described with reference to FIGS. 12 to 14. FIG.

FIG. 12 is a diagram showing an example of signal waveforms of the input signal IN, the logic gate signal LS, and the output signals OUTA and OUTB when the interface circuit 20 normally operates (that is, when the external power supply voltage Vext does not drop). be.

When the input signal IN is high level (Vext level), the inverter 21 outputs a low level logic gate signal LS. The latch circuit 24 receives a high-level input signal IN and a low-level logic gate signal LS, and outputs a high-level (Vint level) output signal OUTA and a low-level output signal OUTB.

On the other hand, when the input signal IN is at low level, the inverter 21 outputs the logic gate signal LS at high level (Vext level). The latch circuit 24 receives a low-level input signal IN and a high-level logic gate signal LS, and outputs a low-level output signal OUTA and a high-level (Vint level) output signal OUTB.

Next, the voltage level of external power supply voltage Vext decreases to fall below logic threshold TH4 of inverter 21 and logic threshold TH5 of latch circuit 24 (hereinafter collectively referred to as logic threshold TH). The operation of the interface circuit 20 in this case will be described.

FIG. 13 shows an example of the signal waveform of each signal when the voltage level of the external power supply voltage Vext drops below the logic thresholds TH4 and TH5 at the timing when the input signal IN is at low level. Chart.

On the other hand, FIG. 14 shows an example of signal waveforms when the voltage level of the external power supply voltage Vext drops below the logic thresholds TH4 and TH5 at the timing when the input signal IN is at high level. It is a time chart.

When the voltage level of the external power supply voltage Vext falls below the logic threshold TH (TH4 and TH5) (section T2 in the drawing), the signal level of the input signal IN is lower than the logic threshold TH even in the high level state. Become. The inverter 21 determines that the low-level input signal IN is input, and outputs a high-level logic gate signal LS. However, since the signal level of logic gate signal LS is equal to the voltage level of external power supply voltage Vext, it is less than logic threshold TH.

An input signal IN and a logic gate signal LS having a signal level less than the logic threshold TH are input to the latch circuit 24 . Therefore, the latch circuit 24 determines that the low-level input signal IN and the logic gate signal LS are input, and holds the signal levels of the output signals OUTA and OUTB at the previous levels.

After that, when the voltage level of the external power supply voltage Vext exceeds the logic threshold TH (TH4 and TH5) again (section T3 in the figure), the interface circuit 20 returns to normal operation, and the latch circuit 24 returns to the state shown in FIG. It outputs output signals OUTA and OUTB according to the truth table.

As described above, in the interface circuit 20 of the present embodiment, when the voltage level of the external power supply voltage Vext drops below the logic threshold TH, the latch circuit 24 detects the voltage level before the voltage level of the external power supply voltage Vext drops. The signal levels of the output signals OUTA and OUTB are held and continue to be output as interface output signals. Therefore, it is possible to prevent malfunction of the circuit due to voltage fluctuation.

Further, the interface circuit 20 of this embodiment is composed of one inverter (21) and one latch circuit (24), and six high voltage transistors (MP1, MN1, MP4, MN4, MP6 and MN6). and four low voltage transistors (MP5, MN5, MP7 and MN7). On the other hand, the interface circuit 10 of the first embodiment is therefore composed of three inverters (11, 12, 13) and one latch circuit (14). It includes a transistor and eight low-voltage transistors forming a latch circuit. Therefore, the interface circuit 20 of this embodiment is smaller in circuit scale than the interface circuit 10 of the first embodiment.

Also, the interface circuit 20 of this embodiment includes a total of three gates, an inverter 21, a NOR gate NR1 and a NOR gate NR2. Therefore, the number of gates is smaller than that of the interface circuit 10 of the first embodiment, which includes a total of five gates, ie, the first inverter 11, the second inverter 12, the third inverter 13, the NAND gate ND1 and the NAND gate ND2. Therefore, power consumption (operating power, standby power) can be suppressed.

In addition, in the interface circuit 20 of the present embodiment, the number of gate stages that the input signal IN passes through before it is output as the output signals OUTA and OUTB is at most three. The time (delay time) from the input of the input signal IN to the output of the output signals OUTA and OUTB is shorter than that of the interface circuit of the first embodiment.

FIG. 15 is a block diagram showing the configuration of the interface circuit 30 according to the third embodiment. As with the interface circuit 10 of the first embodiment and the interface circuit 20 of the second embodiment, the interface circuit 30 receives an input signal IN and generates output signals OUTA and OUTB based on the external power supply voltage Vext and the internal power supply voltage Vint. and supplied to the subsequent circuit as an interface output signal.

Interface circuit 30 includes inverter 21 and latch circuit 34 . The latch circuit 34 is composed of a NOR gate NR3 and a NOR gate NR4.

The NOR gate NR3 is composed of a PMOS transistor MP4, a PMOS transistor MP5, an NMOS transistor MN4 and an NMOS transistor MN5. The PMOS transistor MP4 and the NMOS transistor MN4 are composed of high voltage transistors. On the other hand, the PMOS transistor MP5 and the NMOS transistor MN5 are composed of low-voltage transistors.

An internal power supply voltage Vint is applied to the source terminal of the PMOS transistor MP5. A drain terminal of the PMOS transistor MP5 is connected to a source terminal of the PMOS transistor MP4. The drain terminal of the PMOS transistor MP4 is connected to the drain terminals of the NMOS transistors MN4 and MN5. The source terminals of the NMOS transistor MN4 and the NMOS transistor MN5 are grounded and applied with the ground potential Vss. A gate terminal of the PMOS transistor MP4 and a gate terminal of the NMOS transistor MN4 are connected to each other and receive an input signal IN. Gate terminals of the PMOS transistor MP5 and the NMOS transistor MN5 are connected to each other and receive the output signal OUTA from the NOR gate NR4.

The NOR gate NR4 is composed of a PMOS transistor MP6, a PMOS transistor MP7, an NMOS transistor MN6 and an NMOS transistor MN7. The PMOS transistor MP6 and the NMOS transistor MN6 are composed of high voltage transistors. On the other hand, the PMOS transistor MP7 and the NMOS transistor MN7 are composed of low withstand voltage transistors.

An internal power supply voltage Vint is applied to the source terminal of the PMOS transistor MP7. The drain terminal of the PMOS transistor MP7 is connected to the source terminal of the PMOS transistor MP6. The drain terminal of the PMOS transistor MP6 is connected to the drain terminals of the NMOS transistors MN6 and MN7. The source terminals of the NMOS transistor MN6 and the NMOS transistor MN7 are grounded and applied with the ground potential Vss. The gate terminal of the PMOS transistor MP6 and the gate terminal of the NMOS transistor MN6 are connected to each other and receive the input of the logic gate signal LS from the inverter 21 . Gate terminals of the PMOS transistor MP7 and the NMOS transistor MN7 are connected to each other and receive the output signal OUTB from the NOR gate NR3.

Latch circuit 34 is a semiconductor logic gate having a logic threshold (latch threshold) TH5. In the latch circuit 34 of this embodiment, the internal power supply voltage Vint is applied to the source terminals of the PMOS transistor MP5 and the PMOS transistor MP7, which are low-voltage transistors, and the PMOS transistor MP4 and the PMOS transistor MP6, which are high-voltage transistors, are applied with an output voltage. It differs from the latch circuit 24 of the second embodiment in that it is connected to the output lines (OUTA and OUTB).

However, the latch circuit 34 outputs the output signals OUTA and OUTB according to the truth table of FIG. 11, like the latch circuit 24 of the second embodiment. That is, the latch circuit 34 outputs a low-level output signal OUTA and a high-level output signal OUTB when the input signal IN is at low level and the logic gate signal LS is at high level. On the other hand, when the input signal IN is at high level and the logic gate signal LS is at low level, it outputs the output signal OUTA at high level and the output signal OUTB at low level. When the input signal IN is at low level and the logic gate signal LS is at low level, the state of the signal levels of the output signals OUTA and OUTB immediately before that is held, and the output signals OUTA and OUTB having the held signal levels are output. Output as an interface output signal.

Also, the latch circuit 34 is a semiconductor logic gate having a logic threshold (latch threshold) TH5, like the latch circuit 24 of the second embodiment. Therefore, the latch circuit 34 is similar to the latch circuit 24 of the second embodiment in both the state in which the interface circuit 20 normally operates and the state in which the voltage level of the external power supply voltage Vext drops below the logic threshold TH. take action. That is, in the interface circuit 30 of the present embodiment, when the voltage level of the external power supply voltage Vext drops below the logic threshold TH, the latch circuit 34 outputs the output signal OUTA before the voltage level of the external power supply voltage Vext drops. and OUTB are held and output as interface output signals.

Therefore, according to the interface circuit 30 of the present embodiment, it is possible to prevent circuit malfunction due to voltage fluctuation.

FIG. 16 is a block diagram showing the configuration of the interface circuit 40 according to the fourth embodiment. The interface circuit 40 receives an input signal IN and an external power supply voltage Vext, generates an output signal OUTB based on the external power supply voltage Vext and the internal power supply voltage Vint, and supplies it as an interface output signal to a subsequent circuit. The interface circuit 40 has no inverter, the external power supply voltage Vext is supplied to the latch circuit 24 in addition to the input signal IN, and the output signal OUTA is not output to the subsequent circuit (outside the interface circuit 40). This is different from the interface circuit 20 of the second embodiment.

The interface circuit 40 includes a latch circuit 24 composed of a NOR gate NR1 and a NOR gate NR2, like the interface circuit 20 of the second embodiment. However, unlike the second embodiment, the external power supply voltage Vext is applied to the gate terminals of the PMOS transistor MP6 and the NMOS transistor MN6 forming the NOR gate NR2.

Next, the operation of the interface circuit 40 of the present invention will be described with reference to FIGS. 17-19.

FIG. 17 is a diagram showing an example of signal waveforms of the input signal IN, the external power supply voltage Vext, and the output signals OUTA and OUTB when the interface circuit 40 normally operates (that is, the external power supply voltage Vext does not drop). be.

During normal operation of interface circuit 40, external power supply voltage Vext takes a constant voltage value (Vext level). Therefore, the output signal OUTA is always at low level (Vss level). On the other hand, the output signal OUTB is a signal whose signal level changes in a phase opposite to that of the input signal IN (a signal having opposite logic). That is, the output signal OUTB is low level (Vss level) when the input signal IN is high level (Vext level), and is high level (Vint level) when the input signal IN is low level (Vss level). becomes.

Next, the operation of interface circuit 40 when the voltage level of external power supply voltage Vext drops below logic threshold TH5 of latch circuit 24 will be described.

FIG. 18 is a time chart showing an example of signal waveforms of each signal when the voltage level of the external power supply voltage Vext drops below the logic threshold TH5 at the timing when the input signal IN is at low level. be.

When the voltage level of the external power supply voltage Vext falls below the logic threshold TH5 (section T2 in the figure), the signal level of the input signal IN is below the logic threshold TH even if it becomes high level after that.

The latch circuit 24 is supplied with an input signal IN having a signal level lower than the logic threshold TH5 and an external power supply voltage Vext. Therefore, the latch circuit 24 determines that the low-level input signal IN and the external power supply voltage Vext have been supplied, and holds the signal levels of the output signals OUTA and OUTB at the previous levels. That is, the output signal OUTA becomes low level, and the output signal OUTB becomes high level.

After that, when the voltage level of external power supply voltage Vext exceeds logic threshold TH5 again (section T3 in the drawing), interface circuit 40 returns to normal operation. That is, the output signal OUTA maintains a low level, and the output signal OUTB becomes a signal whose signal level changes in a phase opposite to that of the input signal IN (a signal having opposite logic).

FIG. 19 is a time chart showing an example of signal waveforms of each signal when the voltage level of the external power supply voltage Vext drops below the logic threshold TH5 at the timing when the input signal IN is at high level. be.

When the voltage level of external power supply voltage Vext falls below logic threshold TH5 (section T2 in the figure), the signal level of input signal IN is below logic threshold TH even in the high level state.

The latch circuit 24 is supplied with an input signal IN having a signal level lower than the logic threshold TH5 and an external power supply voltage Vext. Therefore, the latch circuit 24 determines that the low-level input signal IN and the external power supply voltage Vext have been supplied, and holds the signal levels of the output signals OUTA and OUTB at the previous levels. That is, both the output signal OUTA and the output signal OUTB are at low level.

After that, when the voltage level of external power supply voltage Vext exceeds logic threshold TH5 again (section T3 in the drawing), interface circuit 40 returns to normal operation. That is, the output signal OUTA maintains a low level, and the output signal OUTB becomes a signal whose signal level changes in a phase opposite to that of the input signal IN (a signal having opposite logic).

As described above, according to the interface circuit 40 of the present embodiment, even when the voltage level of the external power supply voltage Vext drops below the logic threshold TH5, the level of the external power supply voltage Vext before the drop falls. The signal level of the output signal OUTB is held and continues to be output as the interface output signal. Therefore, it is possible to prevent malfunction of the circuit due to voltage fluctuation.

Further, unlike the interface circuits (20, 30) of the second and third embodiments, the interface circuit 40 of this embodiment does not include the inverter 21. FIG. Therefore, the interface circuit 40 is composed of four high voltage transistors (MP4, MN4, MP6 and MN6) and four low voltage transistors (MP5, MN5, MP7 and MN7). Therefore, compared with the interface circuit 20 of the second embodiment and the interface circuit 30 of the third embodiment, the circuit scale can be further reduced.

Further, the interface circuit 40 of this embodiment includes a total of two gates, the NOR gate NR1 and the NOR gate NR2. Therefore, the number of gates is smaller than that of the interface circuits of Examples 2 and 3, which include a total of three gates: inverter 21, NOR gates NR1 and NOR gates NR2 (or NOR gates NR3 and NOR gates NR4). Therefore, power consumption (operating power, standby power) can be further reduced.

In addition, in the interface circuit 40 of the present embodiment, since the number of stages of gates through which a signal passes from the input of the input signal IN to the output of the output signal OUTB is two at maximum, the number of stages of gates to pass through is the maximum. The time (delay time) from the input of the input signal IN to the output of the output signal OUTB can be further reduced compared to the three-stage interface circuits of the second and third embodiments.

In addition, this invention is not limited to the said embodiment. For example, in the above embodiments, the internal power supply voltage Vint is a voltage generated by converting the external power supply voltage Vext using a voltage converter or the like. However, it is not limited to this, and may be generated independently of the external potential Vext. That is, the first voltage applied to the logic gate on the input side to which the input signal IN is input and the second voltage applied to the subsequent logic gate have independent voltage values, and the voltage level of the first voltage is can be lower than the voltage level of the cut-off or second voltage.

Further, in the above embodiment, an example has been described in which the external power supply voltage Vext is higher than the internal power supply voltage Vint during normal operation. However, the external power supply voltage Vext and the internal power supply voltage Vint may be substantially the same potential during normal operation.

In addition, in the first embodiment, an example in which high voltage transistors are used as the transistors constituting the first inverter 11, the second inverter 12, and the third inverter 13 has been described. However, the breakdown voltage of the transistor that configures each inverter is not limited to this. The transistors forming each inverter may have a breakdown voltage that can withstand at least the external power supply voltage Vext (first voltage) and the internal power supply voltage Vint (second voltage).

Further, in the first embodiment, an example has been described in which the first to third inverters (11 to 13) are composed of high-voltage transistors, and the NAND gates ND1 and ND2 are composed of low-voltage transistors. Further, in the second to fourth embodiments, examples have been described in which the NOR gates NR1 to NR4 are configured by a combination of high-voltage transistors and low-voltage transistors. However, all the transistors may be composed of transistors with the same breakdown voltage. That is, the interface circuit of the present invention may be configured using transistors with the same breakdown voltage, or may be configured by combining transistors with different breakdown voltages.

Further, in the above embodiment, the logic threshold of each inverter and latch circuit is 1/2 times the voltage level of the power supply voltage applied to each inverter and latch circuit (that is, logic thresholds TH1 and TH4). is 1/2 times Vext and logic thresholds TH2, TH3 and TH5 are 1/2 times Vint). However, the logic threshold value of each inverter and latch circuit is not limited to this. Also, the logic thresholds of the first inverter 11, the second inverter 12, and the third inverter 13 may be different from each other, or may be the same value. Similarly, the logic thresholds of the inverter 21 and the latch circuit 24 (34) may be different or may be the same. The logic thresholds of the first inverter 11, the second inverter 12, the third inverter 13, the inverter 21, the latch circuits 24 and 34 are at least lower than the voltage level of the power supply voltage applied to each inverter and latch circuit. I wish I had.

Also, in the above embodiment, an example in which the latch circuit 14 is composed of the NAND gate ND1 and the NAND gate ND2 has been described. However, the configuration of the latch circuit 14 is not limited to this, and the latch circuit 14 may be configured using, for example, a NOR gate or the like.

Also, the truth table for the operation of each latch circuit is not limited to those shown in FIGS. For example, in the truth table of FIG. 2, when the second output signal S2 is 'L' and the third output signal S3 is 'H', the output signal OUTA is 'H' and the output signal OUTB is 'L'. When the second output signal S2 is 'H' and the third output signal S3 is 'L', the output signal OUTA is 'L' and the output signal OUTB is 'H'. However, unlike this, when the second output signal S2 is 'L' and the third output signal S3 is 'H', the output signal OUTA is 'L' and the output signal OUTB is 'H'. The latch circuit 14 may be configured so that the output signal OUTA is 'H' and the output signal OUTB is 'L' when the output signal S2 is 'H' and the third output signal S3 is 'L'. .

In the above embodiment, the latch circuit 14 generates the output signals OUTA and OUTB and outputs them as interface output signals. However, the latch circuit 14 may supply at least one of OUTA and OUTB as an interface output signal to the subsequent circuit.

Further, the interface circuit 40 of the fourth embodiment is not limited to the case where the voltage level of the external power supply voltage Vext and the signal level of the input signal IN are lowered at the same time. It is applicable even when it occurs before the signal level drop of the input signal IN. For example, when the input signal IN is at the high level, the voltage level of the external power supply voltage Vext drops below the logic threshold TH5, and then the signal level of the input signal IN drops below the logic threshold TH5. , the signal level of the output signal OUTB is held at a low level. Therefore, the change in the signal level of the output signal OUTB is the same as when the voltage level of the external power supply voltage Vext and the signal level of the input signal IN decrease simultaneously.

Further, the interface circuits 10, 20, and 30 of the first to third embodiments described above are not limited to the case where the voltage level of the external power supply voltage Vext and the signal level of the input signal IN are lowered at the same time. When the voltage level of Vext occurs before the signal level of the input signal IN decreases, or when the voltage level of the external power supply voltage Vext decreases after the signal level of the input signal IN decreases (that is, when the input signal IN The case where the signal level of the signal IN drops before the voltage level of the external power supply voltage Vext drops). For example, when the level of the external power supply voltage Vext and the level of the input signal IN drop below the logic threshold at the timing when the input signal IN is at high level, the output signal OUTA is at high level and the output signal OUTB is at low level. The signal level is held in the state of Similarly, when the levels of the external power supply voltage Vext and the input signal IN drop below the logic threshold at the timing when the input signal IN is at low level, the output signal OUTA is at low level and the output signal OUTB is at high level. The signal level is held in the state of Therefore, the changes in the signal levels of the output signal OUTA and the output signal OUTB are the same as when the voltage level of the external power supply voltage Vext and the signal level of the input signal IN decrease at the same time.

In short, the interface circuit (10) according to the present invention receives a first voltage (Vext) and a second voltage (Vint) and generates an interface output signal (OUTA or OUTB) based on the input signal (IN). . A first semiconductor logic gate (11) is supplied with a first voltage (Vext) and has a low level first output signal when the signal level of the input signal (IN) is equal to or higher than a logic threshold (TH1). (S1), and when the signal level of the input signal (IN) is less than the logic threshold value (TH1), a high-level first output signal (S1) corresponding to the first voltage (Vext) is output. do. A second semiconductor logic gate (12) is supplied with a second voltage (Vint) and has a low level second output signal when the signal level of the input signal (IN) is equal to or higher than the logic threshold (TH2). (S2), and when the signal level of the input signal (IN) is less than the logic threshold value (TH2), a high-level second output signal (S2) corresponding to the second voltage (Vint) is output. do. A third semiconductor logic gate (13) is supplied with a second voltage (Vint) and is at a low level when the signal level of the first output signal (S1) is equal to or higher than a logic threshold (TH3). An output signal (S3) is output, and when the signal level of the first output signal (S1) is less than the logic threshold (TH3), a high level third output signal (S3) corresponding to the second voltage (Vint) S3) is output. A latch circuit (14) receives inputs of the second output signal (S2) and the third output signal (S3) to generate a fourth output signal (OUTA) and a fifth output signal (OUTB), and an interface output signal. output as In a first state in which one of the second output signal (S2) and the third output signal (S3) is at low level, the latch circuit (14) outputs a signal level obtained by inverting the second output signal (S2). and a fifth output signal (S5) having a signal level that is the inverse of the third output signal (S3), and after the first state, the second output signal (S2) and the third output signal (S3) are both at high level, the fourth output signal (S4) and the fifth output hold the signal level in the first state immediately before the transition to the second state. It is characterized by generating a signal (S5).

Further, the interface circuit (10, 20, 30) according to the present invention receives an input signal (IN) whose signal level changes between the first voltage (Vext) and the ground potential (Vss), and receives the input signal (IN). When the signal level of (IN) is equal to or higher than the logic thresholds (TH2, TH4), the signal level is low, and the signal level of the input signal (IN) is less than the logic thresholds (TH2, TH4). A semiconductor logic gate (12, 21) for outputting a logic gate signal (S2, LS) whose signal level is high when the signal level is high, and a logic gate signal (S2, LS) are taken in as a first latch signal, while an input signal (IN) converted into a signal whose signal level changes between the second voltage (Vint) and the ground voltage (Vss), or the input signal (IN) is taken as a second latch signal, and the first a latch circuit (14, 24, 34) for outputting an interface output signal (OUTA) and a second interface output signal (OUTB). The latch circuit (14, 24, 34) receives the first latch signal (S2 , LS) is outputted as the first interface output signal (OUTA), and a signal having the signal level inverted from the second latch signal is outputted as the second interface output signal (OUTA). (OUTB). The latch circuit (14, 24, 34) has transitioned from the first state to the second state in which both the first latch signal (S2, LS) and the second latch signal (S3, IN) are both at low level or at high level. In this case, at least one of the first interface output signal (OUTA) and the second interface output signal (OUTB), which hold the signal level in the first state immediately before shifting to the second state, is output. be.

10, 20, 30, 40 interface circuit 11 first inverter 12 second inverter 13 third inverter 14, 24, 34 latch circuit 21 inverters MP1 to MP7 PMOS transistors MN1 to MN7 NMOS transistors ND1 and ND2 NAND gates NR1 to NR4 NOR gates

Claims (12)

An interface circuit for generating an interface output signal based on an input signal whose signal level changes between a high level and a low level and the signal level at the high level has a potential of a first voltage,
operates upon application of the first voltage, outputs a low-level first output signal when the signal level of the input signal is equal to or higher than a logic threshold, and outputs a low-level first output signal when the signal level of the input signal is above the logic threshold; a first semiconductor logic gate that outputs said first output signal having a potential of said first voltage when below a threshold;
receives the application of a second voltage generated by stepping down the first voltage, and outputs a low-level second output signal when the signal level of the input signal is equal to or higher than a logic threshold; a second semiconductor logic gate that outputs the second output signal having the potential of the second voltage when the signal level of the input signal is less than the logic threshold;
operates upon application of the second voltage, outputs a low-level third output signal when the signal level of the first output signal is equal to or higher than a logic threshold, and outputs the signal level of the first output signal; a third semiconductor logic gate outputting said third output signal having a potential of said second voltage when is less than said logic threshold;
receives the second voltage, receives the second output signal and the third output signal, generates a fourth output signal and a fifth output signal, and receives the fourth output signal or the third output signal. 5 a latch circuit that outputs the output signal as the interface output signal;
including
The latch circuit is
In a first state in which the first voltage is equal to or higher than the logic threshold of the first semiconductor logic gate, the fourth output signal and the third output signal having signal levels inverted from the second output signal are generated. generating said fifth output signal having an inverted signal level;
After the first state, when the voltage level of the first voltage decreases and transitions to a second state that is less than the logic threshold of the first semiconductor logic gate, the voltage level immediately before transitioning to the second state. generating the fourth output signal and the fifth output signal that retain the signal level in the first state;
An interface circuit characterized by: 2. The interface circuit according to claim 1, wherein said input signal has a ground potential at a low signal level. the first semiconductor logic gate outputs the first output signal having a ground potential at a low level;
the second semiconductor logic gate outputs the second output signal having a ground potential at a low level;
the third semiconductor logic gate outputs the third output signal having a ground potential at a low level;
3. An interface circuit according to claim 1 or 2, characterized in that: The first voltage is an external power supply voltage supplied from the outside,
The second voltage is a voltage obtained by converting the first voltage by a voltage conversion circuit.
4. The interface circuit according to any one of claims 1 to 3, characterized in that: the first semiconductor logic gate includes a first transistor of a first conductivity type with drain terminals connected together and a second transistor of a second conductivity type opposite to the first conductivity type;
the second semiconductor logic gate includes the third transistor of the first conductivity type and the fourth transistor of the second conductivity type, the drain terminals of which are connected to each other;
the third semiconductor logic gate includes the fifth transistor of the first conductivity type and the sixth transistor of the second conductivity type, the drain terminals of which are connected to each other;
The first transistor has a source terminal to which the first voltage is applied,
the second transistor has a source terminal grounded,
The third transistor has a source terminal to which the second voltage is applied,
the fourth transistor has a source terminal grounded,
The fifth transistor has a source terminal to which the second voltage is applied,
the sixth transistor has a source terminal grounded;
5. The interface circuit according to any one of claims 1 to 4, characterized in that: 6. The interface circuit according to claim 1, wherein said latch circuit includes a first NAND circuit and a second NAND circuit. The logic threshold of the first semiconductor logic gate, the logic threshold of the second semiconductor logic gate, and the logic threshold of the third semiconductor logic gate are equal to each other. 7. An interface circuit according to any one of claims 1-6. operates upon application of a first voltage, receives an input signal whose signal level changes between the first voltage and a ground potential, and receives an input signal whose signal level is equal to or higher than a logic threshold; a semiconductor logic gate for outputting a logic gate signal whose signal level becomes low level and whose signal level becomes the potential level of the first voltage when the signal level of the input signal is less than the logic threshold;
The first interface receives the second voltage generated by stepping down the first voltage for operation, takes in the logic gate signal as a first latch signal, takes in the input signal as a second latch signal, and operates as a first interface. a latch circuit that outputs an output signal and a second interface output signal;
including
the latch circuit includes a first NOR circuit and a second NOR circuit each operating upon application of the second voltage;
In a first state in which the first voltage is equal to or higher than the logic threshold of the semiconductor logic gate, a signal having a signal level obtained by inverting the logic gate signal is output as the first interface output signal, and the input signal is output as the first interface output signal. outputting a signal having an inverted signal level as the second interface output signal;
When the voltage level of the first voltage decreases and transitions from the first state to a second state in which the voltage level is less than the logic threshold, the signal level in the first state immediately before transitioning to the second state is held. outputting at least one of the first interface output signal and the second interface output signal;
An interface circuit characterized by: The first NOR circuit includes a first conductivity type first transistor having a source terminal to which the second voltage is applied;
a second transistor of a second conductivity type opposite to the first conductivity type, the source terminal of which is grounded and the gate terminal of which receives the input signal;
a third transistor of the first conductivity type having a source terminal connected to the drain terminal of the first transistor;
a fourth transistor of the second conductivity type having a source terminal grounded, a drain terminal connected to the drain terminal of the third transistor, and a gate terminal receiving the first interface output signal;
including
The second NOR circuit includes a first conductivity type fifth transistor having a source terminal to which the second voltage is applied;
a sixth transistor of the second conductivity type whose source terminal is grounded and whose gate terminal receives the input of the logic gate signal;
a seventh transistor of the first conductivity type having a source terminal connected to the drain terminal of the fifth transistor;
an eighth transistor of the second conductivity type having a source terminal grounded, a drain terminal connected to the drain terminal of the seventh transistor, and a gate terminal receiving the second interface output signal;
9. The interface circuit of claim 8 , comprising: the first transistor, the second transistor, the fifth transistor, and the sixth transistor are high voltage transistors;
the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are low-voltage transistors;
the first transistor receives the input signal at its gate terminal;
the third transistor receives the input of the first interface output signal at its gate terminal;
the fifth transistor receives the input of the logic gate signal at its gate terminal;
10. The interface circuit of claim 9 , wherein the seventh transistor receives the second interface output signal at its gate terminal. the first transistor, the fourth transistor, the fifth transistor, and the eighth transistor are low-voltage transistors;
the second transistor, the third transistor, the sixth transistor, and the seventh transistor are high voltage transistors;
the first transistor receives the input of the first interface output signal at its gate terminal;
the third transistor receives the input signal at its gate terminal;
the fifth transistor receives the second interface output signal at its gate terminal;
10. The interface circuit of claim 9 , wherein the seventh transistor receives the input of the logic gate signal at its gate terminal. receiving an application of a second voltage generated by stepping down a first voltage to operate and receiving an input signal whose signal level changes between the first voltage and a ground potential and the first voltage; including a latch circuit that outputs an output signal,
the latch circuit includes a first NOR circuit and a second NOR circuit each operating upon application of the second voltage;
in a first state in which the voltage level of the first voltage is higher than the logic threshold, outputting as the output signal a signal whose signal level changes in a phase opposite to that of the input signal;
When the voltage level of the first voltage decreases and transitions from the first state to a second state in which the voltage level is less than the logic threshold, the signal level in the first state immediately before transitioning to the second state outputting the output signal holding
An interface circuit characterized by:

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