JP3477448B2 - Level shift circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit for converting a logic level, and more particularly to one having a structure for preventing a shoot-through current generated when a signal changes.

[0002]

2. Description of the Related Art A latch type level shift circuit has been known as a level shift circuit. A concrete structure of this level shift circuit is shown in FIG. The level shift circuit shown in the figure includes two N-type transistors 51 and 52, two cross-coupled P-type transistors 53 and 54 whose gates are connected to each other's drains, and a first
And second inverters 55 and 56. The first inverter 55 inverts the input signal of the input terminal IN and operates with a low voltage source VDD of, for example, 1.5v. The elements other than the first inverter 55 are, for example, 3.3v
The two N-type transistors 51 and 52, which are elements on the high voltage side that are operated by the high voltage source VDD3, are grounded and are signals complementary to each other, that is, the input signals of the input terminals IN, and The inverted signal of the input signal from the first inverter 55 is received. The two P-type transistors 53,
54 has a source connected to the high voltage source VDD3 and has drains connected to the drains of N-type transistors 51 and 52, respectively, and the second inverter 56 connects the one N-type transistor 52 and the P-type transistor 54. The output side is connected to the output terminal OUT.

Next, the operation of the level shift circuit will be described. In the stationary state, for example, when the input signal is at the H (VDD) level and its inverted signal is at the L (VSS = 0v) level, the N-type transistor 51 is ON and the N-type transistor 5 is
2 is OFF, the P-type transistor 53 is OFF, and the P-type transistor 54 is ON. Also, in this state,
A node W1 which is a connection point between the N-type transistor 51 and the P-type transistor 53 is at L (VSS) level, and a node W2 which is a connection point between the N-type transistor 52 and the P-type transistor 54 is at H (VDD3 ) At the level. Transistors 51 and 53, Transistors 52 and 54
Are complementary to each other, so no current flows in this quiescent state.

After that, when the input signal changes to the L (VSS) level and becomes in operation, as shown in FIG. 33, the N-type transistor 51 is OFF and the N-type transistor 52 is ON.
To do. Therefore, the through current I flows from the high voltage source VDD3 through the P-type transistor 54 and the N-type transistor 52 in the ON state, and the potential of the node W2 starts to drop from the H (VDD3) level. The potential of the node W2 is VDD3-Vt
When p (Vtp is a threshold voltage of the P-type transistor 53) or less, the P-type transistor 53 starts to turn on,
The potential of the node W1 rises, the drain current of the P-type transistor 54 decreases, and the potential of the node W2 becomes lower.

Finally, the potential of the node W1 is H (VDD
3) level, the potential of the node W2 becomes L (0v) level, the through current stops flowing, and the second inverter 56
As a result, the output logic is inverted, and the next input signal change wait state is entered. Although the case where the input signal changes from the H level to the L level has been described above, the same applies to the case where the input signal changes vice versa.

However, in the conventional level shift circuit, the through current flows through the P-type transistor 54 and the N-type transistor 52 during operation to change the potential of the node W2. There was a drawback that the power was increased.

Therefore, conventionally, for example, Japanese Unexamined Patent Publication No. 10-190.
Japanese Unexamined Patent Publication No. 438-106946 and Japanese Unexamined Patent Publication No. 7-106946 propose a level shift circuit having a configuration in which a through current is cut off according to a change in the potential of the output node W2. The structure of this level shift circuit is shown in FIG. The level shift circuit shown in the figure has, in addition to the configuration shown in FIG.
High voltage source VDD3 and two P-type transistors 53 and 54
And a current cut-off transistor 57, 58 made up of a P-type transistor, respectively, and a gate of one current cut-off transistor 57 is connected to the node W1 via a delay element 59, 60 made up of two inverters. The potential is applied, and the potential of the node W2 is applied to the gate of the other current cut-off transistor 58 via the two delay elements 61 and 62. Furthermore, a small latch 63 is connected to the two nodes W1 and W2, and the latch 63 has two P-type transistors 64 and 65, which have sources connected to a high voltage source VDD3 and drains. Are respectively connected to the nodes W1 and W2 and the other gate.

In the conventional level shift circuit having the through current cutoff function, for example, when the input signal is at the H level, the potential of the node W2 is at the H (VDD3) level, and the current cutoff transistor 58 is turned off. Therefore, the connection between the high voltage source VDD3 and the P-type transistor 54 is cut off. Further, the potential of the node W1 is at the L (0v) level, the P-type transistor 53 and the current cutoff transistor 57 are ON, and the high voltage source VDD3 and the P-type transistor 53 are connected. During the operation in which the input signal changes from this state to the L level, the connection between the node W1 and the ground is cut off by the OFF operation of the N-type transistor 51, and the node W2 is grounded by the ON operation of the N-type transistor 52. The potential of the node W2 drops. This decrease in the potential is transmitted to the current cutoff transistor 58, but the transmission is delayed by a predetermined delay time by the two delay elements 61 and 62. During the delay time, the P-type transistor 53 is turned on due to the potential drop of the node W2.
Then, the high voltage source VDD3 and the node W1 are connected, the potential of the node W1 rises, and the P-type transistor 54 is turned off.
F Then, after that, the current cut-off transistor 5
8 turns on. Therefore, even if the N-type transistor 52 is turned on during this operation, the through current from the high voltage source VDD3 through the P-type transistor 54 and the N-type transistor 52 is cut off, so that the power consumption is reduced. On the other hand, when the current cut-off transistor 57 is turned off after a predetermined time delay due to the increase in the potential of the node W1, the small latch 63 prevents the node W1 from entering a high impedance state and the output from becoming indefinite. The internal P-type transistor 62 is turned on in accordance with the potential decrease of
By connecting the high voltage source VDD3 to the node W1,
Pull up.

[0009]

However, in the conventional level shift circuit having the shoot-through current cut-off function, the small latch 63 has a sufficiently large gate length L so that it can operate even at a low voltage, and the transistor is a transistor. However, since the operating currents of the N-type transistors 51 and 52 are generally small, the driving capacitance of the N-type transistors 51 and 52 is increased by the small latch 61, and the logic of the input signal is increased. There is a drawback that the delay time from the level change to the logical level change of the output terminal OUT of the level shift circuit becomes long.

Further, in the conventional level shift circuit having the through current interruption function, since the latch 63 is connected to the drains of the N-type transistors 51 and 52, in order to change the logic level of the output terminal OUT, It is necessary to fully swing the drain potentials of the N-type transistors 51 and 52, that is, the potentials of the nodes W1 and W2, between the potential of the high voltage source VDD3 and the ground potential, which is another cause of increasing the delay time. It is also accompanied. On the other hand, if the current capability of the N-type transistors 51 and 52 is increased so as to reduce the delay time, these N-type transistors 51 and 52 are
Size increases. Particularly, when the voltage of the low voltage source VDD becomes low, the current value flowing through the N-type transistors 51 and 52 becomes small.
Since the size of the device is further increased, there is a drawback that the area is increased.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a level shift circuit having a shoot-through current cut-off function that operates at high speed and has a short delay time without disposing the small latch as in the prior art. It is in.

[0012]

In order to achieve the above object, in the present invention, a resistor is connected to a connection point between a current cutoff transistor and a cross-coupled transistor,
A configuration is adopted in which the connection point is pulled up to a high voltage via this resistor .

That is , in the level shift circuit according to the first aspect of the present invention, a complementary input signal using the first voltage source as a power source is input, one end is grounded, and the other end is connected to the first and second nodes. First and second N-type transistors respectively connected,
A first cross-coupled connection, one end of which is connected to a second voltage source and the other end of which is connected to the first and second nodes, respectively.
And a second P-type transistor, a current cut-off unit that cuts off a connection between the second voltage source and the first or second P-type transistor when the level of the input signal changes, and cuts off a through current. A resistor connecting the second voltage source to the first or second node when the input signal is stationary ,
The current cutoff unit includes a third P-type transistor arranged between the second voltage source and the first P-type transistor, the second voltage source and the second P-type transistor. A fourth P-type transistor disposed between the first and second P-type transistors and the third P-type transistor.
And a transistor connected to a connection point between the second P-type transistor and the fourth P-type transistor.

[0014] level Rushifuto circuit of the invention of claim 2, wherein
Is a first and second N-type transistor, to which a complementary input signal using the first voltage source as a power source is input, one end of which is grounded, and the other end of which is connected to the first and second nodes, respectively. Cross-coupled first and second P-type transistors, one end of which is connected to a second voltage source and the other end of which is connected to the first and second nodes, respectively, and when the level of the input signal changes A current cut-off unit that cuts off a connection between the second voltage source and the first or second P-type transistor to cut off a shoot-through current; and when the input signal is stationary, the second voltage source is set to the first or the second. A resistor connected to a second node, wherein the current cutoff unit is a third P-type transistor arranged between the second voltage source and the first P-type transistor;
A fourth P-type transistor disposed between the second voltage source and the second P-type transistor, wherein the resistor includes the second voltage source and the first and third P-type transistors. A first resistor disposed between the connection point of the P-type transistors and a second resistor disposed between the connection point of the second voltage source and the connection points of the second and fourth P-type transistors. Ri consists a resistor, the first resistor is made of P-type transistors controlled by the potential of said second node, said second resistor is controlled by a potential obtained by inverting the potential of said second node It is characterized by comprising a P-type transistor.

The invention according to claim 3 is the same as claim 1 or
In the level shift circuit according to the second aspect, the resistance value of the resistor is set to a high resistance value so that a value of a current flowing from the second voltage source through its own resistance is substantially zero. To do.

The invention according to claim 4 is the same as claim 1 or
2. In the level shift circuit according to 2, the next-stage inverter is connected to the second node, and the gate capacitance of the next-stage inverter and the gate capacitance of the first P-type transistor are equal to those of the second node. It is characterized in that it is set to a small value so that when the potential drops, the potential drops faster.

The invention according to claim 5 is the same as claim 1 or
2. The level shift circuit according to 2, wherein the second and fourth
The P-type transistor is characterized in that it is set to a large size so that the potential of the second node rises quickly when the potential of the second node rises.

The invention according to claim 6 is the same as claim 1 or
In the level shift circuit 2 according to the shutdown of the first voltage source, characterized by having a function of fixing the second node to a predetermined potential.

[0019] Thus, in claims 1 to 6 Symbol mounting of the invention, the steady state in which the level of the input signal does not change, even if the situation ends of the first or second node is cut off, the first Since the second voltage source is connected to the first or second node via a resistor and pulled up, it is not necessary to arrange a small latch for pulling up as in the conventional case. Therefore, the driving capacitances of the first and second N-type transistors that change the logic of the two transistors (latch) in the cross-coupled connection are reduced, so that when the level of the input signal changes, the first or second node The potential drop is accelerated, the delay time is shortened, and the level shift circuit operates at high speed. Moreover, since the conventional pull-up resistor is smaller than the small latch, the layout area is reduced.

Particularly, in the inventions of claims 3, 4, and 5 , when the potential of the second node is lowered, the potential is lowered earlier, so that the delay time is further shortened and the level is reduced. Possible to further speed up shift circuit operation
Is.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A level shift circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a specific configuration of the level shift circuit according to the present embodiment.

In the figure, IN is a signal input terminal, I
NV0 is an inverter that inverts the signal input to the input terminal IN, and operates with a low voltage source (first voltage source) VDD of, for example, 1.5v. In the level shift circuit of FIG. 1, all the elements other than the inverter INV0 are high-voltage side elements that operate with a high-voltage source (second voltage source) VDD3 such as 3.3v.

In FIG. 1, N1 and N2 are a pair of N-type transistors, the sources of which are grounded.
One N-type transistor (first N-type transistor) N
The input signal of the input terminal IN is input to the gate of 1, and the inverted signal of the inverter INV0 is input to the gate of the other N-type transistor (second N-type transistor) N2. P1 and P2 are a pair of P-type transistors, the gates of which are mutually cross-coupled to the opposite drains, and the drains of which are connected to the drains of the N-type transistors N1 and N2, respectively. The connection point between one of these P-type transistors (first P-type transistor) P1 and the first N-type transistor N1 is the first node W1,
The other P-type transistor (second P-type transistor) P
2 and the N-type transistor N2 at the second node W
Set to 2.

Further, P3 and P4 are current cut-off transistors (current cut-off portions) each consisting of a pair of P-type transistors, the sources are connected to the high voltage source VDD3, and the drains are the sources of the P-type transistors P1 and P2, respectively. Connected to. The connection point between the one current cut-off transistor (third P-type transistor) P3 and the first P-type transistor P1 is the third node W3, and the other current cut-off transistor (fourth P-type transistor) P4 is the third node W3. A connection point between the second P-type transistor P2 and the second P-type transistor P2 is defined as a fourth node W4. The second node W2 is connected to the gate of the one current cut-off transistor P3 via an inverter INV1.
The gate of the other current cut-off transistor P4 is connected to the second transistor via the inverter INV1 and the inverter INV2.
Node W2 of is connected. The output terminal OUT is connected to the output side of the inverter INV2.

In addition, P5 is a resistor composed of a P-type transistor whose gate is grounded, one end of which is connected to the third node W3 and the other end of which is the fourth node W3.
4 is connected.

The operation of the level shift circuit configured as described above will be described below.

First, the potential of the signal at the input terminal IN is H (V
In the steady state at the DD) level, the N-type transistor N1
Is ON and the P-type transistor P1 is OFF. Further, the N-type transistor N2 is OFF and the P-type transistor P2 is ON. The first node W1 has a potential of 0v and the second node W2 has a potential of the high voltage VDD3 (3.3v). These operations are similar to those of the conventional latch type level shift circuit described above. Further, due to the potential (3.3v) of the node W2, one of the current cutoff transistors P3
Is on and the other current cut-off transistor P4 is off. When the one current cut-off transistor P3 is turned on, the high voltage source VDD3 and the fourth node W4 are connected via the transistor (resistor) P5, and the fourth node W4.
Is pulled up to the high voltage of the high voltage source VDD3, and accordingly, the second voltage is supplied via the P-type transistor P2 in the ON state.
Node W2 is also pulled up to the high voltage of the high voltage source VDD3. Therefore, it is possible to prevent the second and fourth nodes W2 and W4 from being in a high impedance state because both the current cutoff transistor P4 and the N-type transistor N2 are in an OFF state. As a result, the output terminal OUT
Is fixed at the H (VDD3) level.

Next, when the input signal changes from the H (VDD) level to the L (VSS) level, the N-type transistor N2 is turned on. However, the current cutoff transistor P
Since 4 is turned off, a through current does not flow from the high voltage source VDD3 through the P-type transistor P2 and the N-type transistor N2.

The state of the current flowing immediately after the change of the input signal is shown in FIG. In the figure, since the N-type transistor N2 is turned on immediately after the input signal changes, the second
, The current Igp1 for discharging the gate capacitance Cgp1 of the P-type transistor P1, the current Iginv for discharging the gate capacitance Cginv of the next-stage inverter Inv1, and the high voltage source VDD3 from the current cutoff transistor P3, the resistor P5, and the resistor P5. A current Idp flowing through the P-type transistor P2 flows. on the other hand,
A current Idn that flows to the ground through the N-type transistor N2 flows out from the node W2. Therefore, Iginv + Igp1 = Idn-Idp holds. Here, the resistance value of the transistor (resistance) P5 is set to a sufficiently large value so that the through current ldp does not flow. This setting is performed by the current cutoff transistor P3 and the P-type transistor P2 in the path through which the through current flows.
This is done in collaboration with the setting of the resistance value of. With this setting, the through current Idp in the above equation is ignored and the second node W2
In order to quickly lower the potential of and to reduce the delay time, it is preferable to increase the current Idn and set the current Iginv and the current Igp1 small. That is, the P-type transistor P1
Gate capacitance Cgp1 and the next-stage inverter Inv1
It is effective to set a small gate capacitance Cginv of.

After that, one P-type transistor P1 is turned on.
N, the other P-type transistor P2 is turned off, and when the logic of the latch portion composed of these is reversed, the inverter IN
After a predetermined delay time via V1 and INV2, the output terminal OUT is inverted to the L (0V) level, one current cutoff transistor P3 is turned off, and the other current cutoff transistor P4 is turned on. The state of waiting for input change of the input signal of is entered. Here, the current cutoff transistor P
Even if 4 is turned on, since the P-type transistor P2 is already turned off, no through current flows from the high voltage source VDD3 through these two transistors P4 and P2.
Further, even if both the current cutoff transistor P3 and the N-type transistor N1 are turned off, the current cutoff transistor P4 is turned on, so the high voltage source VDD3 and the third node W
3 is connected via a transistor (resistor) P5, and the fourth node W4 is pulled up to the high voltage of the high voltage source VDD3. Therefore, the P-type transistor P in the ON state
The first node W1 is also pulled up to the high voltage of the high voltage source VDD3 via 1 to prevent the first node W1 from entering the high impedance state.

Next, when the input signal changes from the L (VSS) level to the H (VDD) level, the N-type transistor N1 is turned on. However, the current cutoff transistor P
Since 3 is off, no through current flows from the high voltage source VDD3 through the P-type transistor P1 and the N-type transistor N1.

The state of the current flowing immediately after the change of the input signal is shown in FIG. In the figure, since the N-type transistor N2 is turned off immediately after the input signal changes, the current −Igp1 for charging the gate capacitance Cgp1 of the P-type transistor P1 and the gate of the inverter Inv1 are output from the second node W2. The current −Iginv that charges the capacitance Cginv flows out, and the second node W2
High voltage source VDD3 to current cutoff transistors P4 and P
A current Idp flows in through the type transistor P2. Therefore, Iginv + Igp1 = Idp holds. To reduce the delay time, the current Idp
Is preferably set to be large and the current Igp1 and the current lginv are set to be small. That is, the current cutoff transistor P
It is effective to increase the size of the P-type transistor P2 and the P-type transistor P2 and reduce the gate capacitance of the next-stage inverter INV1.

From the above, the two P-type transistors P1 and P2 have optimum values for matching the rising time and the falling time of the potential of the second node W2. Further, if the size of the current cutoff transistors P3 and P4 is larger than the size of these P-type transistors P1 and P2, the delay time can be further shortened.

In this embodiment, a resistor P5 connected to the third and fourth nodes W3 and W4 is arranged, and this resistor P5 is connected.
5, the high impedance state of the first and second nodes W1 and W2 is prevented, so that it is not necessary to dispose a small latch as in the related art on the first and second nodes W1 and W2. As a result, two N-type transistors N1 and N2
Respectively, the driving capacity thereof decreases, so that the rising and falling speeds of the potential of the second node W2 become faster, and the delay time is effectively shortened. Moreover, N-type transistors N1 and N
Since 2 can be designed in a small size and only the resistor 5 needs to be arranged in place of the conventional small latch, the layout area can be reduced.

Assuming that the resistance value of the transistor (resistor) P5 is very large, the operation limit of the level shift circuit of the present embodiment is VDD ≦ Vtn (Vtn is the threshold voltage of the N-type transistors N1 and N2). ). Therefore, it is possible to secure a large design margin.

(Modification) FIGS. 4, 5 and 6 show modifications of the above embodiment .

FIG. 4 shows a modification of the arrangement position of the transistor (resistor) P5. In the above-described embodiment , when one P-type transistor (for example, P4) is in the OFF state, the other P-type transistor P3 in the ON state is in the ON state, and this P-type transistor P3 in the ON state is utilized.
Through the second and fourth nodes W2 and W4 to the high voltage source VD
Although it is pulled up to the high voltage of D3, in the present modification, the pull-up resistor (first resistor) P5 of the nodes W1 and W3 is used.
1 and a resistor (second resistor) P52 for pulling up the nodes W2 and W4. These resistors are constituted by P-type transistors and connected to the high voltage source VDD3.
These transistors P3 and P4 are turned on so that the P-type transistors P3 and P4 are turned off.
4 is used to control the P-type transistors (resistors) P51 and P52 by using a signal obtained by inverting the signal controlling 4 (the potential of the second node W2 and the potential obtained by inverting this potential). The functions of these resistors P51 and P52 are the same as those of the resistor (transistor) P5 of the above-mentioned embodiment , and the description thereof is omitted.

FIG. 5 is a further modification of the modification of FIG. That is, in the level shift circuit of FIG. 5, the resistors P51 and P52 for node pull-up are connected to the high voltage source VDD3 via the resistor P60 which is a P-type transistor. The function of this modification is the same as that of the modification of FIG.

FIG. 6 shows a level shift circuit having a function of fixing the output logic when the internal low voltage power supply is shut down. The level shift circuit shown in FIG. 6 is based on the level shift circuit shown in FIG. 1, and further includes an input terminal SD for receiving a shutdown command signal of a low voltage power supply, a P-type transistor P65, and an N-type transistor N66. ing. The P-type transistor P65 is a high voltage source VD
D3 is connected to the second node W2, and the shutdown command signal (L
Level) is entered. Also, the N-type transistor N
In 66, the drain is connected to the sources of the N-type transistors N1 and N2, the sources are grounded, and the shutdown command signal of the input terminal SD is input to the gate.

Therefore, in this modification, the N-type transistor 66 is turned off at the time of the shutdown command of the low-voltage power supply.
Then, the connection between the second node W2 and the ground is cut off, the P-type transistor P65 is turned on, the second node W2 is forcibly connected to the high voltage source VDD3, and the logic of the output terminal OUT is changed. It can be fixed at H (VDD3) level.

[0042] (the present invention related art) or less, a level shift circuit of the related art of the present invention will be described with reference to FIG.

FIG. 7 shows the overall structure of a level shift circuit according to the related art . The related art is characterized in that, compared with the level shift circuit of the above-described embodiment , the level conversion does not employ a latch structure composed of two transistors each having a gate connected to the other drain. The details will be described below.

In FIG. 7, IN is an input terminal and INV0
Is an inverter that inverts a signal input to the input terminal IN, and operates with a low voltage source (first voltage source) (VDD). In the level shift circuit of FIG. 7, all elements other than the inverter INV0 operate on the high voltage source (second voltage source) VDD3.

Further, in FIG. 7, N1 and N2 are a pair of N-type transistors which receive mutually complementary signals, and one N-type transistor (first transistor) N1 has its gate having a signal of the input terminal IN. Therefore, the other N-type transistor (second transistor) N2 receives the inverted signal from the inverter INV0 at its gate. The sources of these N-type transistors N1 and N2 are grounded, and the drains thereof are connected to the first and second nodes W1 and W2, respectively.
Therefore, when one of the N-type transistors N1 and N2 is turned on, the first or second node W1 or W2 is grounded and the potential of the first or second node W1 or W2 is set to L (0v).
Lower to a level.

Further, B is a precharge circuit, which is 1
The supply circuit 40 includes a pair of P-type transistors P3 and P4, an interrupt circuit 50 includes a pair of N-type transistors N3 and N4, and a P-type transistor P5 that operates as a resistor. One P-type transistor (first P-type
The type transistor P3 has a source connected to the high voltage source VDD3 and a drain connected to the first node W1.
The other P-type transistor (second P-type transistor) P
4, the source is connected to the high voltage source VDD3, and the drain is connected to the second node W2. Either P
-Type transistor P3 or P4 is ON, high voltage source VD
D3 is connected to the first or second node W1 or W2, and the potential of the first or second node W1 or W2 is changed to the high voltage source VDD.
Precharge to a high voltage of 3.

In the precharge circuit B,
One N-type transistor (third N-type transistor) N
3 is the first node W1 and the N-type transistor N in FIG.
1 and the other N-type transistor (fourth N-type transistor) N4 is arranged between the second node W2 and the N-type transistor N2. In these N-type transistors N3 and N4, when the P-type transistors P3 and P4 are precharged, the corresponding first or second nodes W1 and W2 are connected to the ground via the N-type transistors N1 and N2, respectively. Prevent. Further, the P-type transistor P5 is connected to the drains (first and second nodes W1 and W2) of the two P-type transistors P3 and P4. In the P-type transistor P5, the high voltage source VDD3 is connected to the first or second node W1, as in the above embodiment .
It is arranged to connect to W2 and prevent the first and second nodes W1 and W2 from entering a high impedance state.

Further, A is a control circuit, which detects that the first or second node W1 or W2 has dropped to the L (0v) level, and after this detection, the first or second node W1. , W2 is precharged to H (VDD3) level. The internal structure of the control circuit A is shown in FIG.

The control circuit A of FIG. 8 has a flip-flop circuit FF and a precharge control circuit 70 having two inverters INV1 and INV2. The flip-flop circuit (level detection circuit) FF has first and second two-input NAND circuits Nand1 and Nand2.
The first NAND circuit Nand1 receives the potential of the first node W1 and the output signal of the second NAND circuit Nand2, and the second NAND circuit Nand2 receives the potential of the second node W2 and the first NAND circuit Nand2. It receives the output signal of NAND circuit Nand1. The outputs of these first and second NAND circuits become the outputs of the flip-flop circuit FF. Therefore,
When the first node W1 becomes L (0v) level,
The output of the first NAND circuit Nand1 is H (VDD3)
Level, the output of the second NAND circuit Nand2 is L (0
v) level, while the second node W2 is at L (0
v) When it goes to the second level, the second NAND circuit Nan
The output of d2 becomes H (VDD3) level, and the output of the first NAND circuit Nand1 becomes L (0v) level.

Precharge control circuit 7 of the control circuit A
0 controls the precharge operation of the precharge circuit B, and one inverter INV1 controls the first NAND circuit Na of the flip-flop circuit FF.
It receives and inverts the output of nd1 and outputs the inverted signal to the P-type and N-type transistors P3 and N3 of the precharge circuit B.
Output to the gate of. The other inverter INV2 is connected to the second NAND circuit Na of the flip-flop circuit FF.
It receives and inverts the output of nd2 and outputs the inverted signal to the P-type and N-type transistors P4 and N4 of the precharge circuit B.
Output to the gate of.

Next, the operation of the level shift circuit of the related art will be described.

In the steady state, the first and second nodes W1 and W2
Are both at the H (VDD3) level. When the input signal is at H (VDD3) level, N-type transistor N
1 and N2 are turned on and off respectively, and two outputs of the flip-flop circuit FF (first and second NAND circuits Nan
The output of d1) is at the H (VDD3) level and the L (0v) level and holds its logic. At this time, the N-type transistors N3 and N4 are OFF and ON, respectively, and the P-type transistors P3 and P4 are ON and OFF, respectively. N-type transistors N1 and N3, and N-type transistor N
2 and N4 are complementary logics.

In the above state, for example, the input signal H
When the (VDD) level is changed to the L (0v) level, the N-type transistor N2 is turned on. At this time, in the precharge circuit B, the N-type transistor N4 is in the ON state, but the P-type transistor P4 is in the OFF state.
A through current does not flow to the ground through 4, N4 and N2. In this case, a current as shown in FIG. 9 flows. That is, immediately after the input signal changes, the N-type transistor N
Since 2 is turned on, the current Idn flowing to the ground via the N-type transistors N4 and N2 flows out from the second node W2, and the second NAND circuit Nand2 in the flip-flop circuit FF flows to the second node W2. Gate capacitance C
Current Igand2 for discharging gand2
And the current Idp flowing through the P-type transistors P3 and P5. Therefore, Ignand2 = Idn-Idp is established. Here, if the through current Idp does not flow, that is, if the resistance value of the P-type transistor (resistance) P5 is sufficiently large, the through current Idp can be ignored. Therefore, in order to quickly lower the potential of the second node W2 and shorten the delay time, the current Idn is increased and the current Ignan is increased.
It is advisable to set d2 small. Specifically, it is effective to set the gate capacitance Cgnand2 of the NAND circuit Nand2 of the flip-flop circuit FF small. Further, since the current Idp is a current flowing through the two transistors P3 and P5, it is easy to keep this current value small.

After that, the potential of the second node W2 is further reduced and the logic of the flip-flop circuit FF is reversed,
When the output of the NAND circuit Nand2 is inverted to the H (VDD3) level and the output of the NAND circuit Nand1 is inverted to the L (0v) level, the N-type transistor N4 is turned off and the P-type transistor P4 is turned on. Therefore, the second node W2 Is precharged to H (VDD3) level by the high voltage source VDD3. Since this precharge operation is performed by the P-type transistor P4, it is fast. On the other hand, the P-type transistor P3 is turned off and the high voltage source VDD
3 to stop the precharge from the first node W1 and the N-type transistor N3 is turned on to turn on the first node W1.
1 is connected to the N-type transistor N1 in the OFF state to enter the state of waiting for the next change of the input signal. In this state, the high voltage of the high voltage source VDD3 is in the ON state of the P-type transistor P.
4, the voltage is applied to the first node W1 via the resistor P5, so that the potential of the first node W1 becomes the H (VDD3) level, and the P-type transistor P3 and the N-type transistor N1
The high-impedance state of the first node W1 due to the turning off of the signal is prevented.

The input signal changes from L (0v) level to H (VD
The operation when the level is changed to D) is the same as the operation described above, and thus the description thereof is omitted.

Here, the switching levels of the two NAND circuits Nand1 and Nand2 of the flip-flop circuit FF are set high. Therefore, the N-type transistor N
When 1 and N2 are ON, the potential of the corresponding first or second node W1 or W2 is changed from H (VDD3) level to L (0
v) Since it is not necessary to make a full swing to the level, it is possible to operate at a higher speed and lower power consumption as compared with the conventional level shift circuit that needs a full swing.

Since the N-type transistors N1 and N2 need only drive the gate capacitances of the corresponding NAND circuits Nand1 and Nand2 of the flip-flop circuit FF, respectively, these transistors N1 and N2 are suppressed to a small size. It is possible. Therefore, it is possible to reduce the layout area.

The operation limit of the level shift circuit of the related art is VDD ≧ Vtn, assuming that the resistance value of the P-type transistor (resistor) P5 is very large. Therefore, a large design margin can be secured.

(First Modification) FIGS. 10 and 11 show a first modification of the related art . In the level shift circuit of FIG. 10, the control circuit A is composed of a small number of transistors. That is, as can be seen by comparing with the level shift circuit of FIG. 8, the two inverters INV1 and INV2 are omitted and the NAND
One of the P-type and N-type transistors P3 and N3 is controlled by the output of the circuit Nand2, and the NAND circuit Nand1
The other P-type and N-type transistor P4 with the output of
It controls N4. Therefore, the level shift circuit of FIG. 10 can perform the same operation as the level shift circuit of FIG. 8 with a small number of transistors.

Further, in the level shift circuit of FIG. 11, the flip-flop circuits are two NOR circuits Nor1 and No.
The inverters INV10 and INV11 are arranged in front of these NOR circuits, respectively. Further, similar to the level shift circuit of FIG. 10, the two inverters INV1 and INV1 of the precharge control circuit 70 are provided.
V2 is omitted. Therefore, in the level shift circuit of FIG. 11, the same operation as that of the level shift circuit of FIG. 8 is performed, and due to the presence of the two inverters INV10 and INV11, the drive capacity of the two NOR circuits Nor1 and Nor2 is reduced. As a result, the operating speed of the flip-flop circuit increases.

(Second Modification) FIGS. 12 to 16 show a second modification of the related art . The level shift circuit of FIG. 12 has a function of fixing the logic of the flip-flop circuit to the logic before the shutdown when the low voltage source VDD is shut down. Specifically, when the shutdown command signal (H (VDD3) level) is received at the terminal SD, the two NOR circuits Nor3 and Nor4 operate the precharge circuit B to operate the first and second nodes. Both W1 and W2 are fixed to the H (VDD3) level, and the outputs of the two NAND circuits Nand1 and Nand2 of the flip-flop circuit are fixed.

Similarly, the level shift circuit of FIG. 13 has a function of fixing the logic of the flip-flop circuit to the logic before the shutdown when the low voltage source VDD is shut down. The difference from the level shift circuit of FIG. 12 is that the flip-flop circuit is composed of two NOR circuits Nor1 and Nor2, and that when a shutdown command signal (H (VDD3) level) is received at the terminal SD. By the two NOR circuits Nor5 and Nor6,
Regardless of the level of the first and second nodes W1, W2,
Two NOR circuits Nor of the flip-flop circuit
The output of No. 1 and Nor2 is fixed to the logic before shutdown of the low voltage source. Further, in the level shift circuit of FIG. 13, the shutdown command signal (H (V
DD3) level), P-type transistor (resistor) P
5 is turned off. This is to prevent a through current from flowing through these transistors and the P-type transistor P5 when the P-type transistor P3 and the N-type transistors N4 and N2 are ON, for example.

In the level shift circuit of FIG. 14, when the low voltage source VDD is shut down, the logic of the flip-flop circuit is forced, and the NAND circuit Nand1 is set to L (0
v) level, in the NAND circuit Nand2, H (VDD
3) It is fixed at the level. That is, in the level shift circuit of FIG. 14, an inverter INV12 is further added to the level shift circuit of FIG. 12, the shutdown signal (H (VDD3) level) input to the terminal SD is inverted by the inverter INV12, and the inverted signal is obtained. To the NAND circuit Nand2 of the flip-flop circuit to input NAN
The output of the D circuit Nand2 is fixed to the H (VDD3) level. The shutdown signal is given to the P-type transistor P3 and N-type transistor N3 and the P-type transistor P4 and N-type transistor N4 via the NOR circuits Nor3 and Nor4, and the potentials of the first and second nodes W1 and W2 are H ( VDD3) level is fixed.

The level shift circuit of FIG. 15 has two NOR circuits which are flip-flop circuits of the level shift circuit of FIG.
Circuits Nor1, Nor2 and two inverters INV1
0, INV11, and inverter INV1
2 is omitted and the shutdown signal is directly sent to the NOR circuit No.
It has the configuration input to r2. This level shift circuit is also shown in Figure 1.
4 has the same function as the level shift circuit.

The level shift circuit of FIG. 16 is similar to that of FIG.
And the same function as that of the level shift circuit of FIG. 15 is achieved by another configuration. That is, two NAND circuits Nand1 and N constituting a flip-flop circuit
Inverters INV12 and N are provided in front of and2, respectively.
OR circuit Nor5, inverters INV13 and INV1
4 is arranged and a shutdown signal from the terminal SD is input to the NOR circuit Nor5.

(Third Modification) FIGS. 17 and 18 show a third modification of the related art . These have a function of arbitrarily switching the output logic of the level shift circuit when the low voltage source VDD is shut down. In the level shift circuit of FIG. 17, based on the configuration of FIG. 16, a NAND circuit Nand3 is arranged in place of the inverter INV14 of the level shift circuit of FIG. 16, another NAND circuit Nand4 is arranged, and a priority signal is further received. A terminal PR is provided. The NAND circuit Nand4 receives the shutdown signal (H (VDD3) level) from the terminal SD and the priority signal from the terminal PR, and its output is input to the NAND circuit Nand3.

Therefore, in the level shift circuit of FIG.
At the time of inputting the shutdown signal, the output of the NAND circuit Nand3 is switched between the H level and the L level by changing the priority signal to the terminal PR into the H (VDD3) level and the L (0v) level, and the flip-flop circuit. N
The logic of the AND circuit Nand2 can be switched between the H (VDD3) level and the L (0v) level. In this level shift circuit, the other NA of the flip-flop circuit is used.
The ND circuit Nand1 is always fixed at the H (VDD3) level.

In the level shift circuit of FIG. 18, the level shift circuit of FIG. 17 is improved so that the other NAND circuit Nand1 of the flip-flop circuit also becomes H (V
It is possible to switch between the DD3) level and the L (0v) level. Specifically, the inverter INV15,
Two NAND circuits Nand5 and Nand6 are separately arranged. One of the NAND circuits Nand5 has a terminal P
The priority signal from R is input through the inverter INV15, and the shutdown signal (H (VDD3) level) is input from the terminal SD. This NAND
The output of the circuit Nand5 is input to another NAND circuit Nand6.

Therefore, in this level shift circuit, by changing the priority signal of the terminal PR to the H (VDD3) level and the L (0v) level, the NAND circuit NAND is obtained.
The output logic of the NAND circuit Nand1 of the flip-flop circuit is also changed to H (V
It is possible to switch between the DD3) level and the L (0v) level.

(Fourth Modification) FIGS. 19 to 21 show a fourth modification of the related art .
These are edge trigger type level shift circuits.

In the level shift circuit shown in FIG. 19, the first flip-flop circuit FF1 receiving the clock signal CLK and the potential of the first node W1 and the clock signal CLK.
And a second flip-flop circuit FF2 that receives the potential of the second node W2, and these flip-flop circuits FF
1, and a third flip-flop circuit FF3 that receives the outputs of FF2.

In the level shift circuit of FIG. 19, when the clock signal CLK is at L level, the first and second flip-flop circuits FF1 and FF2 are in the reset state, the precharge circuit B is the NAND circuit Nand7 and the inverter. INV15 allows the first and second nodes W1,
W2 is precharged to the high voltage of the high voltage source VDD3. The third flip-flop circuit FF3 is in the level holding state. After that, when the clock signal transits to the H level, the NAND circuit Nand7 and the inverter INV15 cause the two P-type transistors P3 and P to be transferred.
4 turns off and the precharge stops, and 2
N-type transistors N3 and N4 are turned on, and the terminal IN
Depending on the level of the input signal of the first or second node W
1 and W2 drop to the L (0v) level, which are taken into the first or second flip-flop circuits FF1 and FF2, and the logic of the flip-flop circuit FF3 is set. When this acquisition is completed, the NAND circuit Na
The nd7 and the inverter INV15 cause the precharge circuit B to precharge the first and second nodes W1 and W2 again to the high voltage of the high voltage source VDD3.

FIG. 20 is a modification of the level shift circuit of FIG. 19, in which the two N-type transistors N3 and N4 of the level shift circuit of FIG. 19 are shared by one N-type transistor N5. .

The level shift circuit shown in FIG. 21 is the same as that shown in FIG.
This is a modification of part of the level shift circuit of. That is, the other N-type transistors N7 and N8 are provided between the first and second nodes W1 and W2 and the N-type transistors N3 and N4.
Are arranged and these N-type transistors are connected to the clock signal CL.
By controlling by K, H of the clock signal CLK
When rising to the level, these N-type transistors N
7 and N8 are turned on to change the logic level of the first or second node W1 or W2 according to the input signal of the terminal IN.

(Fifth Modification) FIGS. 22 and 23 show a level shift circuit in which a test mode function is further added to the edge trigger type level shift circuit of FIG.

In the level shift circuit of FIG. 22, the two N-type transistors N10 and N11 are turned off by the test mode signal (L level) input to the terminal NT during the test, and the input signal (input Two N-type transistors N1 and N that operate according to the input signal of the terminal IN)
2 is separated from the P-type transistors P3 and P4,
Two N-type transistors N12 and N13 for the test mode are turned on by a signal obtained by inverting the test mode signal by the inverter INV16, and the test signal input to the terminal INT and the inverted signal by the inverter INV17 are output. Two operating N-type transistors N14,
N15 is connected to the P-type transistors P3 and P4,
In the test mode, the logic level of the first and second nodes W1 and W2 is changed by the test signal of the terminal INT.

The level shift circuit of FIG. 23 is an improvement of the level shift circuit of FIG. That is, similarly to the N-type transistor N5 that grounds the two normal N-type transistors N1 and N2, the N-type transistor N16 that grounds the two N-type transistors N14 and N15 for the test mode is provided, and the terminal NT The test mode signal (L level) input to the NAND circuit NAND8 and NO
The output of the R circuit Nor6 is controlled to control ON / OFF of the N-type transistor N5 for normal operation in normal operation in accordance with the output of the NAND circuit Nand8 of the precharge control circuit 70, and in the test mode for the test mode. N
Type transistor N16 is set to N of the precharge control circuit 70.
The ON / OFF control is performed according to the output of the OR circuit Nor6.

(Sixth Modification) FIGS. 24 and 25 show a sixth modification of the related art .

The level shift circuit shown in FIG. 24 is obtained by adding a reset function to the edge shift type level shift circuit shown in FIG.

That is, in the level shift circuit of FIG. 24, the reset signal input to the reset terminal R is fed to the inverter I.
It is input to one NOR circuit Nor7 of the flip-flop circuit FF3 via NV18 to fix the output logic and at the same time to output the reset signal to the NAND circuit Nand9, and the precharge circuit B causes the first and second nodes to operate. The configuration is such that W1 and W2 are precharged to the high voltage of the high voltage source VDD3.

Further, the level shift circuit of FIG.
The level shift circuit of No. 4 has a set function added thereto. That is, in the level shift circuit of FIG. 25, the set signal input to the set terminal S is supplied to the inverter INV19.
Via the input to the other NOR circuit Nor8 of the flip-flop circuit FF to fix the output logic and output the set signal to the NAND circuit Nand9,
The precharge circuit B causes the first and second nodes W1,
W2 is configured to be precharged to the high voltage of the high voltage source VDD3.

(Seventh Modification) FIG. 26 shows a seventh modification of the related art . The level shift circuit shown in the figure constitutes a tri-state level shift circuit.

That is, in the level shift circuit of FIG. 26, the combination of the levels of the output terminals OUT1 and OUT2 is
In addition to “H, L” and “L, H”, the state of “H, H” is created. Specifically, the pair of N-type transistors N1 and N
2 is further provided with one N-type transistor N17, one pair of P-type transistors P3 and P4 is further provided with one P-type transistor P6, and one pair of N-type transistors N3 and N4 is provided. Then, one N-type transistor N18 is further provided. Further, a P-type transistor (resistor) P7 is provided corresponding to the P-type transistor (resistor) P5.

Then, in a normal state, the input signal of the terminal C is set to the L (0v) level, the N-type transistor N18 is turned off, and the node W3 is held in the precharged state. In this state, depending on the input signal at the terminal IN and its inverted signal, the NAND circuits Nand10 and Nand1
The pair of N-type transistors N1 and N2 are turned on or off through the control circuit 1 and the pair of output terminals O is controlled by the control circuit 30.
Set the logic level of UT1 and OUT2 to "H, L" or "L,
H ". On the other hand, when controlling the logic levels of the output terminals OUT1 and OUT2 to "H, H", the input signal of the terminal C is set to the H (VDD) level. As a result, the N-type transistor N17 is turned on, and the node W3 is set to L (0
The control circuit 30 controls the logic levels of the pair of output terminals OUT1 and OUT2 to "H, H" in accordance with the decrease in the potential of the node W3.
In the figure, Nand 12 constitutes a precharge control circuit 70 for controlling the precharge of the nodes W1, W2, W3.

(Eighth Modification) FIGS. 27 to 29 show an eighth modification of the related art .

These level shift circuits correspond to the pair of N-type transistors N in the level shift circuit shown in FIG.
This is an improvement of the circuit for generating the complementary signals input to the terminals 1 and N2. That is, in the level shift circuit of FIG. 8, the delay time of the control circuit A is short, and the delay time required for a series of changes from the change of the input signal to the setting of the flip-flop circuit FF and the precharge to the high voltage VDD3. However, if the delay time is shorter than the delay time of the inverter INV0 on the low voltage VDD side, it is possible that the first or second node W1 or W2 to be precharged is erroneously discharged. That is, as shown in FIG. 31, when the input signal waveforms to the pair of N-type transistors N1 and N2 are both at H level at the same time and the delay time of the control circuit A is short, the first and second It is conceivable that the nodes W1 and W2 are alternately discharged and precharged, and a pulsed output waveform is erroneously output to the output terminal. In particular, when the input signal transits from the H level to the L level, the input system is composed of high breakdown voltage transistors, the output system is composed of low breakdown voltage transistors, and the delay time of the high breakdown voltage system is higher than that of the low breakdown voltage system. It is considered that malfunction occurs when it is very long. In this modification, in order to prevent this malfunction,
Only after one of the complementary signals to the pair of N-type transistors N1 and N2 has transited to the L level, the other of the complementary signals is set to H.
It is configured such that one and the other of the complementary signals do not become the H level at the same time by not setting the level.

In the level shift circuit of FIG. 27, an inverter INV27 is used instead of the inverter INV0 of FIG.
A delay circuit composed of two inverters INV28 and INV29, and a NOR circuit Nor that receives the output of the inverter INV29 and the output of the first-stage inverter INV27.
And 27 generate complementary input signals.

Further, in the level shift circuit of FIG. 28, 2
The inverters INV30 and INV31 and the flip-flop circuit FF4 generate complementary input signals.

Furthermore, in the level shift circuit of FIG.
By the individual Schmitt circuits SchA and SchB, the inverter INV32, and the flip-flop circuit FF4,
By generating complementary input signals, as shown in FIG. 30, the switching level of the one Schmitt circuit SchA is set low and the switching level of the other Schmitt circuit SchB is set high.

In the above description, the level shift circuit for converting a low voltage logic level into a high voltage logic level has been described. However, the present invention is not limited to this, and conversely the high voltage logic level is lowered. It is needless to say that the same can be applied to a level shift circuit that converts a voltage into a logic level. In this case, the first voltage source is the high voltage source and the second voltage source is the low voltage source.

[0091]

As described in the foregoing, according to the level shift circuit of claim 1 to claim 6 Symbol mounting of the invention, the steady state in which the level of the input signal does not change, both ends of the first or second node Since the first or second node is pulled up by connecting the second voltage source through the resistor in the situation of being cut off, there is no need to arrange a small latch for pulling up as in the conventional case. Since the driving capacitances of the first and second N-type transistors have been reduced, the potential drop of the first or second node when the level of the input signal changes is promoted,
It is possible to provide a level shift circuit which can reduce the delay time, operates at high speed, and has a small layout area.

In particular, according to the third, fourth and fifth aspects of the invention, since the configuration is made so as to promote the lowering of the potential of the second node, the delay time can be further shortened and the level can be reduced. der can be further high-speed operation of the shift circuit
It

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a level shift circuit according to an embodiment of the present invention .

FIG. 2 is an explanatory diagram of a current flowing through the same level shift circuit when an input signal changes from H level to L level.

FIG. 3 is an explanatory diagram of a current flowing through the same level shift circuit when the input signal changes from L level to H level.

FIG. 4 is a diagram showing a modification of the arrangement position of resistors in the level shift circuit according to the same embodiment.

FIG. 5 is a diagram showing another modification of the same level shift circuit.

FIG. 6 is a diagram showing a modified example of the same level shift circuit, showing a level shift circuit having a fixed output logic configuration when the internal power supply is shut down.

FIG. 7 is a diagram showing a schematic configuration of a level shift circuit according to a related technique of the present invention .

FIG. 8 is a diagram showing a specific configuration of the same level shift circuit.

FIG. 9 is an explanatory diagram of a current flowing through the same level shift circuit when the input signal changes from the H level to the L level.

FIG. 10 shows a first modified example of the related art of the present invention ,
It is a diagram in which a precharge control circuit included in the level shift circuit is modified.

FIG. 11 is a diagram showing a modified first example of the related technique, in which a flip-flop circuit included in the level shift circuit is modified.

FIG. 12 shows a second modification of the related art of the present invention ,
It is a figure which shows the structure of the level shift circuit which has a function which fixes logic at the time of a low voltage source shutdown.

FIG. 13 is a diagram showing another configuration of the level shift circuit of the second modified example.

FIG. 14 is a diagram showing still another configuration of the level shift circuit of the second modified example.

FIG. 15 is a diagram showing another configuration of the level shift circuit of the second modified example.

FIG. 16 is a diagram showing still another configuration of the level shift circuit of the second modified example.

FIG. 17 shows a third modification of the related art of the present invention ,
It is a figure which shows the structure of the level shift circuit which has a function which outputs a predetermined logic preferentially at the time of a low voltage source shutdown.

FIG. 18 is a diagram showing another configuration of the level shift circuit of the third modified example.

FIG. 19 is a diagram showing a configuration of an edge trigger type level shift circuit according to a fourth modified example of the related art of the present invention .

FIG. 20 is a diagram showing another configuration of the edge trigger type level shift circuit of the fourth modified example.

FIG. 21 is a diagram showing still another configuration of the edge trigger type level shift circuit of the fourth modified example.

FIG. 22 is a diagram showing the configuration of an edge trigger type level shift circuit with a test mode function of a fifth modified example of the related art of the present invention .

FIG. 23 is a diagram showing another configuration of the edge trigger type level shift circuit with the test mode function of the modified example.

FIG. 24 is a diagram showing a configuration of an edge trigger type level shift circuit with a reset function according to a sixth modified example of the related art of the present invention .

FIG. 25 is a diagram showing a configuration in which a set function is added to an edge trigger type level shift circuit with a reset function of the modified example.

FIG. 26 is a diagram showing a configuration of a tri-state level shift circuit according to a seventh modified example of the related art of the present invention .

FIG. 27 is a diagram showing the configuration of a level shift circuit according to an eighth modification of the related art of the present invention .

FIG. 28 is a diagram showing another configuration of the level shift circuit of the modified example.

FIG. 29 is a diagram showing still another configuration of the level shift circuit of the modified example.

FIG. 30 is a diagram showing an operation of the same level shift circuit.

FIG. 31 is a diagram showing input waveforms and output waveforms that can occur in the level shift circuit according to the related art of the present invention .

FIG. 32 is a diagram showing a configuration of a conventional level shift circuit.

FIG. 33 is a diagram illustrating a current flowing when the same level shift circuit operates.

FIG. 34 is a diagram showing the configuration of another conventional level shift circuit.

[Explanation of symbols]

IN input terminal VDD low voltage source (first voltage source) VDD3 high voltage source (second voltage source) N1 N-type transistor (first
N-type transistor) N2 N-type transistor (second
N-type transistor) P1 P-type transistor (first
P-type transistor) P2 P-type transistor (second
P-type transistor) P3 P-type transistor (third P-type transistor, current interruption unit) P4 P-type transistor (fourth P-type transistor, current interruption unit) P5 P-type transistor (resistor) P51 P-type transistor (first 1
Resistance) P52 P-type transistor (second
INV0, INV1, INV2 inverter W1 first node W2 second node W3 third node W4 fourth node A control circuit B precharge circuit FF flip-flop circuit (level detection circuit) NAND1, NAND2 NAND circuit 40 supply circuit 50 intermittent circuit 70 precharge control circuit P3 P-type transistor (first
P-type transistor) P4 P-type transistor (second
P-type transistor) N3 N-type transistor (3rd
N-type transistor) N4 N-type transistor (4th
N-type transistor) SD shutdown terminal CLK clock terminal NT test mode terminal INT test terminal R reset terminal S set terminal C control terminal 30 control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-253417 (JP, A) JP-A-5-315931 (JP, A) JP-A-5-206827 (JP, A) JP-A-10- 149238 (JP, A) JP 11-103240 (JP, A) JP 9-93114 (JP, A) JP 8-79053 (JP, A) JP 2000-209074 (JP, A) Kai 2000-165207 (JP, A) Zhang Y. et al, Low clock-swing condition precharge flip-flop for more than 30% power red reduction, Electronics Letters, April 2000, Vol. 36, No. 9, Page 785-786 (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/0185 H03K 17/16 H03K 17/687

Claims (6)

(57) [Claims] 1. Complementary input signals powered by a first voltage source.
Signal is input, one end is grounded , the other end is connected to the first and second nodes, respectively, and first and second N-type transistors, and one end is connected to the second voltage source and the other end is The first and the first
The first of the cross-coupled connections, each connected to two nodes
And a second P-type transistor, the second voltage source and the second voltage source when the level of the input signal changes.
A current cutoff unit that cuts off a through current by cutting off the connection with the first or second P-type transistor , and the second voltage source is connected to the first voltage source when the input signal is stationary.
Or a resistor connected to the second node, the current blocking unit includes a third P-type transistor disposed between the second voltage source and the first P-type transistor, wherein A fourth P-type transistor disposed between the second voltage source and the second P-type transistor, wherein the resistor includes the first P-type transistor and the third P-type transistor. connection points, and level Rushifuto circuit, characterized in that consisting of transistors connected to a connection point between the second P-type transistor and the fourth P-type transistor. 2. Complementary input signals powered by a first voltage source.
Signal is input, one end is grounded , the other end is connected to the first and second nodes, respectively, and first and second N-type transistors, and one end is connected to the second voltage source and the other end is The first and the first
The first of the cross-coupled connections, each connected to two nodes
And a second P-type transistor, the second voltage source and the second voltage source when the level of the input signal changes.
A current cutoff unit that cuts off a through current by cutting off the connection with the first or second P-type transistor , and the second voltage source is connected to the first voltage source when the input signal is stationary.
Or a resistor connected to the second node , wherein the current cutoff unit is provided between the second voltage source and the first P-type transistor.
It includes a third P-type Trang register disposed, and a fourth P-type transistor disposed between the second voltage source and the second P-type transistor, the resistor, the first Second voltage source and the first and third P-type transistors
A first resistor disposed between the connection point between the two resistors, the second voltage source, and the second and fourth P-type transistors.
A second resistor disposed between a connection point between the two resistors, the first resistor is a P-type transistor controlled by the potential of the second node, and the second resistor is , level Rushifuto circuit, characterized in that composed of P-type transistor controlled by a potential obtained by inverting the potential of said second node. 3. The resistance value of the resistor is set to a high resistance value so that a value of a current flowing from the second voltage source through its own resistance is substantially zero. The level shift circuit according to 1 or 2 . 4. The second-stage inverter is connected to the second node, and the gate capacitance of the next-stage inverter and the gate capacitance of the first P-type transistor are set when the potential of the second node drops. 3. The level shift circuit according to 1 or 2 above, wherein the level shift circuit is set to a small value so that the potential is reduced quickly. 5. The second and fourth P-type transistors are set to a large size so that the potential of the second node rises quickly when the potential of the second node rises. The level shift circuit according to 1 or 2 . 6. The level shift circuit according to claim 1 , wherein the level shift circuit has a function of fixing the second node to a predetermined potential when the first voltage source is shut down.