JP5015819B2 - Voltage conversion circuit - Google Patents

Description

  The present invention relates to a voltage conversion circuit that converts a voltage amplitude.

  In recent years, there has been a demand for higher integration, smaller size, higher speed, and lower power consumption in semiconductor devices. In particular, in LSIs (Large Scale Integrated Circuits), the internal power supply voltage has been lowered with the downsizing. There is a tendency to increase the difference from the voltage of the external power supply.

  Therefore, a voltage conversion circuit (level shifter) for voltage amplitude conversion is required at the interface portion between the outside and the inside, and at the interface portion between circuits having different power supply voltages inside the LSI.

  As an example of such a voltage conversion circuit, for example, the configuration shown in FIG. In this voltage conversion circuit, a high-speed voltage conversion operation and low power consumption can be realized, and it is possible to cope with a case where the voltage level of the input signal changes from a low speed to a high-speed change.

JP 2006-121654 A

  However, in the configuration of FIG. 1 of Patent Document 1, when the voltage level of the input signal is “L”, the potentials of the gate connection nodes of the two P-channel MOS transistors constituting the current mirror do not rise to the power supply potential. When the threshold voltages (Vth) of the two P-channel MOS transistors are shifted, there is a possibility that the mirror transistor is not completely turned off and a leak current flows.

  In order to quickly increase the potential of the gate connection node, it is necessary to increase the transistor size of the P-channel MOS transistor that constitutes the current mirror. If this is increased, the potential at the gate connection node is decreased. The transistor size of the N-channel type MOS transistor has to be increased, and there is a problem that it goes against the miniaturization of semiconductor devices.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a voltage conversion circuit capable of reducing leakage current and reducing power consumption and promoting the miniaturization of a semiconductor device. And

  In one embodiment of the present invention, the gate node of the second PMOS transistor serving as a current source is connected to the drain of the first PMOS transistor serving as a current source, and the gate of the first PMOS transistor is used as a reference. Since the first MOS transistor is always turned on by connecting the potential, when the input signal at the input terminal becomes the “L” level, the gate node of the second PMOS transistor that supplies current is supplied. A configuration for increasing the potential to the power supply potential is disclosed.

  According to the above embodiment, even if the threshold voltages of the first and second PMOS transistors are shifted by raising the potential of the gate node of the second PMOS transistor to the power supply potential, The PMOS transistor can be turned off, current leakage through the second PMOS transistor can be prevented, and low power consumption can be achieved.

<Comparative example>
Prior to the description of the embodiment of the invention, a voltage conversion circuit described in FIG. 1 of Patent Document 1 will be described as a comparative example.

First, the configuration of the voltage conversion circuit of Patent Document 1 will be described with reference to FIG.
In the voltage conversion circuit shown in FIG. 1, the “L” level (first logic level) is the reference potential VSS (0 V), and the “H” level (second logic level) is the power supply potential VDD (first power supply). An input signal whose potential is 1.5 V, for example, is an output whose “L” level is the reference potential VSS (0 V) and whose “H” level is the power supply potential VPP (second power supply potential: 5.0 V, for example). It is a voltage conversion circuit that converts a signal.

  In FIG. 1, a P-channel MOS transistor (PMOS transistor) P3 and N-channel MOS transistors (NMOS transistors) N6 and N7 are connected in series from the power supply potential VPP side to the power supply potential VPP and the reference potential VSS. In parallel with this, a PMOS transistor P4 and an NMOS transistor N8 are connected in series in order from the power supply potential VPP side. A connection node between the NMOS transistors N6 and N7 is referred to as a node ND3.

  The gates of the PMOS transistors P3 and P4 are commonly connected to the drain of the PMOS transistor P3. Note that the gate node of the PMOS transistor P4 is referred to as a node ND1.

  The gate of the NMOS transistor N7 is connected to the input terminal IN and is connected to the input terminal of the inverter IV9, and the output terminal of the inverter IV9 is connected to the gate of the NMOS transistor N8. The inverter IV9 is an inverter that sets the power supply potential VDD to the “H” level.

  A connection node (referred to as a node ND2) between the PMOS transistor P4 and the NMOS transistor N8 is an output node, and its output is given to the output terminal OUT via the inverters IV10 and IV11 connected in series and becomes an output signal. Inverters IV10 and IV11 are inverters that set power supply potential VPP to "H" level.

  A PMOS transistor P5 (sixth MOS transistor) is connected between the node ND2 and the power supply potential VPP, and its gate is connected to the input terminal of the inverter IV11 in common with the gate of the NMOS transistor N6. .

  In the voltage conversion circuit having such a configuration, when the signal (input signal) at the input terminal IN is at the “L” level, the NMOS transistor N7 is turned off and the node ND1 is charged by the PMOS transistor P3. Is turned on when the gate-source voltage Vgs is larger than the threshold voltage Vthp3 of the PMOS transistor P3 (| Vgs |> | Vthp3 |). Therefore, when the potential of the node ND1, that is, the gate voltage Vg of the PMOS transistor P3 rises to VPP− | Vthp3 |, | Vgs | = | Vthp3 | No longer.

  On the other hand, when the threshold voltage Vthp4 of the PMOS transistor P4 is smaller than Vthp3, the PMOS transistor P4 maintains the on state even in the above state.

  For example, when VPP = 5.0V, Vthp3 = −0.9V, and Vthp4 = −0.8V, the potential of the node ND1 rises to VPP− | Vthp3 | = 4.1V. At this time, the gate-source voltage Vgs of the PMOS transistor P4 becomes VPP−ND1 = 0.9V, and | Vgs | (0.9V)> | Vthp4 | (0.8V). Therefore, the PMOS transistor P4 is turned on. maintain.

  At this time, since the NMOS transistor N8 that has received the inversion level (“H” level) of the signal at the input terminal IN is on, current leakage occurs from the power supply potential VPP via the PMOS transistor P4.

Here, FIG. 2 shows a voltage waveform representing the time change of the potential of the node ND1 described above.
In FIG. 2, the vertical axis indicates voltage (arbitrary unit), the horizontal axis indicates time (arbitrary unit), the upper stage shows the time change of the signal potential of the input terminal IN and the output terminal OUT, and the lower stage shows the node ND1. And the time change of the electric potential of ND2 is shown.

  As shown in FIG. 2, when the input signal is at “L” level, the potential of the node ND1 does not reach the power supply potential VPP, and even after the input signal is switched to “H”, the potential of the node ND1 is It can be seen that the power supply potential VPP is not reached and the rate of increase in potential is slow.

<A. Embodiment 1>
Hereinafter, the voltage conversion circuit according to the first embodiment of the present invention will be described with reference to FIGS. 3 and 4.

<A-1. Device configuration>
FIG. 3 shows a configuration of the voltage conversion circuit 10 according to the first embodiment.
As shown in FIG. 3, in the voltage conversion circuit 10, the “L” level (first logic level) is the reference potential VSS (0 V), and the “H” level (second logic level) is the power supply potential VDD (first logic level). An input signal having a power supply potential of 1 (e.g., 1.5 V), an “L” level is a reference potential VSS (0 V), and an “H” level is a power supply potential VPP (second power supply potential: 5.0 V, for example). It is the voltage conversion circuit which converts into the output signal which is.

  In FIG. 3, a PMOS transistor P3 (first MOS transistor), NMOS transistors N6 and N7 (second and third MOS transistors) are connected in series from the power supply potential VPP side between the power supply potential VPP and the reference potential VSS. In parallel with this, a PMOS transistor P4 (fourth MOS transistor) and an NMOS transistor N8 (fifth MOS transistor) are connected in series in order from the power supply potential VPP side. A connection node between the NMOS transistors N6 and N7 is referred to as a node ND3.

  The gates of the PMOS transistors P3 and P4 are commonly connected to the drain of the PMOS transistor P3. Note that the gate node of the PMOS transistor P4 is referred to as a node ND1. The PMOS transistor P12 is connected between the node ND1 and the power supply potential VPP, and the gate of the PMOS transistor P12 is connected to the input terminal IN.

  The gate of the NMOS transistor N7 is connected to the input terminal IN and is connected to the input terminal of the inverter IV9, and the output terminal of the inverter IV9 is connected to the gate of the NMOS transistor N8. The inverter IV9 is an inverter that sets the power supply potential VDD to the “H” level.

  A connection node (referred to as a node ND2) between the PMOS transistor P4 and the NMOS transistor N8 is an output node, and its output is applied to the output terminal OUT via inverters IV10 and IV11 connected in series. Inverters IV10 and IV11 are inverters that set power supply potential VPP to "H" level.

  A PMOS transistor P5 is connected between the node ND2 and the power supply potential VPP, and its gate is connected to the input terminal of the inverter IV11 in common with the gate of the NMOS transistor N6.

<A-2. Device operation>
In the voltage conversion circuit 10, when the input signal of the input terminal IN becomes “L” level, the NMOS transistor N7 is turned off and the NMOS transistor N8 is turned on. However, the period when the potential of the node ND1 is lower than VPP− | Vthp3 | Since the PMOS transistor P3 is on, the node ND1 is charged by the PMOS transistor P3. However, since the PMOS transistor P12 to which the input signal is applied to the gate is also turned on, the potential rise at the node ND1 does not stop at VPP− | Vthp3 |, but rises to the power supply potential VPP.

  This is because the gate-source voltage Vgs of the PMOS transistor P12 is sufficiently larger than the threshold voltage Vthp12. For example, when VPP = 5.0V and Vthp12 = −0.8V, the gate-source voltage Vgs of the PMOS transistor P12 is VPP−IN = 5.0V−0V = 5.0V, and | Vgs |> | Since Vthp12 |, the node ND1 is charged until the source-drain voltage Vds of the PMOS transistor P12 becomes 0V. Note that Vds = 0V is when the potential of the node ND1 becomes the power supply potential VPP, and the potential of the node ND1 is charged to the power supply potential VPP.

  In this case, even if the threshold voltage Vthp4 of the PMOS transistor P4 is smaller than Vthp3, the PMOS transistor P4 is turned off.

  For example, when VPP = 5.0V, Vthp3 = −0.9V, and Vthp4 = −0.8V, the potential of the node ND1 rises to 5.0V. Therefore, the gate-source voltage Vgs of the PMOS transistor P4 is VPP. Since −ND1 = 0V and | Vgs | (0V) <| Vthp4 | (0.8V), the PMOS transistor P4 is turned off.

  Therefore, even if the NMOS transistor N8 is turned on, current leakage does not occur from the power supply potential VPP via the PMOS transistor P4.

FIG. 4 shows a voltage waveform representing the time change of the potential of the node ND1 described above.
In FIG. 4, the vertical axis represents voltage (arbitrary unit), the horizontal axis represents time (arbitrary unit), the upper stage shows the time change of the signal potential of the input terminal IN and the output terminal OUT, and the lower stage shows the node ND1. And the time change of the electric potential of ND2 is shown.

  As shown in FIG. 4, when the input signal is at “L” level, the potential of the node ND1 reaches the power supply potential VPP, and even after the input signal is switched to “H”, the potential of the node ND1 remains at the power supply potential VPP. It can be seen that the potential VPP is reached and the potential rise rate is fast. This is because the current flowing through the PMOS transistor P3 decreases as the potential of the node ND1 increases, but the PMOS transistor P12 does not enter such a state.

<A-3. Effect>
As described above, the voltage conversion circuit 10 includes the PMOS transistor P12 to increase the potential of the node ND1 to the power supply potential VPP when the input signal of the input terminal IN becomes “L” level. Even when the threshold voltages of the PMOS transistors P3 and P4 are shifted, the PMOS transistor P4 can be turned off, and current leakage through the PMOS transistor P4 can be prevented. For this reason, low power consumption can be achieved.

<A-4. Modification 1>
As a first modification of the first embodiment described above, FIG. 5 shows a configuration of a voltage conversion circuit 10A. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 10 shown in FIG. 3, and the overlapping description is abbreviate | omitted.

  In the voltage conversion circuit 10A, a PMOS transistor P6 is connected instead of the NMOS transistor N6 of the voltage conversion circuit 10, and its gate is connected to the output terminal of the inverter IV11. Also with this configuration, the same effect as that of the voltage conversion circuit 10 can be obtained.

<A-5. Modification 2>
As a second modification of the first embodiment described above, FIG. 6 shows a configuration of a voltage conversion circuit 10B. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 10 shown in FIG. 3, and the overlapping description is abbreviate | omitted.

  In the voltage conversion circuit 10B, a PMOS transistor P13 (eighth MOS transistor) is interposed between the source of the PMOS transistor P5 and the power supply potential VPP, and the gate thereof is connected to the output terminal of the inverter IV9. It has become.

  By adopting such a configuration, when the input signal changes from the “H” level to the “L” level, the current flowing from the PMOS transistor P5 to the node ND2 can be reduced, and the operation is further increased in speed and consumption. In addition to increasing the power, the transistor size of the NMOS transistor N8 can be reduced.

  That is, when the input signal changes from the “H” level to the “L” level, the NMOS transistor N8 is turned on and the charge of the node ND2 is extracted, but the PMOS transistor P5 is turned on. Although it is necessary to overcome the charging current from the PMOS transistor P5, since the power supply potential VDD lower than the power supply potential VPP is applied to the gate of the NMOS transistor N8, the driving capability is lower than that of the PMOS transistor P5. For this reason, it takes time to extract the charge of the node ND2, and in order to shorten the time, the transistor size of the NMOS transistor N8 must be increased.

  Here, the PMOS transistor P5 fixes the potential of the node ND2 to the “H” level (VPP) by turning on the PMOS transistor P5 when the input signal changes from the “L” level to the “H” level. Provided to stabilize the potential of the node ND2. Since the gate voltage Vg of the PMOS transistor P13 is given an inverted signal of the input signal, when the input signal is at the “L” level, the gate-source voltage Vgs becomes VPP−VDD, and the current flowing through the PMOS transistor P13 is reduced. As a result, the current flowing from the PMOS transistor P5 to the node ND2 can be reduced. For this reason, the charge of the node ND2 can be extracted in a relatively short time without increasing the transistor size of the NMOS transistor N8, and the operation speed is increased, the power consumption is reduced, and the transistor size of the NMOS transistor N8 is reduced. It becomes possible.

<A-6. Modification 3>
As a third modification of the first embodiment described above, FIG. 7 shows a configuration of a voltage conversion circuit 10C. In addition, the same code | symbol is attached | subjected about the structure same as the voltage converter circuits 10, 10A, and 10B shown in FIG.3, FIG5 and FIG.6, and the overlapping description is abbreviate | omitted.

  The voltage conversion circuit 10C has a configuration in which a PMOS transistor P6 is connected instead of the NMOS transistor N6 of the voltage conversion circuit 10 and the gate thereof is connected to the output terminal of the inverter IV11, the source of the PMOS transistor P5, and the power supply potential VPP. The configuration in which the PMOS transistor P13 is interposed between the two and the gate thereof is connected to the output terminal of the inverter IV9 is employed.

<B. Second Embodiment>
Next, the voltage conversion circuit according to the second embodiment of the present invention will be described with reference to FIG.

<B-1. Device configuration>
FIG. 8 shows the configuration of the voltage conversion circuit 20 of the second embodiment. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 10 shown in FIG. 3, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 8, the voltage conversion circuit 20 has a configuration in which the gate of the PMOS transistor P3 is connected to the reference potential VSS (0V) instead of connecting to the node ND1, and the node ND1 is connected to the drain of the PMOS transistor P3. It has become.

<B-2. Device operation>
In the voltage conversion circuit 20, since the reference potential VSS is always applied to the gate of the PMOS transistor P3, the PMOS transistor P3 is always on. Therefore, when the input signal of the input terminal IN becomes “L” level and the NMOS transistor N7 is turned off, the potential of the node ND1 rises to the power supply potential VPP.

  In this case, as described above, the PMOS transistor P4 is turned off even if the threshold voltage Vthp4 of the PMOS transistor P4 is smaller than Vthp3.

  Therefore, even if the NMOS transistor N8 is turned on, current leakage does not occur from the power supply potential VPP via the PMOS transistor P4.

<B-3. Effect>
As described above, in the voltage conversion circuit 20, by connecting the gate of the PMOS transistor P3 to the reference potential VSS, the potential of the node ND1 is changed when the input signal of the input terminal IN becomes “L” level. Even when the threshold voltages of the PMOS transistors P3 and P4 are shifted, the PMOS transistor P4 can be turned off to prevent current leakage through the PMOS transistor P4. be able to. For this reason, low power consumption can be achieved.

  Further, since only the gate of the PMOS transistor P3 is connected to the reference potential VSS, it is not necessary to add a new transistor or the like, and the device configuration can be prevented from becoming complicated.

  Even if the PMOS transistor P3 is always on, if the transistor sizes of the NMOS transistors N6 and N7 are made larger than the transistor size of the PMOS transistor P3 and larger than the current driving capability of the PMOS transistor P3, Since the potential of the node ND1 can be extracted and the potential can be lowered, there is no problem in turning on the PMOS transistor P4.

<B-4. Modification 1>
As a first modification of the second embodiment described above, FIG. 9 shows a configuration of a voltage conversion circuit 20A. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 20 shown in FIG. 8, and the overlapping description is abbreviate | omitted.

  In the voltage conversion circuit 20A, a PMOS transistor P6 is connected instead of the NMOS transistor N6 of the voltage conversion circuit 20, and its gate is connected to the output terminal of the inverter IV11. Also with this configuration, the same effect as that of the voltage conversion circuit 20 can be obtained.

<B-5. Modification 2>
As a second modification of the second embodiment described above, FIG. 10 shows a configuration of a voltage conversion circuit 20B. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 20 shown in FIG. 8, and the overlapping description is abbreviate | omitted.

  In the voltage conversion circuit 20B, the PMOS transistor P13 is interposed between the source of the PMOS transistor P5 and the power supply potential VPP, and the gate thereof is connected to the output terminal of the inverter IV9.

  By adopting such a configuration, when the input signal changes from the “H” level to the “L” level, the current flowing from the PMOS transistor P5 to the node ND2 can be reduced, and the operation is further increased in speed and consumption. In addition to increasing the power, the transistor size of the NMOS transistor N8 can be reduced.

<B-6. Modification 3>
As a third modification of the second embodiment described above, FIG. 11 shows a configuration of a voltage conversion circuit 20C. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuits 20, 20A, and 20B shown in FIG.8, FIG.9 and FIG.10, and the overlapping description is abbreviate | omitted.

  The voltage conversion circuit 20C has a configuration in which a PMOS transistor P6 is connected instead of the NMOS transistor N6 of the voltage conversion circuit 20, the gate thereof is connected to the output terminal of the inverter IV11, the source of the PMOS transistor P5, and the power supply potential VPP. The configuration in which the PMOS transistor P13 is interposed between the two and the gate thereof is connected to the output terminal of the inverter IV9 is employed.

  By adopting such a configuration, an effect similar to that of the voltage conversion circuit 20B can be obtained.

<C. Embodiment 3>
Next, the voltage conversion circuit according to the third embodiment of the present invention will be described with reference to FIG.

<C-1. Device configuration>
FIG. 12 shows the configuration of the voltage conversion circuit 30 according to the third embodiment. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 10 shown in FIG. 3, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 12, the voltage conversion circuit 30 has a configuration in which the gate of the PMOS transistor P3 is connected to the input terminal IN instead of being connected to the node ND1, and the node ND1 is connected to the drain of the PMOS transistor P3. .

<C-2. Device operation>
In the voltage conversion circuit 30, since the signal of the input terminal IN is given to the gate of the PMOS transistor P3, when the input signal of the input terminal IN becomes “L” level, the NMOS transistor N7 is turned off and the PMOS transistor P3 is turned on. It becomes. Therefore, the potential of the node ND1 rises to the power supply potential VPP.

  In this case, as described above, the PMOS transistor P4 is turned off even if the threshold voltage Vthp4 of the PMOS transistor P4 is smaller than Vthp3.

  Therefore, even if the NMOS transistor N8 is turned on, current leakage does not occur from the power supply potential VPP via the PMOS transistor P4.

<C-3. Effect>
As described above, in the voltage conversion circuit 30, when the input signal of the input terminal IN becomes “L” level, the potential of the node ND1 can be raised to the power supply potential VPP, and the PMOS transistors P3 and P4 Even when the threshold voltage is shifted, the PMOS transistor P4 can be turned off, and current leakage through the PMOS transistor P4 can be prevented. For this reason, low power consumption can be achieved.

  Further, since only the gate of the PMOS transistor P3 is connected to the input terminal IN, it is not necessary to add a new transistor or the like, and the device configuration can be prevented from becoming complicated.

  Further, since the current flowing from the PMOS transistor P3 to the node ND1 can be reduced when the input signal changes from the “L” level to the “H” level, the operation speed can be increased and the power consumption can be reduced, and the NMOS transistor N6. In addition, the increase in transistor size of N7 can be suppressed.

  That is, for example, when VPP = 5.0V and VDD = 1.5V, the gate-source voltage Vgs of the PMOS transistor P3 is 5.0V when the input signal is “L” level, and when it is “H” level. When the threshold voltage Vthp3 is −0.8 V, the PMOS transistor P3 is turned on regardless of whether the input signal is “L” or “H”.

  The operation when the input signal is at the “L” level is as described above. However, when the input signal changes from the “L” level to the “H” level, the NMOS transistor N7 is turned on and the charge at the node ND1 is used as a reference. Attempt to lower the potential by discharging to the potential VSS side, but the voltage Vgs between the gate and source of the PMOS transistor P3 at that time is 3.5 V, so that the PMOS transistor is compared with the case where the input signal is at the “L” level. The current that P3 flows is reduced. Therefore, the transistor sizes of the NMOS transistors N6 and N7 may be set in accordance with the current drive capability of the PMOS transistor P3 at that time, and the increase in size of the NMOS transistors N6 and N7 can be suppressed.

<C-4. Modification 1>
As a first modification of the third embodiment described above, FIG. 13 shows a configuration of a voltage conversion circuit 30A. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 30 shown in FIG. 12, and the overlapping description is abbreviate | omitted.

  In the voltage conversion circuit 30A, a PMOS transistor P6 is connected instead of the NMOS transistor N6 of the voltage conversion circuit 30, and the gate thereof is connected to the output terminal of the inverter IV11. Also with this configuration, the same effect as that of the voltage conversion circuit 30 can be obtained.

<C-5. Modification 2>
As a second modification of the third embodiment described above, FIG. 14 shows a configuration of a voltage conversion circuit 30B. Note that the same components as those of the voltage conversion circuit 30 shown in FIG. 13 are denoted by the same reference numerals, and redundant description is omitted.

  In the voltage conversion circuit 30B, the PMOS transistor P13 is interposed between the source of the PMOS transistor P5 and the power supply potential VPP, and the gate thereof is connected to the output terminal of the inverter IV9.

  By adopting such a configuration, when the input signal changes from the “H” level to the “L” level, the current flowing from the PMOS transistor P5 to the node ND2 can be reduced, and the operation is further increased in speed and consumption. In addition to increasing the power, the transistor size of the NMOS transistor N8 can be reduced.

<C-6. Modification 3>
As a third modification of the third embodiment described above, FIG. 15 shows a configuration of a voltage conversion circuit 30C. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuits 30, 30A, and 30B shown in FIG.12, FIG.13 and FIG.14, and the overlapping description is abbreviate | omitted.

  The voltage conversion circuit 30C has a configuration in which a PMOS transistor P6 is connected instead of the NMOS transistor N6 of the voltage conversion circuit 30, the gate thereof is connected to the output terminal of the inverter IV11, the source of the PMOS transistor P5, and the power supply potential VPP. The configuration in which the PMOS transistor P13 is interposed between the two and the gate thereof is connected to the output terminal of the inverter IV9 is employed.

  By adopting such a configuration, the same effect as that of the voltage conversion circuit 30B can be obtained.

<D. Embodiment 4>
Next, a voltage conversion circuit according to a fourth embodiment of the present invention will be described with reference to FIG.

<D-1. Device configuration>
FIG. 16 shows the configuration of the voltage conversion circuit 40 of the fourth embodiment. In addition, the same code | symbol is attached | subjected about the structure same as the voltage conversion circuit 30 shown in FIG. 12, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 16, in the voltage conversion circuit 40, a PMOS transistor P14 (seventh MOS transistor) is connected in parallel to the NMOS transistor N6, and its gate is connected to the node ND2.

<D-2. Device operation>
In the voltage conversion circuit 40, since the signal of the input terminal IN is given to the gate of the PMOS transistor P3, when the input signal of the input terminal IN becomes “L” level, the NMOS transistor N7 is turned off and the PMOS transistor P3 is turned on. It becomes. Therefore, the potential of the node ND1 rises to the power supply potential VPP.

  In this case, as described above, the PMOS transistor P4 is turned off even if the threshold voltage Vthp4 of the PMOS transistor P4 is smaller than Vthp3.

  Therefore, even if the NMOS transistor N8 is turned on, current leakage does not occur from the power supply potential VPP via the PMOS transistor P4.

  The NMOS transistor N6 is provided to prevent current leakage from the PMOS transistor P3 when the input signal changes from “L” level to “H” level, and becomes non-conductive. In the flash memory, the value of the power supply potential VPP may be switched and used. In this case, charges may be accumulated in the node ND3 between the NMOS transistors N6 and N7, resulting in a high voltage state. However, by connecting the PMOS transistor P14 in parallel to the NMOS transistor N6, a CMOS operation is performed, and charge accumulation can be prevented.

  That is, for example, in the voltage conversion circuit 30 shown in FIG. 12, when the power supply potential VPP is switched from 5 V to 10 V when the input signal is at “L” level, the potential of the node ND1 becomes 10 V. At this time, the NMOS transistor N6 is in an on state and the NMOS transistor N7 is in an off state.

  Since the NMOS transistor N6 is on, the potential of the node ND3 rises to a value obtained by subtracting the threshold voltage Vthn6 of the NMOS transistor N6 from the potential of the node ND1. For example, when Vthn6 = 0.8V, the potential of the node ND3 = ND1 potential−Vthn6 = 9.2V is reached.

  After that, when the power supply potential VPP returns to 5V, the potential of the node ND1 is lowered to 5V. At this time, the gate voltage Vg of the NMOS transistor N6 falls to the level (5V) of the power supply potential VPP, the gate-source voltage Vgs of the NMOS transistor N6 becomes 0V, and the source is on the node ND1 side. Here, since Vgs <Vthn6, the NMOS transistor N6 is turned off, and the potential 9.2V is held at the node ND3.

  Thereafter, when the input signal changes from the “L” level to the “H” level, the NMOS transistor N7 is turned on. However, since the potential of the node ND3 is 9.2V, 9.2V is applied between the source and the drain. As a result, the on-breakdown voltage of the NMOS transistor N7 may be exceeded (breakdown voltage violation), and a malfunction may occur in the NMOS transistor N7.

  However, by connecting the PMOS transistor P14 in parallel to the NMOS transistor N6, when the input signal is at "L" level, the node ND2 to which the gate of the PMOS transistor P14 is connected becomes 0V, and the PMOS transistor P14 is turned on. Therefore, when the power supply potential VPP changes from 5V to 10V in this state, the PMOS transistor P14 makes the potential of the node ND3 the same as that of the node ND1, so that the potential drops to 5V. Therefore, the node ND3 is prevented from entering a high voltage state, and a breakdown of the breakdown voltage is prevented from occurring in the subsequent switching operation.

  In addition, the voltage conversion circuits 30A and 30C shown in FIGS. 13 and 15 employ a configuration in which a PMOS transistor P6 is connected instead of the NMOS transistor N6, and its gate is connected to the output terminal of the inverter IV11. Also in this case, when the input signal is “L” level, the output of the inverter IV11 to which the gate of the PMOS transistor P6 is connected becomes 0V, and the gate-source voltage Vgs of the PMOS transistor P6 becomes the ND1 potential −0V. As a result, the PMOS transistor P6 is turned on, and the node ND3 is prevented from entering a high voltage state. The same applies to the voltage conversion circuits 10A, 10C, 20A, and 20C shown in FIGS. 5, 7, 9, and 11.

<D-3. Effect>
As described above, in the voltage conversion circuit 40, when the input signal of the input terminal IN becomes “L” level, the potential of the node ND1 can be increased to the power supply potential VPP, and the PMOS transistors P3 and P4 Even when the threshold voltage is shifted, the PMOS transistor P4 can be turned off, and current leakage through the PMOS transistor P4 can be prevented. For this reason, low power consumption can be achieved.

  Further, when applied to a flash memory or the like, even when the value of the power supply potential VPP is switched and used, electric charges are accumulated in the node ND3 between the NMOS transistors N6 and N7, and a high voltage state is prevented. In the subsequent switching operation, the breakdown of the breakdown voltage is prevented from occurring in the NMOS transistor N7.

It is a figure which shows the structure of the voltage converter circuit of the comparative example with respect to this invention. It is a signal waveform diagram explaining operation | movement of the voltage converter circuit of the comparative example with respect to this invention. It is a figure which shows the structure of the voltage converter circuit of Embodiment 1 which concerns on this invention. It is a signal waveform diagram explaining operation | movement of the voltage converter circuit of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 1 of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 2 of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 3 of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of Embodiment 2 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 1 of Embodiment 2 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 2 of Embodiment 2 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 3 of Embodiment 2 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of Embodiment 3 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 1 of Embodiment 3 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 2 of Embodiment 3 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of the modification 3 of Embodiment 3 which concerns on this invention. It is a figure which shows the structure of the voltage converter circuit of Embodiment 4 which concerns on this invention.

Explanation of symbols

  IN input terminal, OUT output terminal, ND1, ND2, ND3 nodes.

Claims (7)

An input signal in which the first logic level is the reference potential and the second logic level is the first power supply potential, the first logic level is the reference potential, and the second logic level is the second power supply. A voltage conversion circuit that converts an output signal that is a potential,
First, second, and third MOS transistors connected in series in order from the second power supply potential side between the second power supply potential and the reference potential;
Fourth and fifth MOS transistors connected in series in order from the second power supply potential side between the second power supply potential and the reference potential;
Connected to a second node, which is a connection node of the fourth and fifth MOS transistors, and turned on when the input signal changes from the first logic level to the second logic level; A sixth transistor for fixing the potential of the second node to the second power supply potential;
A first inverter having an input terminal connected to the gate of the third MOS transistor, an output terminal connected to the gate of the fifth MOS transistor, and driven by the first power supply potential;
A second inverter having an input terminal connected to the second node and driven by the second power supply potential;
An input terminal connected to the output terminal of the second inverter, and the output terminal comprises a third inverter driven by the second power supply potential serving as an output terminal for outputting the output signal;
The first, fourth, and sixth MOS transistors are of a first conductivity type, and the second, third, and fifth MOS transistors are of a second conductivity type,
A gate of the sixth transistor is connected to an output terminal of the second inverter;
An input terminal to which the input signal is input is connected to the input terminal of the first inverter,
A first node that is a gate of the fourth MOS transistor is connected to a drain of the first MOS transistor;
The gate of the first MOS transistor is supplied with a first signal that turns on the first MOS transistor when at least the input signal is at the first logic level.
A voltage conversion circuit, wherein a second signal for turning on the second MOS transistor when the input signal is at the first logic level is applied to a gate of the second MOS transistor. The first and second conductivity types are P-type and N-type, respectively.
The voltage conversion circuit according to claim 1, wherein a gate of the first MOS transistor is connected to the reference potential, and the first signal is a signal of the first logic level. The first and second conductivity types are P-type and N-type, respectively.
The voltage conversion circuit according to claim 1, wherein a gate of the first MOS transistor is connected to the input terminal, and the first signal is the input signal. The first and second conductivity types are P-type and N-type, respectively.
The second MOS transistor is of the second conductivity type,
A first conductivity type seventh MOS transistor connected in parallel to the second MOS transistor;
The gate of the second MOS transistor is connected to the output terminal of the second inverter, and the output of the second inverter is given as the second signal,
The voltage conversion circuit according to claim 1, wherein a gate of the seventh MOS transistor is connected to the input terminal of the second inverter. The first and second conductivity types are P-type and N-type, respectively.
The second MOS transistor is the first conductivity type,
4. The voltage conversion circuit according to claim 2, wherein a gate of the second MOS transistor is connected to the output terminal, and the output signal is supplied as the second signal. 5. The first and second conductivity types are P-type and N-type, respectively.
An eighth MOS transistor of the first conductivity type connected between the second power supply potential and the source of the sixth MOS transistor;
4. The voltage conversion circuit according to claim 2, wherein a gate of the eighth MOS transistor is connected to the output terminal of the first inverter. 5. The first and second conductivity types are P-type and N-type, respectively.
The second MOS transistor is the first conductivity type,
The gate of the second MOS transistor is connected to the output terminal, and the output signal is given as the second signal, and is connected between the second power supply potential and the source of the sixth MOS transistor. And further comprising an eighth MOS transistor of the first conductivity type,
4. The voltage conversion circuit according to claim 2, wherein a gate of the eighth MOS transistor is connected to the output terminal of the first inverter. 5.

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