JP4731333B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit, and more particularly to a level shift circuit that converts an amplitude level between two digital circuits having different voltage levels.

  When the power supply voltage inside the LSI is different from the power supply voltage outside the LSI, a level shift circuit (level shifter) that converts the amplitude level suitable for each voltage level is used to transmit a signal between the inside and the outside. It is done. For example, in the output buffer circuit, when the signal input from the inside is 1.2V and the signal output to the outside is 3.3V, a level shift circuit that converts the level from 1.2V to 3.3V is required. . In recent years, in the inter-chip communication, the speed of the interface circuit has been increased, such as high-speed serial transfer with a small number of signals, and the need for high-speed operation of the level shift circuit is also increasing.

  A level shift circuit corresponding to such high speed can be configured by using a differential pair (current mirror type differential amplifier) (for example, see Non-Patent Document 1) having a current mirror as a load.

  FIG. 7 shows a circuit example in which a Pch current mirror type differential amplifier circuit is used as a level shift circuit. This circuit includes an inverter circuit LINV that inverts an input signal IN, NMOS transistors HN1 and HN2 that are differential pairs, PMOS transistors HP1 and HP2 that are current mirror connected, and an NMOS transistor LN1 that is a current source. Here, the NMOS transistor HN1 and the NMOS transistor HN2 have the same size, and the PMOS transistor HP1 and the PMOS transistor HP2 have the same size.

  The input signal IN is supplied to the gate of the NMOS transistor HN1, is inverted by the inverter circuit LINV, and is supplied to the gate of the NMOS transistor HN2. The sources of the NMOS transistors HN1 and HN2 are connected to the drain of the NMOS transistor LN1, respectively. The NMOS transistor LN1 has a source grounded (GND) and a gate connected to the low voltage side power supply VDDL. The sources of the PMOS transistors HP1 and HP2 are connected to the high voltage side power supply VDDH. The gate and drain of the PMOS transistor HP1 are connected to the gate of the PMOS transistor HP2 and the drain of the NMOS transistor HN1. Further, the drain of the PMOS transistor HP2 and the drain of the NMOS transistor HN2 are connected to output an output signal OUT.

  In the level shift circuit configured as described above, when a difference potential is generated between signals input to the gates of the NMOS transistors HN1 and HN2, a difference occurs in currents flowing through the NMOS transistors HN1 and HN2. By converting this difference current into a voltage by a Pch current mirror as a load, a voltage having a large output amplitude can be obtained from a small input difference potential. That is, the level shift circuit can output a large level output signal OUT obtained by level conversion from a small level input signal IN.

  Incidentally, the level shift circuit shown in FIG. 7 consumes a large amount of current because the current always flows to the differential amplifier by the NMOS transistor LN1 serving as a current source.

  Thus, as a method for reducing current consumption, Patent Document 1 discloses a high-speed sampling receiver. This sampling receiver is configured to input a clock signal for sampling the data in addition to the data signal input for level conversion, and is devised to reduce current consumption during non-sampling.

  FIG. 9 shows a level shift circuit using a differential amplifier to which a sampling function using a clock signal is added. The circuit shown in FIG. 9 corresponds to a circuit in which the sampling receiver disclosed in Patent Document 1 is applied to a level shift circuit. This level shift circuit includes an inverter circuit LINV that inverts an input signal, an inverter circuit HINV that inverts a clock signal CLK, and a differential pair of PMOS transistors HP11, HP12, and Nch that form a differential pair of Pch constituting a differential amplifier. NMOS transistors HN11 and HN12, a PMOS transistor HP13 and an NMOS transistor HN13 for supplying / cutting off the current of the differential pair, and a latch circuit HLAT and an SR flip-flop circuit HSRFF for latching data in the differential amplifier when the current is cut off. Here, the NMOS transistors HN11 and HN12 have the same size, and the PMOS transistors HP11 and HP12 have the same size.

  The input signal IN is supplied to the gate of the NMOS transistor HN11 and the gate of the PMOS transistor HP11, further inverted by the inverter circuit LINV, and supplied to the gate of the NMOS transistor HN12 and the gate of the PMOS transistor HP12. The sources of the NMOS transistors HN11 and HN12 are connected to the drain of the NMOS transistor HN13. The source of the NMOS transistor HN13 is grounded (GND), and the clock signal CLK is supplied to the gate. The clock signal CLK is supplied to the common input of the latch circuit HLAT, inverted by the inverter circuit HINV, and supplied to the gate of the PMOS transistor HP13. The sources of the PMOS transistors HP11 and HP12 are connected to the drain of the PMOS transistor HP13. The source of the PMOS transistor HP13 is connected to the high voltage side power supply VDDH.

  The drain of the NMOS transistor HN11 and the drain of the PMOS transistor HP11 are connected to one output terminal (B1) of the latch circuit HLAT, and the drain of the NMOS transistor HN12 and the drain of the PMOS transistor HP12 are the other side of the latch circuit HLAT. Connected to the output terminal (A1). Further, one output terminal of the latch circuit HLAT is connected to one input terminal of the SR flip-flop circuit HSRFF, and the other output terminal of the latch circuit HLAT is connected to the other input terminal of the SR flip-flop circuit HSRFF. .

  The level shift circuit configured as described above cuts through current when the clock signal CLK is at a low level by the PMOS transistor HP13 and NMOS transistor HN13, which are through current cutoff transistors, and the differential output signal by the latch circuit HLAT. A1 and B1 are set to the high level (the level of the power supply VDDH) from the respective output states. The inputs of the SR flip-flop circuit HSRFF that receives the differential output signals A1 and B1 are both at a high level, and the previous state is maintained.

  When the clock signal CLK rises, the PMOS transistor HP13 and the NMOS transistor HN13 are turned on, and a current path flowing from the PMOS transistor HP11 to the NMOS transistor HN11 by the potential difference between the gate inputs of the differential pairs HP11, HP12, HN11, and HN12, and the PMOS A current difference is generated between the current path flowing from the transistor HP12 to the NMOS transistor HN12, and a difference potential is generated between the differential output signals A1 and B1 due to the difference current. This difference potential is further emphasized by the latch circuit HLAT. By these operations, the differential output signal A1 or B1 falls, and the fall is triggered to change the output signal OUT of the SR flip-flop circuit HSRFF.

JP 2003-78407 A Behzad Razavi, translated by Tadahiro Kuroda, Analog CMOS integrated circuit design basics, Maruzen Co., Ltd., published on March 30, 2003, p. 185

  In the level shift circuit shown in FIG. 7, when the signal level of the input signal IN is high (voltage value VDDL), the NMOS transistor HN1 is turned on, the NMOS transistor LN1 that is always on, and the PMOS transistor HP1 that is diode-connected. Thus, a through current is always generated from the high voltage side power supply VDDH to the GND. Therefore, a steady current is generated, and the power consumption increases by several orders of magnitude compared to a general CMOS circuit.

  FIG. 8 is a diagram showing the voltage waveform of the input signal IN, the voltage waveform of the output signal OUT, and the current waveform of the GND flowing in the GND of the entire circuit of the level shift circuit shown in FIG. As shown in FIG. 8, the current GND always flows when the input signal IN is at a high level.

  On the other hand, in the level shift circuit shown in FIG. 9, when the clock signal CLK is at a low level, the through current is blocked by the PMOS transistor HP13 and the NMOS transistor HN13. However, when the clock signal CLK is at a high level, the gate inputs of the PMOS transistors HP11 and HP12, which are Pch differential pairs, are pulled up only to the potential of the low-voltage power supply VDDL at the maximum, and neither of them is completely cut off. . For this reason, a through current from the high voltage side power supply VDDH to the GND is generated.

  For example, when the input signal IN is low level and the clock signal CLK is high level, the differential output A1 is low level and the differential output B1 is high level. At this time, the NMOS transistor HN11 is completely turned off, and the differential output B1 is pulled up to the potential of the high voltage side power supply VDDH by the latch circuit HLAT. For this reason, no current flows through the PMOS transistor HP11. On the contrary, the differential output A1 becomes low level by the latch circuit HLAT and the NMOS transistors HN12 and HN13. However, since the gate input of the PMOS transistor HP12 is the potential of the low voltage side power supply VDDL, it is not completely turned off. Therefore, the through current continues to flow from the PMOS transistor HP13 to the latch circuit HLAT and the NMOS transistor HN12 to the NMOS transistor HN13 via the PMOS transistor HP12.

  FIG. 10 is a diagram showing a voltage waveform of the input signal IN, a voltage waveform of the clock signal CLK, a voltage waveform of the output signal OUT, and a current waveform of GND flowing through the GND of the entire circuit of the level shift circuit shown in FIG. As shown in FIG. 10, the current GND always flows when the clock signal CLK is at a high level.

  Therefore, power consumption also increases in the level shift circuit shown in FIG. Note that the level shift circuit shown in FIG. 9 needs to receive the clock signal CLK, and is difficult to use for an asynchronous circuit in which no clock signal exists.

  The level shift circuit according to one aspect of the present invention includes a differential pair having a current mirror as a load, and the first level and the third level corresponding to the first level and the second level of the input signal, respectively. Output a level output signal from the non-inverted output terminal. The level shift circuit is connected to the non-inverting output terminal, and when the non-inverting output signal becomes the third level, the non-inverting output terminal is short-circuited with the power supply of the differential pair, and the input signal is the first. A first pull-up circuit that is open when the level is low, a current source circuit that is connected between the differential pair and ground, supplies an operating current to the differential pair, and a non-inverted output signal The current source circuit is configured to cut off the operating current to the differential pair after a predetermined time has elapsed since the level becomes 3, and to supply the operating current to the differential pair when the input signal is at the first level. A current source control circuit for controlling

  According to the present invention, power consumption can be reduced by employing a configuration that does not generate a steady current without using a clock signal.

  The level shift circuit according to the embodiment of the present invention includes a differential pair (HN1 and HN2 in FIG. 1) using a current mirror (HP1 and HP2 in FIG. 1) as a load, a pull-up circuit (HP3 and HINV1 in FIG. 1), A current source circuit (LN1 in FIG. 1) and a current source control circuit (HBUF, LNAND in FIG. 1) are provided. The differential pair outputs an output signal (FIG. 1) that becomes a high level (hereinafter referred to as a second high level) that is low level and level shifted corresponding to the low level and high level of the input signal (IN in FIG. 1), respectively. OUT) from the non-inverting output terminal. The pull-up circuit connected to the non-inverting output terminal operates when the non-inverting output signal becomes the second high level, pulls up the non-inverting output terminal, and the input signal is low level. It becomes open. A current source circuit connected between the differential pair and the ground, more specifically, a transistor (LN1 in FIG. 1) supplies an operating current to the differential pair. The current source control circuit cuts the operating current to the differential pair after a lapse of a predetermined time after the non-inverted output signal becomes the second high level, and to the differential pair when the input signal is at the low level. The current source circuit is controlled so as to supply the operating current.

  Since the level shift circuit having such a configuration is a current mirror type, it operates at high speed. In addition, in order to prevent steady current, which is a drawback of the conventional current mirror type level shift circuit, the gate terminal of the transistor, which is a current source circuit through which steady current flows, is controlled by the level of the input signal. The gate terminal is controlled by the input data signal itself for converting the level. That is, a new control signal or control mechanism is not required for controlling the gate terminal, and a large delay deterioration is not caused by switching the control signal. With such a configuration, no steady current is generated and low power consumption can be realized. Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a circuit diagram of a level shift circuit according to a first embodiment of the present invention. In FIG. 1, the same reference numerals as those in FIG. The level shift circuit shown in FIG. 1 is different from the level shift circuit shown in FIG. 7 in that it is a two-input NAND circuit LNAND that controls the gate voltage of the NMOS transistor LN1, and the output signal OUT is the level of the low voltage side power supply VDDL (not shown). In this configuration, a buffer circuit HBUF that converts the signal into a feedback signal, an inverter circuit HINV1 that latches the output signal OUT, and a PMOS transistor HP3 are added. Here, the inverter circuit LINV, the NAND circuit LNAND, and the NMOS transistor LN1 are low-breakdown-voltage elements or circuits that operate with the low-voltage power supply VDDL. Further, the buffer circuit HBUF is a high voltage circuit that operates with the low voltage side power supply VDDL. Further, the inverter circuit HINV1, the NMOS transistors HN1, HN2, and the PMOS transistors HP1 to HP3 are high breakdown voltage elements or circuits that operate with the high voltage side power supply VDDH.

  The buffer circuit HBUF converts the output signal OUT into a signal level of the low voltage side power supply VDDL and supplies it to one input terminal of the NAND circuit LNAND with a predetermined time delay. An input signal IN is supplied to the other input terminal of the NAND circuit LNAND, and the output terminal of the NAND circuit LNAND is connected to the gate of the NMOS transistor LN1.

  The inverter circuit HINV1 connects the drain of the PMOS transistor HP3 to the input terminal to give an output signal OUT, and connects the output terminal to the gate terminal of the PMOS transistor HP3. The PMOS transistor HP3 has a source connected to the high voltage side power supply VDDH and a drain connected to the drain of the NMOS transistor HN2 and the drain of the PMOS transistor HP3. The inverter circuit HINV1 and the PMOS transistor HP3 constitute a latch circuit for holding a high level when the output signal OUT becomes a high level. Here, the driving capability of the PMOS transistor HP3 is sufficiently small so as not to disturb the operation of the current mirror circuit itself.

  As shown in FIG. 1, a current path to GND in a differential pair having a current mirror circuit composed of PMOS transistors HP1 and HP2 and NMOS transistors HN1, HN2, and LN1 as a load always passes through the NMOS transistor LN1. Therefore, the configuration is such that a steady current is not generated by controlling the NMOS transistor LN1 by the operations of the NAND circuit LNAND and the buffer circuit HBUF.

  FIG. 2 is a state diagram showing the on / off state of the NMOS transistor LN1 corresponding to the level states of the input signal IN and the output signal OUT. When the input signal IN changes, that is, when the state of the input signal IN is different from that of the output signal OUT, the NMOS transistor LN1 is on, and the operation corresponds to a normal current mirror circuit.

  The NMOS transistor LN1 is also turned on when both the input signal IN and the output signal OUT are at a low level. However, since the input signal IN is at a low level, the NMOS transistor HN1 is turned off, the current path of the diode-connected PMOS transistor HP1 disappears, and the voltage at the point A becomes “VDDH−Vtp (Vtp is the threshold voltage of the PMOS transistor HP1). ) ”. Therefore, the PMOS transistor HP2 is also completely turned off.

  Even if the PMOS transistor HP3 is temporarily turned on, the driving capability of the PMOS transistor HP3 itself is set to be very weak compared to the PMOS transistor HP2, NMOS transistors HN2, and LN1. Therefore, when the PMOS transistor HP2 is turned off and the NMOS transistor HN2 and the NMOS transistor LN1 are turned on, the output signal OUT is always at a low level regardless of whether the PMOS transistor HP3 is turned on or off, and the PMOS transistor HP3 is finally completely turned off. Turn off. In this way, all current paths from the high-voltage power supply VDDH to GND in the current mirror are blocked. Therefore, no through current is generated when both the input signal IN and the output signal OUT are stationary at a low level.

  Only when both the input signal IN and the output signal OUT are at a high level, the gate potential of the NMOS transistor LN1 is lowered to the GND level and turned off. As in the case where the input signal IN and the output signal OUT are at the low level, the current path of the PMOS transistor HP1 disappears, the voltage at the point A becomes “VDDH−Vtp”, and the PMOS transistor HP2 is also completely turned off.

  FIG. 3 shows voltage waveforms of the input signal IN, the output signal OUT, the current mirror gate (point A), and the drain (point B) of the NMOS transistor LN1 during the circuit operation of FIG. The point A is “VDDH−Vtp” (in the vicinity of 2.8 V in FIG. 3) when the input signal IN is stationary at the low level or the high level. Point B indicates “VDDL−Vtn (Vtn is the threshold voltage of the NMOS transistor LN1)” when the input signal IN is at a low level and is stationary at a high level (FIG. 3). In the vicinity of 0.7V).

  In the above description, if the PMOS transistor HP3 does not exist, the output signal OUT is in a floating state, and the potential of the output signal OUT becomes an intermediate potential other than the high voltage side power supply VDDH or GND level. In this case, when a CMOS circuit that receives the output signal OUT is present outside, there is a possibility that a through current may be generated in the CMOS circuit. Therefore, the output signal OUT is pulled up to the potential of the high-voltage side power supply VDDH by the pull-up circuit composed of the inverter circuit HINV1 and the PMOS transistor HP3. As described above, since the current path from the high voltage side power supply VDDH to GND in the current mirror is completely cut off, even if both the input signal IN and the output signal OUT are stationary at a high level, the through current Does not occur.

  As described above, the level shift circuit shown in FIG. 1 has a circuit configuration in which no through current is generated regardless of the stationary state of the input signal IN.

  Next, the current waveform that actually flows will be described. FIG. 4 is a diagram showing the input signal IN, the output signal OUT, each voltage waveform at the gate (point C) of the NMOS transistor LN1, and the current waveform GND flowing in the GND of the entire circuit in the operation of the level shift circuit of FIG. It is. The NMOS transistor LN1 is turned on while the voltage at the point C is at the potential of the low voltage side power supply VDDL (1.2V in FIG. 4). However, as shown in FIG. 2, the input signal IN and the output signal OUT are high. The NMOS transistor LN1 is off, that is, the voltage at the point C is at the GND level only when the level is stationary. Further, when looking at the current GND, a current is generated when the input signal IN and the output signal OUT are switched. However, when the input signal IN is stationary at a low level or a high level, the current does not flow. Recognize.

  In the level shift circuit of the conventional example, when the current GND is viewed as shown in FIGS. 8 and 10, the current continues to flow in a part of the stationary state other than when the input signal is switched. On the other hand, it can be seen that the level shift circuit shown in FIG. 1 is improved in terms of current consumption because no current flows in a stationary state.

  As described above, the level shift circuit of the present invention is a current mirror type circuit, but has a configuration in which no steady current is generated. Therefore, the disadvantage of high power consumption in the conventional current mirror type circuit is solved.

  On the other hand, the loss of high speed, which is an advantage of the current mirror type, due to the circuit configuration that does not generate a steady current does not make sense for the current mirror type. There are two possible causes of delay degradation due to the circuit added in the level shift circuit shown in FIG. 1 compared to the conventional current mirror type circuit. The first is the influence of an increase in load on the output signal OUT portion by the PMOS transistor HP3. The second is the influence of the delay until the NMOS transistor LN1 is turned off in the initial state when the input signal IN falls, and it is turned on.

  First, the influence of the load increase due to the PMOS transistor HP3 will be described. When the input signal IN falls, the PMOS transistor HP3 is turned on in the initial state. For this reason, when the output signal OUT falls, the PMOS transistor HP3 works in the reverse direction, thereby hindering the operation of the current mirror. However, the PMOS transistor HP3 is for latching the high level when the output signal OUT becomes the high level, and not for switching the output signal OUT. Accordingly, the PMOS transistor HP3 has no problem as a sufficiently small driving capability with respect to the PMOS transistor HP2 and the NMOS transistors HN1 and LN1 that drive the output signal OUT. For this reason, it is possible to sufficiently reduce the delay increase due to the PMOS transistor HP3.

  Next, the influence of the delay until the NMOS transistor LN1 is turned on from off when the input signal IN falls will be described. Compared to the delay from when the input signal IN falls to when the NMOS transistor HN1 is turned on, the delay at which the NMOS transistor LN1 is turned on after the input signal IN falls and pulls the drain of the NMOS transistor LN1 to the GND level is more If it is larger, the delay from the input signal IN to the output signal OUT increases accordingly. However, the number of gate stages from the input signal IN to the NMOS transistor LN1 is such that the NAND circuit LNAND has only one stage, and the NMOS transistor LN1 only needs to have a breakdown voltage equal to or higher than the potential of the low voltage side power supply VDDL. Since the transistor LN1 has a small gate area and can use a high-speed transistor, an increase in delay due to the control of the NMOS transistor LN1 can be sufficiently reduced. However, it is necessary to use a transistor whose breakdown voltage is equal to or higher than the potential of the high-voltage power supply VDDH as the NMOS transistor HN1.

  As described above, according to the level shift circuit of the present embodiment, an unnecessary control signal or control mechanism is used as an original function of the level shifter to achieve both high-speed operation and low power consumption, which cannot be achieved by the conventional circuit configuration. Can be realized without any problem.

  FIG. 5 is a circuit diagram of a level shift circuit according to a second embodiment of the present invention. In FIG. 5, the same reference numerals as those in FIG. The level shift circuit shown in FIG. 5 has a configuration in which an inverter circuit HINV2, a PMOS transistor HP4, and a PMOS transistor LP1 with a low-voltage power supply VDDL as a source are added to the level shift circuit of FIG. Here, the PMOS transistor LP1 is a low breakdown voltage element that operates with the low voltage side power supply VDDL. The inverter circuit HINV2 and the PMOS transistor HP4 are high-breakdown-voltage elements or circuits that operate with the high-voltage power supply VDDH.

  The inverter circuit HINV2 has an input terminal connected to the drain (point A) of the PMOS transistor HP1, and an output terminal connected to the gate terminal of the PMOS transistor HP4. The PMOS transistor HP4 has a source connected to the high voltage side power supply VDDH and a drain connected to the drain of the NMOS transistor HN1 and the drain of the PMOS transistor HP1. The inverter circuit HINV2 and the PMOS transistor HP4 constitute a latch circuit for holding a high level when the potential at the point A becomes a high level. Here, it is assumed that the driving capability of the PMOS transistor HP4 is sufficiently small so as not to hinder the operation of the current mirror circuit itself, like the PMOS transistor HP3 described in the first embodiment.

  The PMOS transistor LP1 has a source connected to the low voltage side power supply VDDL, a drain connected to the drain of the NMOS transistor LN1, and a gate connected to the gate of the NMOS transistor LN1.

  FIG. 6 shows voltage waveforms of the input signal IN, the output signal OUT, the current mirror gate (point A), and the drain (point B) of the NMOS transistor LN1 during the circuit operation of FIG. The point A is “VDDH” (3.3 V in FIG. 6) when the input signal IN is stationary at a low level or a high level. Point B is “VDDL” (1.2 V in FIG. 6) when the input signal IN is at a low level and is at a low level, and when the input signal IN is at a high level.

  In the level shift circuit shown in FIG. 1, in a stable state, either the NMOS transistor HN1 or the NMOS transistor LN1 is always turned off, and the PMOS transistor HP1 is diode-connected. The potential at the point A corresponding to this is “VDDH−Vtp”. Since the PMOS transistor HP1 enters a high impedance state when the point A is in the vicinity of “VDDH−Vtp”, it takes a long time for the point A to completely converge to “VDDH−Vtp” after the input signal changes. Become.

  As shown in FIG. 5, by adding a pull-up circuit including an inverter circuit HINV2 and a PMOS transistor HP4 to the level shift circuit of FIG. 1, even if the PMOS transistor HP1 is in a high impedance state, the PMOS transistor HP4 can The potential can be raised to the high voltage side power supply VDDH. Therefore, it is possible to shorten the time until the potential at the point A converges.

  In the level shift circuit shown in FIG. 1, after the input signal rises, the PMOS transistor HP1 is diode-connected, the NMOS transistor HN1 is on, and the NMOS transistor LN1 is off. “VDDL−Vtn”. However, since the NMOS transistor HN1 is in a high impedance state in the vicinity of “VDDL−Vtn”, it takes a long time to completely converge.

  On the other hand, as shown in FIG. 5, by adding the PMOS transistor LP1, the potential at the point B can be raised to the potential of the power supply VDDL by the PMOS transistor LP1 even if the NMOS transistor HN1 is in a high impedance state. Therefore, it is possible to shorten the time until the potential at the point B converges.

  Further, even if the inverter circuit HINV2, the PMOS transistor HP4, and the PMOS transistor LP1 are added, a through current in a stationary state similar to that in FIG. 1 is not generated.

  Comparing the waveforms at points A and B in the waveform diagram shown in FIG. 6 and the waveform diagram shown in FIG. 3, the potential at point A is “VDDH−Vtp” after the output signal OUT rises in FIG. The waveform begins to round from around, and the potential continues to fluctuate even after 0.5 ns have elapsed from the change in the input signal IN. On the other hand, in FIG. 6, the level of the high voltage side power supply VDDH is stable when 0.5 ns elapses from the change of IN. Similarly, in FIG. 3, it takes time for the potential to stabilize from the vicinity of “VDDL−Vtn” in FIG. On the other hand, in FIG. 6, the level is stabilized at the low voltage side power supply VDDL after 0.5 ns.

  By the functions of the inverter circuit HINV2, the PMOS transistor HP4, and the PMOS transistor LP1 added in FIG. 5, it is possible to shorten the time until the voltages at the points A and B converge when the input signal changes. In the time until convergence, the signal delay varies depending on whether the pulse width of the input signal is small or large, because the initial values of the voltage at point A and point B when the input signal changes are different. The difference in delay depending on the frequency of the input signal leads to an increase in jitter when a random data signal is input. Therefore, by suppressing the convergence time, it is possible to suppress an increase in jitter and to operate at a higher frequency.

  Further, the level shift circuit shown in FIG. 5 operates so as to cut off the charging / discharging current at the points A and B at a high speed, so that it is possible to further reduce the power consumption by the interruption.

  The present invention has been described with reference to the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and those skilled in the art within the scope of the invention of each claim of the present application claims. It goes without saying that various modifications and corrections that can be made are included.

1 is a circuit diagram of a level shift circuit according to a first exemplary embodiment of the present invention. It is a table | surface showing the input / output level state of the level shift circuit based on 1st Example of this invention. It is a figure which shows the voltage waveform of each part of the level shift circuit which concerns on 1st Example of this invention. It is a wave form diagram which shows the voltage-current characteristic of the level shift circuit which concerns on 1st Example of this invention. FIG. 6 is a circuit diagram of a level shift circuit according to a second example of the present invention. It is a figure which shows the voltage waveform of each part of the level shift circuit which concerns on the 2nd Example of this invention. It is a circuit diagram of a conventional level shift circuit. It is a wave form diagram which shows the voltage-current characteristic of the conventional level shift circuit. It is a circuit diagram of another conventional level shift circuit. It is a wave form diagram which shows the voltage-current characteristic of the other conventional level shift circuit.

Explanation of symbols

HBUF Buffer circuit HINV1, HINV2, LINV Inverter circuits HN1, HN2, LN1 NMOS transistors HP1 to HP4, LP1 PMOS transistor LNAND NAND circuit VDDH High voltage side power supply VDDL Low voltage side power supply

Claims (6)

A differential pair having a current mirror as a load is included, and output signals having a first level and a third level corresponding to the first level and the second level of the input signal are output from the non-inverting output terminal. A level shift circuit,
The non-inverted output terminal is connected to the non-inverted output terminal, and when the non-inverted output signal becomes a third level, the non-inverted output terminal is short-circuited with the power source of the differential pair, and the input signal is at the first level. A first pull-up circuit that is open if
A current source circuit connected between the differential pair and ground and supplying an operating current to the differential pair;
When a predetermined time elapses after the non-inverted output signal becomes the third level, the operating current to the differential pair is cut off, and when the input signal is at the first level, the differential pair is supplied to the differential pair. A current source control circuit for controlling the current source circuit to supply an operating current;
A level shift circuit comprising:   2. A high power supply voltage is supplied to the differential pair and the first pull-up circuit, and a low power supply voltage is supplied to the current source circuit and the current source control circuit. The level shift circuit described.   The current source circuit includes a first conductivity type MOS transistor having a drain connected to the differential pair, a source grounded, and a gate connected to an output of the current source control circuit. The level shift circuit according to claim 2.   The current source circuit has a drain connected to the drain of the first conductivity type MOS transistor, a source supplied with the low power supply voltage, and a gate connected to the gate of the first conductivity type MOS transistor. 4. The level shift circuit according to claim 3, further comprising a conductive MOS transistor. The inverting output terminal is connected to the inverting output terminal of the differential pair, and when the inverting output terminal reaches a third level, the inverting output terminal is short-circuited to the power source of the differential pair, and the input signal is A second pull-up circuit that is open when the level is reached;
The level shift circuit according to claim 2, wherein the high power supply voltage is supplied to the second pull-up circuit.   A semiconductor integrated circuit device comprising the level shift circuit according to claim 1.

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