JPH07226670A - Cmos level shift circuit - Google Patents

Cmos level shift circuit

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Publication number
JPH07226670A
JPH07226670A JP6017146A JP1714694A JPH07226670A JP H07226670 A JPH07226670 A JP H07226670A JP 6017146 A JP6017146 A JP 6017146A JP 1714694 A JP1714694 A JP 1714694A JP H07226670 A JPH07226670 A JP H07226670A
Authority
JP
Japan
Prior art keywords
terminal
transistor
polarity
type mos
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6017146A
Other languages
Japanese (ja)
Inventor
Masahiro Gion
Jiro Miyake
Kazuki Ninomiya
Maki Toyokura
Norio Uchiumi
二郎 三宅
和貴 二宮
則夫 内海
雅弘 祇園
真木 豊蔵
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, 松下電器産業株式会社 filed Critical Matsushita Electric Ind Co Ltd
Priority to JP6017146A priority Critical patent/JPH07226670A/en
Publication of JPH07226670A publication Critical patent/JPH07226670A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To perform the low power consumption of a circuit by preventing through current from flowing in a CMOS level shift circuit. CONSTITUTION:First and second N type MOS transistors 14 and 15 are serially connected between power source voltage and ground. The signal inputted from an external input terminal 11 is transmitted to the gate of a second N type MOS transistor 15 via a first inverter 12 and is transmitted to the gate of the first N type MOS transistor 14 via the first and second inverters 12 and 13. Each drain of the first and second N type MOS transistors 14 and 15 is connected with the a high output positive feedback circuit composed of a third inverter and a P type MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS level shift circuit.

[0002]

2. Description of the Related Art A conventional CMOS level shift circuit will be described below with reference to FIGS.

The CMOS level shift circuit shown in FIG.
A P-type MOS transistor 51 is connected between the high voltage power supply and ground.
And an N-type MOS transistor 52 are connected in series, and a P-type MOS transistor 51 and an N-type MOS transistor 52 are connected.
This is a circuit in which the threshold voltage is lowered by changing the ratio of the transistor size of and.

By doing so, even if a low-voltage input signal is applied to the external input terminal 11, the high-voltage inverter composed of the P-type MOS transistor 51 and the N-type MOS transistor 52 operates, The output of the inverter drives the high-voltage operating inverter 53, and the output signal level-shifted to the high voltage is output to the external output terminal 18
Taken out. As described above, the circuit shown in FIG. 5 can form a CMOS level shift circuit with a small number of elements.

The circuit shown in FIG. 6 is a CMO having a differential amplifier configuration.
It is an S level shift circuit. In this circuit, two signals whose phases are mutually inverted from the two-stage inverters 61 and 62 operating at low voltage are applied to the gates of the first and second N-type MOS transistors 65 and 66 operating at high voltage. Each has been entered. Since the transistor sizes of the first and second N-type MOS transistors 65 and 66 are about twice as large as the transistor sizes of the first and second P-type MOS transistors 63 and 64, the threshold voltage is (1 / 2) · VDD (high voltage) lower than the first and second N-type MOS transistors 65, 6
One of 6 is in a conducting state and the other is in a non-conducting state. As a result, the first and second P-type MOS transistors 6
Of the three and 64, the P-type MOS whose gate is connected to the drain of the N-type MOS transistor in the conductive state
The transistor becomes conductive, and the other P-type MOS
Since the gate input level of the transistor becomes VDD (high voltage), the other P-type MOS transistor is surely turned off. Then, the high-voltage driven inverter 67 at the next stage operates, and the output signal level-shifted to the high voltage is taken out from the external output terminal 18. As shown in FIG.
In the CMOS level shift circuit shown in FIG.
The input level to the gates of the S transistors 63 and 64 is V
DD (high voltage), P-type MOS transistor 63,
Since one of the 64's is certainly brought into the non-conducting state, the problem that the through current always flows does not substantially occur.

[0006]

In the conventional circuit shown in FIG. 5, a CMOS level shift circuit can be constructed with a small number of elements, but the P-type MOS transistor 51 and the N-type MOS transistor 52 are connected to each other. Since a through current always flows through the device, power consumption increases.

On the other hand, in the conventional CMOS level shift circuit shown in FIG. 6, the problem that the through current always flows does not occur, but the input signal is HIGH → LOW, LOW → HIGH.
A through current flows when it changes. Therefore, as the operating frequency increases, the amount of through current increases and power consumption increases.

As described above, the conventional CMOS level shift circuit has a problem of high power consumption.

In view of the above problems, it is an object of the present invention to provide a CMOS level shift circuit which consumes less power.

[0010]

In order to achieve the above object, the invention of claim 1 provides a CMOS level shift circuit,
A first transistor of a first polarity having a source terminal connected to a high voltage source and a drain terminal connected to an external output terminal; a source terminal connected to a ground voltage source and a drain terminal connected to the external output terminal A second transistor having a first polarity, an input terminal connected to an external input terminal and an output terminal connected to a gate terminal of the second transistor having the first polarity, and an input terminal A second inverter connected to the output terminal of the first inverter, the output terminal of which is connected to the gate terminal of the first transistor of the first polarity; and a source terminal of which is connected to the high-voltage voltage source and a drain terminal Is a transistor of the second polarity connected to the drain terminal of the first transistor of the first polarity and the drain terminal of the second transistor of the first polarity And a positive feedback circuit configured to output a high potential signal, the second inverter having a child connected to the external output terminal and an output terminal connected to the gate terminal of the transistor of the second polarity. To do.

According to a second aspect of the present invention, there is provided a CMOS level shift circuit in which a source terminal is connected to a high voltage source and a drain terminal is connected to an external output terminal. A second transistor having a first polarity connected to a ground voltage source and having a drain terminal connected to the external output terminal; and a second transistor having an input terminal connected to an external input terminal and an output terminal having the first polarity A first inverter connected to the gate terminal of the first inverter, and a second inverter having an input terminal connected to the output terminal of the first inverter and an output terminal connected to the gate terminal of the first transistor of the first polarity. An inverter, a first transistor having a second polarity whose source terminal is connected to the high voltage source, and a source terminal connected to the drain terminal of the first transistor having the second polarity. A drain terminal connected to a drain terminal of the first transistor having the first polarity and a drain terminal of the second transistor having the first polarity, and a gate terminal connected to an output terminal of the first inverter. A high potential signal including a second transistor having a polarity of 2 and a second inverter having an input terminal connected to the external output terminal and an output terminal connected to a gate terminal of the first transistor having the second polarity. And a positive feedback circuit for outputting.

According to a third aspect of the present invention, there is provided a CMOS level shift circuit, wherein a source terminal has a first transistor having a first polarity connected to a high voltage source, and a source terminal has a first polarity having the first polarity. A first transistor having a second polarity connected to the drain terminal of the transistor and having a drain terminal connected to the external output terminal; and a first transistor having a source terminal connected to the ground voltage source and a drain terminal connected to the external output terminal. And a second transistor having a polarity of 1, and an input terminal connected to an external input terminal, and an output terminal connected to a gate terminal of the first transistor of the second polarity and a gate terminal of the second transistor of the first polarity. And the input terminal is connected to the output terminal of the first inverter and the output terminal is connected to the gate terminal of the first transistor of the first polarity. And a drain terminal connected to the drain terminal of the first transistor having the second polarity and the drain terminal of the second transistor having the first polarity. A second transistor having a second polarity and an input terminal connected to the external output terminal and a second inverter having an output terminal connected to the gate terminal of the second transistor having the second polarity, and having a high potential. And a positive feedback circuit for outputting a signal.

According to a fourth aspect of the present invention, there is provided a CMOS level shift circuit, wherein a source terminal has a first transistor having a first polarity connected to a high voltage source and a source terminal has a first polarity having the first polarity. A first transistor having a second polarity connected to the drain terminal of the transistor and having a drain terminal connected to the external output terminal; and a first transistor having a source terminal connected to the ground voltage source and a drain terminal connected to the external output terminal. And a second transistor having a polarity of 1, and an input terminal connected to an external input terminal, and an output terminal connected to a gate terminal of the first transistor of the second polarity and a gate terminal of the second transistor of the first polarity. And the input terminal is connected to the output terminal of the first inverter and the output terminal is connected to the gate terminal of the first transistor of the first polarity. A second inverter and a source terminal connected to the high voltage source and a drain terminal connected to the drain terminal of the first transistor of the first polarity and the source terminal of the first transistor of the second polarity. A second transistor having a second polarity and an input terminal connected to the external output terminal and a second inverter having an output terminal connected to the gate terminal of the second transistor having the second polarity, and having a high potential. And a positive feedback circuit for outputting a signal.

[0014]

According to the present invention, the input signal is input to the first transistor of the first polarity through the first inverter and the second inverter, and the second transistor of the first polarity is input. Since an input signal is input to the transistor of the first inverter through the first inverter, the first and second transistors having the first polarity are provided.
Since one of the transistors is always in a non-conducting state, a through current does not flow in the first and second transistors of the first polarity in the steady state.

Further, according to the first to fourth aspects, in the transient state in which the input signal changes from LOW to HIGH, the first transistor of the first polarity passes the input signal through the first and second inverters. Of the first polarity, the first transistor of the first polarity becomes conductive with a slight delay from the timing when the second transistor of the first polarity becomes non-conductive. No through current flows through the first transistor and the second transistor of the first polarity. In addition, the second-polarity transistor (or the second-polarity first transistor) is turned on after the first-polarity first transistor is turned on.
Through current does not flow in the transistor of the polarity (or the first transistor of the second polarity) and the second transistor of the first polarity.

According to the structure of claim 2, the input signal is HIG.
In the transient state of changing from H to LOW, the input signal is applied to the second transistor of the second polarity at the same timing as the second transistor of the first polarity.
The impedance of the second transistor of the second polarity changes when the second transistor of the first polarity conducts. For this reason, the shoot-through current flowing through the first transistor of the second polarity and the second transistor of the first polarity in the transient state in which the input signal changes from HIGH to LOW is suppressed.

According to the structure of claim 3, the input signal is HIG.
In the transient state of changing from H to LOW, the input signal is applied to the second transistor of the second polarity at the same timing as the second transistor of the first polarity.
The impedance of the second transistor of the second polarity changes when the second transistor of the first polarity conducts. Therefore, the shoot-through current flowing through the first transistor of the first polarity and the second transistor of the first polarity in the transient state in which the input signal changes from HIGH to LOW is suppressed.

According to the structure of claim 4, the input signal is HIG.
In the transient state of changing from H to LOW, the input signal is given to the first transistor of the second polarity at the same timing as the second transistor of the first polarity,
The impedance of the first transistor of the second polarity changes at the timing when the second transistor of the first polarity becomes conductive. Therefore, in the transient state in which the input signal changes from HIGH to LOW, the shoot-through current flowing through the first transistor of the first polarity and the second transistor of the first polarity and the second transistor of the second polarity and the second transistor of the second polarity. The through current flowing through the second transistor having the polarity of 1 is suppressed.

[0019]

Embodiments of the CMOS level shift circuit according to the present invention will be described below.

FIG. 1 shows a CMO according to the first embodiment of the present invention.
This is an S level shift circuit. In this CMOS level shift circuit, a low voltage signal is given from an external input terminal 11 and a level-shifted high voltage signal is taken out from an external output terminal 18. In FIG. 1, reference numeral 12 denotes the first low voltage operation.
Inverter, 13 is a low voltage second inverter,
14 is a first N-type MOS transistor operating at high voltage, 1
5 is a second N-type MOS transistor operating at high voltage, 16
Is a P-type MOS transistor operating at high voltage, and 17 is a third inverter operating at high voltage.

The operation of the CMOS level shift circuit according to the first embodiment will be described below. In the following description, the HIGH level of the low voltage is H1, the HIGH level of the high voltage is H2, the ground level is L, and the threshold voltage of the first N-type MOS transistor 14 is VT.

First, the operation in the steady state will be described. The low voltage signal given from the external input terminal 11 is
Two signals, which are transmitted through the first and second inverters 12 and 13 and have mutually inverted phases, are first and second N-type MOSs.
It is applied to the gates of the transistors 14 and 15, respectively. Since the potential of either one of the two signals with inverted phases is L, the first and second N-type MOS
One of the transistors 14 and 15 is completely non-conductive. Therefore, in the steady state, no through current flows,
Low power consumption can be achieved.

When the low voltage signal supplied from the external input terminal 11 is L, the potential supplied to the gate of the first N-type MOS transistor 14 becomes L, and the first N-type MOS transistor 14 is supplied with the potential.
The transistor 14 is completely non-conductive. At this time, since the second N-type MOS transistor 15 is conducting, the potential of the external output terminal 18 becomes L. Then, the third inverter 17 to which the potential L is input outputs H2, and the P-type MOS transistor 16 to which the output H2 from the third inverter 17 is input becomes completely non-conductive, so that the external output terminal The potential L of 18 is kept stable.

On the other hand, when the low voltage signal given from the external input terminal 11 is H1, the potential given to the gate of the second N-type MOS transistor 15 becomes L, and the second N-type MOS transistor 15 is completely turned on. It becomes non-conductive. At this time, since the first N-type MOS transistor 14 is conducting, the potential of the external output terminal 18 becomes H1-VT. Then, the third inverter 17 to which the potential H1-VT is input outputs L, and the P-type MOS transistor 16 to which the output L from the third inverter 17 is input becomes completely conductive, so that the external output The potential of the terminal 18 is H1-
Boosted from VT to H2. As described above, the positive output circuit of the HIGH output composed of the third inverter 17 and the P-type MOS transistor 16 allows the external output terminal 1
The potential of 8 is kept stable at H2. However, the threshold voltage of the third inverter 17 is set lower than H1-VT.

Next, the operation in the transient state in which the signal changes from HIGH to LOW will be described. When the signal input from the external input terminal 11 is H1, as can be seen from the above description, the second N-type MOS transistor 15 is in a non-conducting state, the first N-type MOS transistor 14 is in a conducting state, and P The type MOS transistor 16 is in a conductive state. In this state, the potential of the external input terminal 11 is H1.
Changes from L to L, the second N-type MOS transistor 1
5 becomes conductive by receiving a change in the input signal via the first inverter 12. The first N-type MOS transistor 14 includes a first inverter 12 and a second inverter 1
Since the input signal is changed via the signal line 3, the state changes a little later than the second N-type MOS transistor 15 and becomes the non-conductive state. The P-type MOS transistor 16 is the second
After the N-type MOS transistor 15 has become conductive, it becomes non-conductive.

As can be seen from the above description, while the potential of the external input terminal 11 changes from H1 to L, it is between the first N-type MOS transistor 14 and the second N-type MOS transistor 15 and P. Type MOS transistor 16 and second
A through current flows between the N-type MOS transistor 15 and the N-type MOS transistor 15.

Next, the operation in the transient state in which the signal changes from LOW to HIGH will be described. When the external input terminal 11 is at L, the second N-type MOS transistor 15 becomes conductive and the first N-type MO transistor 15 becomes conductive, as can be seen from the above description.
The S transistor 14 and the P-type MOS transistor 16 are off. In this state, when the potential of the external input terminal 11 changes from L to H1, the second N-type MOS transistor 15 receives the change of the input signal via the first inverter 12 and becomes non-conductive. Since the first N-type MOS transistor 14 receives a change in the input signal via the first inverter 12 and the second inverter 13, the state changes and the state of conduction becomes slightly later than that of the second N-type MOS transistor 15. It becomes a state. The P-type MOS transistor 16 becomes conductive after the first N-type MOS transistor 14 becomes conductive.

As can be seen from the above description, while the potential of the external input terminal 11 changes from L to H1, the potential between the first N-type MOS transistor 14 and the second N-type MOS transistor 15 and P is increased. Type MOS transistor 16 and second
No through current flows between the N-type MOS transistor 15 and the N-type MOS transistor 15.

FIG. 2 shows a CMOS according to the second embodiment of the present invention.
It is a level shift circuit. This circuit is an example in which the positive feedback circuit for HIGH output in the CMOS level shift circuit according to the first embodiment is improved. The difference from the first embodiment is that another P-type MOS transistor 21 for high voltage operation is added.

As a result, in the transient state in which the signal input to the external input terminal 11 changes from HIGH to LOW, the second N-type MOS transistor 15 and other P-type M-type transistors are provided.
When an input signal is applied to the OS transistor 21 almost at the same time and the second N-type MOS transistor 15 becomes conductive, the impedance of the other P-type MOS transistor 21 changes at the same time, and the second N-type MOS transistor 15 and A through current flowing between the P-type MOS transistor 16 and the P-type MOS transistor 16 can be reduced.

FIG. 3 shows a CMOS according to the third embodiment of the present invention.
It is a level shift circuit. The difference from the first embodiment of this circuit is that a high-voltage operating P-type MOS transistor 31 is connected between the drain of the first N-type MOS transistor 14 and the drain of the second N-type MOS transistor 15. ,
The point is that the output of the first inverter 12 is connected to the gate of the low-voltage operating P-type MOS transistor 31.

As a result, in a transient state in which the signal input to the external input terminal 11 changes from HIGH to LOW, the input signals are input to the second N-type MOS transistor 15 and the high-voltage operating P-type MOS transistor 31 almost at the same time. Almost at the same time when the second N-type MOS transistor 15 is rendered conductive, the impedance of the high-voltage operating P-type MOS transistor 31 changes, and the second N-type MO transistor 15 changes its impedance.
S transistor 15 and first N-type MOS transistor 1
It is possible to reduce the through current flowing between the first and second electrodes.

FIG. 4 shows a CMOS according to the fourth embodiment of the present invention.
It is a level shift circuit. This circuit is an improved example of the third embodiment. The difference from the third embodiment is that the first P-type M
The drain of the OS transistor 16 is connected to the drain of the first N-type MOS transistor 14.

As a result, in the transient state in which the signal changes from HIGH to LOW, the input signals are applied to the second N-type MOS transistor 15 and the P-type MOS transistor 31 operating at high voltage almost at the same time, and the second N-type MOS transistor 15 and the P-type MOS transistor 31 are operated. Almost at the same time that the type MOS transistor 15 becomes conductive, the impedance of the P-type MOS transistor 31 operating at high voltage changes, and the P-type MOS transistor 31 between the first N-type MOS transistor 14 and the second N-type MOS transistor 15 and P It is possible to reduce the through current flowing between the type MOS transistor 16 and the second N-type MOS transistor 15.

[0035]

According to the CMOS level shift circuit of the present invention, in the steady state, one of the first and second transistors of the first polarity is always non-conductive. It is possible to avoid a situation in which a through current flows through the first transistor of the first polarity and the second transistor of the first polarity.

The CMOS according to the inventions of claims 1 to 4
According to the level shift circuit, the input signal changes from LOW to HI.
In the transient state of changing to GH, a situation in which a through current flows through the first transistor of the first polarity and the second transistor of the first polarity and the transistor of the second polarity (or the first transistor of the second polarity). It is possible to avoid a situation in which a through current flows through the transistor) and the second transistor having the first polarity.

Particularly, according to the CMOS level shift circuit of the second aspect of the present invention, the input signal changes from HIGH to LOW.
It is also possible to suppress the shoot-through current flowing in the first transistor of the second polarity and the second transistor of the first polarity in the transient state that changes to.

According to the CMOS level shift circuit of the third aspect of the present invention, the input signal changes from HIGH to LOW.
It is possible to suppress a through current flowing through the first transistor of the first polarity and the second transistor of the first polarity in the transient state of changing to.

Further, according to the CMOS level shift circuit of the invention of claim 4, the input signal is changed from HIGH to LO.
Through current flowing through the first transistor of the first polarity and the second transistor of the first polarity and the first transistor of the second polarity and the second transistor of the first polarity in the transient state changing to W It is possible to suppress the penetrating current flowing through.

Therefore, the CM according to the inventions of claims 1 to 4
According to the OS level shift circuit, it is possible to reduce the power consumption of the circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a CMOS level shift circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a CMOS level shift circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a CMOS level shift circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a CMOS level shift circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional CMOS level shift circuit.

FIG. 6 is a circuit diagram of another conventional CMOS level shift circuit.

[Explanation of symbols]

 11 external input terminal 12 first inverter of low voltage operation 13 second inverter of low voltage operation 14 first N-type MOS transistor of high voltage operation 15 second N-type MOS transistor of high voltage operation 16 high voltage operation P-type MOS transistor 17 High-voltage operating third inverter 18 External output terminal 21 High-voltage operating other P-type MOS transistor 31 High-voltage operating P-type MOS transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Maki Toyokura 1006 Kadoma, Kadoma City, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. (72) Norio Utsumi, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims]
1. A first transistor of a first polarity whose source terminal is connected to a high voltage source and whose drain terminal is connected to an external output terminal; and a source terminal which is connected to a ground voltage source and whose drain terminal is the external terminal. A second transistor having a first polarity connected to the output terminal, an input terminal connected to the external input terminal, and an output terminal connected to the first transistor
A first inverter connected to the gate terminal of the second transistor having the polarity, and an input terminal connected to the output terminal of the first inverter, and the output terminal having the gate terminal of the first transistor having the first polarity. And a drain terminal of the first transistor of the first polarity and a drain terminal of the second transistor of the first polarity, the source terminal of which is connected to the high voltage source and the drain terminal of which is connected to the high voltage voltage source. A second polarity transistor connected to the terminal, and a second inverter having an input terminal connected to the external output terminal and an output terminal connected to the gate terminal of the second polarity transistor. And a positive feedback circuit that outputs the signal of 1.
2. A first transistor of a first polarity whose source terminal is connected to a high voltage source and whose drain terminal is connected to an external output terminal; and a source terminal which is connected to a ground voltage source and whose drain terminal is the external terminal. A second transistor having a first polarity connected to the output terminal, an input terminal connected to the external input terminal, and an output terminal connected to the first transistor
A first inverter connected to the gate terminal of the second transistor having the polarity, and an input terminal connected to the output terminal of the first inverter, and the output terminal having the gate terminal of the first transistor having the first polarity. A second inverter connected to the first inverter, a source terminal connected to the high-voltage voltage source, a first transistor having a second polarity, and a source terminal connected to the drain terminal of the first transistor having a second polarity. A drain terminal connected to the drain terminal of the first transistor of the first polarity and a drain terminal of the second transistor of the first polarity, and a gate terminal connected to the output terminal of the first inverter A second transistor having a second polarity, an input terminal connected to the external output terminal, and an output terminal connected to the gate terminal of the first transistor having the second polarity. It was made and a second inverter, CMOS level shift circuit, characterized in that it comprises a positive feedback circuit for outputting a signal of high potential.
3. A first transistor of a first polarity whose source terminal is connected to a high voltage source, and a source terminal of which is connected to a drain terminal of the first transistor of said first polarity and whose drain terminal is external. A first transistor having a second polarity connected to the output terminal, a second transistor having a first polarity connected to the ground voltage source and a drain terminal connected to the external output terminal, and an input terminal Is connected to the external input terminal and the output terminal is the second
And a gate terminal of the first transistor having a polarity of
A first inverter connected to the gate terminal of the second transistor having the polarity, and an input terminal connected to the output terminal of the first inverter, and the output terminal having the gate terminal of the first transistor having the first polarity. And a drain terminal of the first transistor having the second polarity and a drain terminal of the first transistor having the second polarity and a source terminal connected to the high-voltage voltage source. A second transistor having a second polarity connected to the terminal, and a second inverter having an input terminal connected to the external output terminal and an output terminal connected to the gate terminal of the second transistor having the second polarity. And a positive feedback circuit for outputting a high-potential signal.
Level shift circuit.
4. A first-polarity first transistor having a source terminal connected to a high-voltage voltage source; a source terminal connected to a drain terminal of the first-polarity first transistor; A first transistor having a second polarity connected to the output terminal, a second transistor having a first polarity connected to the ground voltage source and a drain terminal connected to the external output terminal, and an input terminal Is connected to the external input terminal and the output terminal is the second
And a gate terminal of the first transistor having a polarity of
A first inverter connected to the gate terminal of the second transistor having the polarity, and an input terminal connected to the output terminal of the first inverter, and the output terminal having the gate terminal of the first transistor having the first polarity. A second inverter connected to the first inverter, a source terminal connected to the high voltage source, and a drain terminal connected to the drain terminal of the first transistor of the first polarity and a source of the first transistor of the second polarity. A second transistor having a second polarity connected to the terminal, an input terminal connected to the external output terminal and an output terminal connected to the second
A CMOS level shift circuit comprising: a second inverter connected to the gate terminal of a second transistor having the above polarity, and a positive feedback circuit that outputs a high-potential signal.
JP6017146A 1994-02-14 1994-02-14 Cmos level shift circuit Withdrawn JPH07226670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6017146A JPH07226670A (en) 1994-02-14 1994-02-14 Cmos level shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6017146A JPH07226670A (en) 1994-02-14 1994-02-14 Cmos level shift circuit

Publications (1)

Publication Number Publication Date
JPH07226670A true JPH07226670A (en) 1995-08-22

Family

ID=11935863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6017146A Withdrawn JPH07226670A (en) 1994-02-14 1994-02-14 Cmos level shift circuit

Country Status (1)

Country Link
JP (1) JPH07226670A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034549A (en) * 1996-10-30 2000-03-07 Sumitomo Metal Industries, Ltd. Level shift circuit
JP2007201704A (en) * 2006-01-25 2007-08-09 Nec Electronics Corp Level shift circuit
US7288963B2 (en) 2004-03-24 2007-10-30 Elpida Memory, Inc. Level-conversion circuit
JP2010252330A (en) * 2009-04-13 2010-11-04 Taiwan Semiconductor Manufacturing Co Ltd Level shifter, integrated circuit, system, and method for operating level shifter
JP2011151719A (en) * 2010-01-25 2011-08-04 Renesas Electronics Corp Level shift circuit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034549A (en) * 1996-10-30 2000-03-07 Sumitomo Metal Industries, Ltd. Level shift circuit
US7288963B2 (en) 2004-03-24 2007-10-30 Elpida Memory, Inc. Level-conversion circuit
US7576566B2 (en) 2004-03-24 2009-08-18 Elpida Memory, Inc Level-conversion circuit
JP2007201704A (en) * 2006-01-25 2007-08-09 Nec Electronics Corp Level shift circuit
JP2010252330A (en) * 2009-04-13 2010-11-04 Taiwan Semiconductor Manufacturing Co Ltd Level shifter, integrated circuit, system, and method for operating level shifter
US8629704B2 (en) 2009-04-13 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifters, integrated circuits, systems, and methods for operating the level shifters
US9071242B2 (en) 2009-04-13 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifters, methods for making the level shifters and methods of using integrated circuits
JP2011151719A (en) * 2010-01-25 2011-08-04 Renesas Electronics Corp Level shift circuit
US8493125B2 (en) 2010-01-25 2013-07-23 Renesas Electronics Corporation Level shift circuit
US8575987B2 (en) 2010-01-25 2013-11-05 Renesas Electronics Corporation Level shift circuit

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