KR20130131070A - Voltage level shifter - Google Patents

Abstract

The present invention relates to a voltage level shifter which changes a voltage level of an input signal and outputs the changed input signal, and a voltage level shifter according to one embodiment of the present invention includes: a signal input unit for swinging a voltage level of an input signal using an inverter which receives a first voltage; a level conversion unit for converting a signal of the first voltage level into a signal of a second voltage level using a current mirror structure which receives the second voltage; an output buffer for outputting a signal of the second voltage level converted through the level conversion unit using an inverter which receives the second voltage; and a delay cell for preventing a static current of the mirror structure through the inverter receiving the second voltage in a logic-high section. [Reference numerals] (10) Signal input unit;(20) Level conversion unit;(31) Output buffer;(32) Delay cell;(AA) Input signal;(BB) First voltage;(CC) Second voltage;(DD) Output signal

Description

Voltage level shifter

The present invention relates to a level shifter for changing a voltage level, and more particularly to a CMOS voltage level-up shifter for changing a low voltage level to a high voltage level.

Recently, as semiconductor memory devices require high integration and high capacity, design rules continue to be reduced in order to integrate more semiconductor memory devices in a semiconductor chip. In addition, since the power consumption of the semiconductor memory device increases as the integration and capacity of the semiconductor memory device increase, many efforts have been made to reduce the power consumption.

Different voltages are used for each device to reduce power consumption of the system. Therefore, a level shifter circuit is required to accurately transfer signals between different voltages. In particular, the voltage level-up shifter is a circuit for converting a low voltage swing into a high voltage swing, and is applied to various semiconductor IC circuits such as memory devices, I / O interface circuits, and DC-DC converters.

The non-patent literature presented below introduces typical types and structures of such voltage level shifters.

 K.-H. Koo, J.-H. Seo, M.-L. Ko, and J.-W. Kim, “A new level-up shifter for high speed and wide range interface in ultra deep sub-micron,” in Proc. ISCAS, May 2005, vol. 2, pp. 1063-1065.

The technical problem to be solved by the present invention is to solve the problem that the voltage level conversion is delayed by adopting the cross-coupled method in the conventional voltage level shifter, and the constant current generated in the current mirror structure We want to overcome the limitation of increased power consumption due to static current.

In order to solve the above technical problem, the voltage level shifter for changing and outputting the voltage level of the input signal according to an embodiment of the present invention, the input by using an inverter supplied with a first voltage (inverter) A signal input unit swinging a voltage level of a signal to the first voltage; A level converting unit converting the signal of the first voltage level into a signal of the second voltage level by using a current mirror structure receiving a second voltage; An output buffer for outputting a signal of the converted second voltage level by using the inverter supplied with the second voltage; And a delay cell which prevents a static current of the mirror structure through a delay using an inverter supplied with the second voltage in a logic high period.

In the voltage level shifter according to an embodiment, the delay cell is caused by the constant current by using a power down to turn off a transistor constituting the mirror structure in the logic high period. Prevent power consumption

In the voltage level shifter according to an exemplary embodiment, the level converter may include a source terminal connected to a ground power source and a drain terminal connected to a first node to be applied to a gate from the signal input unit. A first transistor for switching according to a signal of a first voltage level; A second transistor having a source terminal connected to the ground power supply and a drain terminal connected to a second node to switch according to a signal of a first voltage level applied from the signal input unit to a gate; A third transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to the first node such that a current according to a second voltage level flows in a logic high period; A fourth transistor supplied with the second voltage through a source terminal, connected to the drain terminal with the second node, and configured to flow a current by a predetermined magnification of the third transistor by forming a current mirror structure with the third transistor; A fifth transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to a first node and switching according to a signal applied from the delay cell to a gate; And a second terminal supplied with the second voltage through a source terminal, and a drain terminal connected to a gate of the third transistor, a gate of a fourth transistor, and a source terminal of the fifth transistor, in response to a signal applied from the delay cell to the gate. And a sixth transistor for switching, and outputs a signal of a second voltage level amplified by the mirror structure through the second node to the output buffer.

In the voltage level shifter according to an embodiment, the level converting unit may output an output of a node supplying a high signal to the output buffer as the transistor constituting the mirror structure is turned off in a logic high period. It includes; PMOS transistor to prevent.

In the voltage level shifter according to an embodiment, the delay cell may include: a fifth inverter configured to receive the second voltage and invert a signal of a second voltage level converted through the level converter; And a sixth inverter configured to receive the second voltage to reinvert the signal of the inverted second voltage level, and to output the output signals of the fifth inverter and the sixth inverter to the level converter. The transistors constituting the mirror structure are turned off in the logic high period by applying them to the gates, respectively.

In order to solve the above technical problem, the voltage level shifter for changing and outputting the voltage level of the input signal according to another embodiment of the present invention, the voltage level of the input signal by using an inverter supplied with the first voltage; A signal input unit swinging at one voltage; A level converting unit converting the signal of the first voltage level into the signal of the second voltage level using a current mirror structure supplied with a second voltage; An output buffer configured to output a signal of the converted second voltage level using an inverter supplied with the second voltage; And a delay cell for preventing a constant current of the mirror structure through a delay using an inverter supplied with the second voltage in the case of logic high, wherein the level converter is configured to input a signal having a first voltage level from the signal input unit. A low voltage transistor and a low voltage transistor having a current mirror structure for converting a signal of the first voltage level into a signal of the second voltage level convert the voltage level at high speed.

In the voltage level shifter according to another embodiment, the level converter, the low voltage transistor receiving the signal of the first voltage level from the signal input unit and the signal of the first voltage level to the signal of the second voltage level Transistors that prevent oxide breakdown are connected in a cascode form between the low voltage transistors of the current mirror structure to be converted.

Further, in the voltage level shifter according to another embodiment, the transistor connected in the cascode form such that the drain-source voltage and the gate-source voltage of the transistors constituting the level converter do not exceed the voltage level that causes the oxide breakdown. A bias voltage is applied to the gate of.

In the voltage level shifter according to another embodiment, the level converter is switched in accordance with the signal of the first voltage level is applied to the gate from the signal input portion is connected to the source terminal and the drain terminal is connected to the first node A first transistor; A second transistor having a source terminal connected to the ground power supply and a drain terminal connected to a second node to switch according to a signal of a first voltage level applied from the signal input unit to a gate; A third transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to the third node such that a current according to a second voltage level flows in a logic high period; A fourth transistor supplied with the second voltage through a source terminal, connected with the drain terminal to the fourth node, and configured to flow a current by a predetermined magnification of the third transistor by forming a current mirror structure with the third transistor; A fifth transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to the third node and switching according to a signal applied from the delay cell to a gate; The second voltage is supplied through a source terminal, and a drain terminal is connected to a gate of the third transistor, a gate of a fourth transistor, and a source terminal of the fifth transistor, and is switched according to a signal applied from the delay cell to the gate. A sixth transistor; A seventh transistor having a source terminal connected to the first node and a drain terminal connected to a fifth node to switch according to a bias voltage applied to the gate; An eighth transistor having a source terminal connected to the second node and a drain terminal connected to a sixth node to switch according to the bias voltage applied to the gate; A ninth transistor connected to the third node with a source terminal connected to the third node, and switched according to the bias voltage applied to the gate; And a tenth transistor having a source terminal connected to the fourth node and a drain terminal connected to a sixth node to switch according to the bias voltage applied to a gate, and through the sixth node by the mirror structure. A signal of the amplified second voltage level is output to the output buffer.

In the voltage level shifter according to another embodiment, the level converter is configured to supply a high signal to the output buffer as the third transistor and the fourth transistor constituting the mirror structure are turned off in a logic high period. And a PMOS transistor for preventing the output of the node from floating.

Embodiments of the present invention use a power down technique in a logic high section of a level shifter of a current mirror structure to suppress the consumption of the static current of the current mirror structure and at the same time, a high voltage level. Conversion can be assured, and additional PMOS transistors in the current mirror structure can prevent floating nodes from occurring during power down. In another embodiment of the present invention, a current mirror structure is formed by using a low voltage transistor in implementing a level shifter, and a cascode type transistor is used to prevent oxide breakdown. Faster conversion time can be provided during voltage level conversion.

1 is a view showing an example of a level shifter for changing a voltage level in the technical field to which the present invention belongs.
2 is a view showing another example of a level shifter for changing a voltage level in the technical field to which the present invention belongs.
3 is a block diagram illustrating a voltage level shifter for changing and outputting a voltage level of an input signal according to an embodiment of the present invention.
4 is a circuit diagram illustrating the voltage level shifter of FIG. 3 in accordance with an embodiment of the present invention.
5 is a circuit diagram illustrating a voltage level shifter employing a cascode structure according to another embodiment of the present invention.
6 is a diagram illustrating a simulation waveform of the voltage level shifter circuit of FIG. 4 in accordance with an embodiment of the present invention.
7 is a diagram illustrating a simulation waveform of the voltage level shifter circuit of FIG. 5 according to another embodiment of the present invention.
8A and 8B are diagrams comparing delay times of the level shifters introduced through the embodiments of the present invention and FIGS. 1 and 2.

Before describing the embodiments of the present invention, a brief introduction of the conventional techniques used in the environment in which the embodiments of the present invention are implemented, that is, in the case of converting and outputting a voltage level of an input signal, will be described with reference to FIGS. In addition, it is intended to present structural problems that may occur in these implementation environments.

As briefly introduced above, level shifters are used to accurately transfer signals between different voltages. In the field of semiconductor circuit technology, various level converter technologies have been developed by many circuit designers to date. 1 to 2 illustrate exemplary voltage level-up shifters, and more detailed descriptions of the operation of these level shifters may obscure the nature of the present invention. .

FIG. 1 is a diagram illustrating an example of a level shifter for changing a voltage level in the technical field to which the present invention belongs, and corresponds to a level shifter commonly referred to as a type I method. The level shifter of FIG. 1 uses a positive feedback network composed of cross-coupled elements 110 (M ₃ , M ₄ ) to create a full output swing. It converts the level from V _DDL to V _DDH without leakage current. Two voltages V _DDL shown in FIG. 1 And V _DDH represent different voltage levels, in which case V _DDL <V _DDH . The input signal used in the circuit is made up of differential and uses a signal with a reverse phase with the original signal. In addition, a pull up latch circuit including two transistors 110 in a cross coupled form is used to perform a level shift.

FIG. 2 is a diagram illustrating another example of a level shifter for changing a voltage level in the technical field to which the present invention belongs, and corresponds to a level shifter commonly referred to as a type II method. Unlike the cross-coupled scheme illustrated in FIG. 1, the level shifter of FIG. 2 uses the elements 210 (M ₃ and M ₄ ) that form a current mirror structure to rapidly level up the voltage of the B node. It is possible.

1 and 2, the inverters INV ₃ and INV ₄ utilized in the transistors M ₁ to M ₄ , and the output buffer have a voltage swing of 0 to V _DDH , and an oxide breakdown. In order to solve the reliability problem caused by the high voltage (high voltage) transistor was used. In the case of a high voltage transistor, the oxide is formed of a thick oxide to prevent oxide film breakage, and is relatively slower than a low voltage device.

In the level shifter shown in FIG. 2, a large current flows through the transistor M ₄ by utilizing a current mirror structure, thereby significantly improving the delay time due to the level shifting compared to the cross-coupled level shifter shown in FIG. 1. However, since the constant current continues to flow through the elements M ₁ , M ₃ , and M ₄ constituting the current mirror in a logic high period (IN = high), power consumption is reduced in the level of FIG. 1. It has an increasing weakness than the shifter.

As introduced above, the level shifters of FIGS. 1 and 2 have disadvantages in certain portions, respectively. Accordingly, embodiments of the present invention described below are intended to propose a voltage level shifter that can effectively change the low voltage level to a high voltage level by utilizing the characteristics of the level shifter while eliminating this disadvantage.

Embodiments of the present invention are to turn off all the transistors constituting the current mirror in the logic high period, in order to improve the problem of the slow conversion that the level shifters of FIGS. We propose a technical means to reduce power consumption by cutting off the constant current using a power down technique. In addition, in order to prevent the output of the mirror structure from floating in a section where the current mirror stage is turned off, an additional transistor is connected to define a logic high.

Furthermore, another embodiment of the present invention, which will be described later, uses a cascode format for transistors for high voltages in the conversion process using a current mirror structure to speed up the conversion time of the proposed level shifter circuit using a power down technique. The present invention proposes a method of substituting low voltage transistors. Thus, this cascode structure can provide a stable and fast conversion time within the breakdown voltage range causing oxide breakdown.

Hereinafter, embodiments of the present invention for solving the above-mentioned technical problems will be described in detail with reference to the drawings. In the following description and the accompanying drawings, detailed description of well-known functions or constructions that may obscure the subject matter of the present invention will be omitted. It is to be noted that the same components are denoted by the same names and reference numerals as possible throughout the drawings.

3 is a block diagram illustrating a voltage level shifter 300 for changing and outputting a voltage level of an input signal according to an exemplary embodiment of the present invention, and schematically illustrating a voltage level shifter circuit centering on a functional block. A more detailed circuit configuration for implementing each functional block will be described later with reference to FIG. 4, and only an outline thereof will be introduced based on the role and function of each block.

The signal input unit 10 swings the voltage level of the input signal to the first voltage by using an inverter supplied with the first voltage.

The level converter 20 converts a signal of the first voltage level into a signal of the second voltage level by using a current mirror structure supplied with a second voltage. That is, in the embodiments of the present invention, the technical means for changing the voltage level is basically based on the current mirror structure. However, in order to solve the problem of the constant current in the current mirror structure as described above, an additional configuration, a delay cell 32 to be introduced later, is provided.

Furthermore, the level converter 20 may prevent the output of a node supplying a high signal to the output buffer from being floated as the transistor constituting the mirror structure is turned off in a logic high period (not shown). It is preferable to include).

The output buffer 31 outputs the signal of the second voltage level converted through the level converter 20 to the output terminal by using the inverter supplied with the second voltage.

The delay cell 32 prevents static current of the mirror structure through a delay using an inverter supplied with the second voltage in a logic high period. The delay cell 32 prevents power consumption due to a constant current flowing through the transistor by using a power down for turning off a transistor constituting the mirror structure in the logic high period. do.

4 is a circuit diagram illustrating the voltage level shifter of FIG. 3 in accordance with an embodiment of the present invention.

As outlined above, the voltage level shifter circuit proposed by the embodiments of the present invention employs a power down technique to improve the problem of power consumption due to the constant current generated in the level shifter introduced through FIG. 2. Embodiments of the present invention also include additional switches to define the logic level of the floating node that occurs upon power down.

In FIG. 4, the voltage level shifter uses the current mirror scheme introduced through FIG. 2 for fast level transitions. The level shifter circuit of FIG. 4 is a 'Stage 1' (10) consisting of inverters swinging from 0 to V _DDL , 'Stage 2' (20), which converts the V _DDL level to the V _DDH level, and powers down. It can be conveniently divided into 'Stage 3' 30 composed of a delay cell 32 for controlling and an output buffer 31 for outputting a final output. Hereinafter, each circuit configuration will be described in more detail.

Stage 1, i.e. the signal input unit 10, the first voltage (V _DDL) for supplying received first inverter (INV ₁₎ and the reverse when supplied with said first voltage (V _DDL) for inverting the input signal (IN) And a second inverter INV _{2 for} reversing the input signal. At this time, the signal input unit 10 has a phase opposite to each other, and the two input signals swinging from 0 to the first voltage V _{DDL at} the elements M ₁ and M ₂ of the level converting unit 20. Output to.

The stage 2, that is, the level converter 20 includes two signal input elements M ₁ and M ₂ , elements constituting the current mirror structure 23, and an anti-floating element M ₇ . More specifically, the level converter 20 is applied to the gate from the signal input unit 10 by connecting a source terminal to a ground power source and a drain terminal to a first node A. The first transistor (M ₁ ) for switching in accordance with the signal of the first voltage level (V _DDL ), and the source terminal is connected to the ground power source, the drain terminal is connected to the second node (B) to the signal input unit 10 A second transistor (M ₂ ) for switching in accordance with the signal of the first voltage level (V _DDL ) applied to the gate.

In addition, the current mirror structure 23 is supplied with a second voltage V _DDH through a source terminal, and a drain terminal is connected with the first node A to a second voltage level V _DDH in a logic high period. The third transistor M ₃ through which the current flows, the second voltage V _DDH is supplied through the source terminal, and the drain terminal is connected to the second node B, and the third transistor M ₃ is applied. And a fourth mirror M ₄ through which the current flows as much as a constant magnification of the third transistor M ₃ (illustrated as a positive integer K times in FIG. ₄ ) through the source terminal. A fifth transistor M ₅ supplied with the second voltage V _DDH and having a drain terminal connected to the first node A, and switched according to a signal applied from a delay cell 32 to a gate, and a source terminal a is the first being supplied to the second voltage (V _DDH) the drain terminal through the Third transistor (M ₃₎ for being connected to the source terminal of the gate and the fifth transistor (M ₅₎ of the gate, the fourth transistor (M _4), for switching in accordance with the signal applied to the gate from the delay cell 32 And a sixth transistor M ₆ .

The level converter 20 outputs a signal of the second voltage level V _DDH amplified by the mirror structure 23 through the second node B to the output buffer 31. In the present embodiment, the transistor constituting the level converter 20 is preferably a high voltage transistor.

Output buffer 31, the second voltage third inverter (INV ₃₎ when supplied with (V _DDH) for inverting the signal of the second voltage level (V _DDH) converted by the level converter 20, and wherein the first, from the fourth inverter (INV ₄₎ by when supplied with the second voltage (V _DDH) and a fourth inverter (INV ₄₎ for re-inverting the signal of the second voltage level (V _DDH) of the inverted 2 The signal of the voltage level V _DDH is output to the output terminal.

In the above level converter 20, first, when the input signal IN is changed from low to high, a logic high operation is started. Transistors M ₁ and M ₂ will receive opposite inputs by inverters INV ₁ and INV ₂ . In the logic high section, the gate of M ₁ is at a high level so that a large current flows through M ₃ , and K times the current flows through M _{4 due} to the current mirror circuit 23 configuration. Therefore, the voltage level of the B node rises, and the final output high occurs through the output buffer 31 composed of INV ₃ and INV ₄ .

On the other hand, the delay cells 32, a fifth inverter (INV ₅₎ which when supplied with the second voltage (V _DDH), invert the signal of the second voltage level (V _DDH) converted by the level converter 20 , and it includes a sixth inverter (INV ₆₎ to re-invert the signal of the second voltage when supplied with said inverted second voltage (V _DDH) level (V _DDH). The delay cell 32 transmits the output signals of the fifth inverter INV ₅ and the sixth inverter INV ₆ to gates of the transistors M ₅ and M ₆ constituting the level converter 20. The respective applications turn off the transistors M ₃ and M ₄ constituting the mirror structure 23 in the logic high period.

That is, Figure 4 the voltage level proposed shifter circuit after a delay by the delay cells configured to use a fast conversion through only during the initial operation logic high interval the current mirror circuit 23, and inverter 32, the transistor M ₃ And a power-down technique for turning M ₄ off, there is no fear of generating a constant current caused by the level shifter of FIG. 2 in the logic high section.

However, the voltage level shifter circuit of FIG. 4 may cause problems in the logic output because the B node is floating due to turning off the transistors M ₃ and M ₄ . Therefore, the voltage level shifter circuit proposed through FIG. 4 further connects the PMOS transistor M ₇ to the output terminal of the current mirror structure 23 to prevent the floating state of the B node in the logic high period. Due to this structure, the proposed voltage level shifter circuit can perform a voltage level-up operation with lower power than the voltage level shifter technology employing the current mirror structure illustrated in FIG.

On the other hand, the voltage level shifter circuit proposed through FIG. 4 uses a high voltage transistor in the level conversion process similarly to the voltage level shifter techniques of FIGS. 1 and 2, so that the reliability problem due to oxide breakdown is solved. On the other hand, a large amount of time may be spent on the conversion of the voltage level. Therefore, another embodiment of the present invention described below proposes a new technical means that can solve this delay of the conversion time.

FIG. 5 is a circuit diagram illustrating a voltage level shifter employing a cascode structure according to another embodiment of the present invention. The level shifter of FIG. Therefore, in order to avoid duplication of explanation, the following description will focus on the added configuration (change of the cascode structure and transistors) to improve the conversion speed.

As in FIG. 4, the voltage level shifter of FIG. 5 also receives a signal input unit 10 and a second voltage that swing the voltage level of the input signal to the first voltage using an inverter supplied with a first voltage. A level converter 20 for converting the signal of the first voltage level into the signal of the second voltage level by using a current mirror structure, and the converted second voltage level by using an inverter supplied with the second voltage. An output buffer 31 for outputting a signal and a delay cell 32 for preventing a constant current of the mirror structure through a delay using an inverter supplied with the second voltage in the case of logic high.

However, unlike the level shifter circuit of FIG. 4, the level converter 20 of the level shifter circuit of FIG. 5 is a low voltage transistor that receives a signal having a first voltage level from the signal input unit 10. And a low voltage transistor having a current mirror structure for converting the signal of the first voltage level to the signal of the second voltage level, so that the voltage level can be converted at high speed. Here, the level converter 20 is a low voltage transistor that receives a signal of the first voltage level from the signal input unit 10 and a current for converting the signal of the first voltage level to the signal of the second voltage level. It is preferable to connect the transistors in the cascode form 25 to prevent oxide breakdown between the low voltage transistors of the mirror structure. In addition, a bias is applied to the gates of the transistors connected to the cascode type 25 so that the drain-source voltage and the gate-source voltage of the transistors constituting the level converter 20 do not exceed the voltage level at which the oxide breakdown occurs. It is desirable to apply a bias voltage. That is, the bias voltage may be determined as a value between the first voltage level and the second voltage level.

More specifically, the level converter 20 may include a first voltage level V _DDL applied to a gate from the signal input unit 10 by connecting a source terminal to a ground power source and a drain terminal to a first node A. A first transistor (M ₁ ) for switching in accordance with the signal of (), and a _first terminal connected to the ground power source and a drain terminal connected to the second node (B) to be applied to the gate from the signal input unit (10). It includes a second transistor (M ₂ ) for switching in accordance with the signal of the voltage level (V _DDL ). Here, it is preferable that these elements M ₁ and M ₂ use low voltage transistors to improve the conversion speed.

In addition, the current mirror structure of the level converter 20 is supplied with the second voltage V _DDH through a source terminal, and a drain terminal is connected to the third node E so as to have a second voltage in a logic high period. The third transistor M ₃ through which current according to the level V _DDH flows, the second voltage V _DDH is supplied through a source terminal, and a drain terminal is connected to the fourth node F. third transistor (M ₃₎ and by forming a current mirror structure, the third transistor (M ₃₎ predetermined magnification (Fig. 5, the exemplified doubled positive integer K.) of the fourth transistor being the current of as much flow (M ₄₎ The fifth transistor M is supplied with the second voltage V _DDH through a source terminal, and the drain terminal is connected to the third node E, and switches according to a signal applied from the delay cell 32 to the gate. _5), and the second voltage (V _DDH), with a source terminal Class receiving and a drain terminal connected to the source terminal of the third transistor (M _3), a gate, a fourth transistor (M _4), the gate and the fifth transistor (M ₅₎ of the, to the gate from the delay cell 32 And a sixth transistor M ₆ that switches according to the applied signal. Here, it is preferable that some of the devices M ₃ and M ₄ forming the mirror structure use a low voltage transistor for improving the conversion speed.

In addition, the level converter 20 may be configured to switch according to a bias voltage V _BIAS applied to a gate by connecting a source terminal to the first node A and a drain terminal to the fifth node C. A seventh transistor M ₈ and an _eighth source terminal connected to the second node B and a drain terminal connected to the sixth node D to switch according to the bias voltage V _BIAS applied to a gate; Transistor M ₉ , a _ninth transistor having a source terminal connected to the third node E and a drain terminal connected to a fifth node C to switch according to the bias voltage V _BIAS applied to a gate ( M ₁₀ ) and a tenth transistor M connected to a source terminal connected to the fourth node F and a drain terminal connected to a sixth node D and applied according to the bias voltage V _BIAS applied to a gate. includes a _11), these elements are cascade-type It is coupled to 25. The Here, the elements M ₈ , M ₉ , M ₁₀ , and M ₁₁ connected in the cascode form 25 may use low voltage transistors to improve conversion speed.

Now, the level converter 20 outputs the signal of the second voltage level V _DDH amplified by the mirror structure through the sixth node D to the output buffer 31.

In summary, the level shifter circuit of FIG. 5 above lows the high voltage transistors M ₁ to M ₄ used in Stage 2 20 to provide faster conversion times than the level shifter circuit of FIG. 4. In order to prevent oxide breakdown that may occur in the low voltage device, M ₈ -M ₉ are connected to the drain terminals of M ₁ and M ₂ in cascode form, and M ₃ , M ₄ M ₁₀ -M ₁₁ was connected to the drain terminal in the form of a cascode. In addition, the drain-source voltage (V _ds ) and the gate-source voltage (V _gs ) of all transistors of 'Stage 2' 20 do not exceed the break-down voltage range, so that M ₈ -M ₉ A bias voltage (V _BIAS ) under appropriate conditions (V _DDL <V _BIAS <V _DDH ) was applied to the gate terminal of. Thus, all transistors of Stage 2 20 can safely operate within the breakdown voltage. Through the above configuration, the voltage level shifter circuit proposed through FIG. 5 may have a relatively faster conversion time than the voltage level shifter circuit proposed through FIG. 4 due to the fast operation characteristics of the low voltage device.

Meanwhile, the level converter 20 also supplies a high signal to the output buffer as the third transistor M ₃ and the fourth transistor M ₄ constituting the mirror structure are turned off in a logic high period. It is preferable to include a PMOS transistor (M ₇ ) to prevent the output of the node to be floated. In addition, the fifth transistor M ₅ , the sixth transistor M ₆ , and the floating prevention PMOS transistor M ₇ are preferably high voltage transistors.

Hereinafter, a simulation result using a 0.35 um BCD process will be introduced to evaluate the performance of the two embodiments proposed above (voltage level shifters of FIGS. 4 and 5). The transistors used in both embodiments are 5V, 8V CMOS devices. 5V devices have V _{gs . max} = 5.5 V, V _{ds . max} = 5.5V, W _min = 1.2um, L _min = 0.5um. 8V devices have V _gs.max = 13.2V, V _{ds . max} = 8.8V, the _{W min = 1.2um, L min =} 2.5um. As such, the 8V device has a higher breakdown voltage level compared to the 5V device. However, the operating speed of the transistor is slower because the minimum length of the transistor is more than five times.

6 is a diagram illustrating a simulation waveform of the voltage level shifter circuit 620 of FIG. 4 according to an embodiment of the present invention, and is compared with the simulation waveform of the conventional level shifter 610 illustrated in FIG. 2. Simulation conditions are V _DDL = 2.5V, V _DDH = 8V, and F _SW = 1MHz. It can be seen that the constant current flows continuously in the case of the conventional level shifter (Type II) 610 when the input signal IN is high. On the other hand, in the level shifter circuit 620 proposed through FIG. 4, when the voltage level of the C node becomes V _DDH , both M ₃ and M ₄ are turned off. Therefore, it can be seen that no constant current flows in the logic high period.

FIG. 7 is a diagram illustrating a simulation waveform of the voltage level shifter circuit of FIG. 5 according to another embodiment of the present invention. Simulation conditions are V _DDL = 2.5V, V _DDH = 8V, and F _SW = 1MHz. The level shifter circuit according to the proposed embodiment can be quickly converted by using a low voltage device, but there is a risk that the device is destroyed when V _gs and V _ds of the transistors exceed the breakdown voltage. Here, since V _BIAS (= V _DDH / 2) is applied to the gate terminals of the M ₃ -M ₄ transistors of the proposed level shifter circuit, all the transistors located in 'Stage 2' (level shifting stage) have a breakdown voltage range ( _{V gs. max = 5.5 V,} V ds.max = 5.5 V) it can be seen that operating within.

8A and 8B are diagrams comparing the delay times of embodiments of the present invention and the level shifters introduced through FIGS. 1 and 2, and a simulation for comparing a proposed voltage level shifter circuit with a conversion time of the prior art. The waveform is an example. Simulation conditions are V _DDL = 2.5V, V _DDH = 8V, and F _SW = 1MHz. FIG. 8A is a comparison of a rising time, and FIG. 8B is a comparison of a falling time. 'Conv.1' is a waveform according to the level shifter circuit of FIG. 1, and 'Conv.2' Are waveforms according to the level shifter circuit of FIG. 2, and 'Prop. 1' and 'Prop. 2' correspond to waveforms according to the level shifter circuit of FIGS. As can be seen in Figures 8a and 8b, the simulation result in the case of the voltage level shifter (Prop. 2) according to another embodiment of the present invention is rising = 2.05ns / falling = 1.22ns in the prior art (Conv. 1 and Compared to Conv. 2), it shows very short delay time.

Table 1 below shows the performance comparison of the proposed voltage level shifter circuit and the conventional level shifter technique through embodiments of the present invention.

Kinds Power Consumption uW ) rising time  ( ns ) falling time  ( ns ) Prior art 1 35.15 4.625 4.453 Prior art 2 1249.67 2.335 2.355 Invented Circuit 1 36.73 2.351 3.325 Invented Circuit 2 30.56 2.051 1.227

In Table 1, the simulation conditions are V _DDL = 2.5V, V _DDH = 8V, and F _SW = 1MHz. As shown in Table 1, it can be seen that the circuits according to the two embodiments of the present invention exhibit excellent characteristics in terms of power consumption and delay time. In particular, it can be seen that the proposed second voltage level shifter (invented circuit 2) greatly improves power consumption and delay time by using a low voltage device.

The above-described embodiments of the present invention use the power down technique in the logic high section of the level shifter of the current mirror structure to reduce the consumption of the static current of the current mirror structure in the logic high section. At the same time, fast voltage level transitions can be ensured, and additional PMOS transistors in the current mirror structure can prevent floating nodes from occurring during power down.

In addition, another embodiment of the present invention is to implement a current mirror structure using a low voltage transistor having a relatively fast operating characteristics in implementing a level shifter, and to provide a transistor that prevents oxide breakdown Cascading can provide faster conversion times for voltage level translations.

The present invention has been described above with reference to various embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

110: cross coupling structure 210: current mirror structure
300: voltage level shifter
10: signal input unit 20: level converting unit
23 current mirror structure 25 cascode structure
31: output buffer 32: delay cell

Claims (15)

In the voltage level shifter for changing the output voltage level of the input signal,
A signal input unit configured to swing a voltage level of the input signal to the first voltage by using an inverter supplied with a first voltage;
A level converting unit converting the signal of the first voltage level into a signal of the second voltage level by using a current mirror structure receiving a second voltage;
An output buffer for outputting a signal of the converted second voltage level by using the inverter supplied with the second voltage; And
And a delay cell for preventing static current of the mirror structure through a delay using an inverter supplied with the second voltage in a logic high period. The method of claim 1,
The delay cell,
The power level shifter is prevented by the constant current by using a power down for turning off the transistors constituting the mirror structure in the logic high period. The method of claim 1,
Wherein the signal input unit comprises:
A first inverter receiving the first voltage and inverting the input signal; And
And a second inverter receiving the first voltage and reversing the inverted input signal.
And a voltage level shifter having a phase opposite to each other and outputting two input signals swinging from zero to the first voltage. The method of claim 1,
The level converting unit,
A first transistor having a source terminal connected to a ground power source and a drain terminal connected to a first node to switch according to a signal of a first voltage level applied from the signal input unit to a gate;
A second transistor having a source terminal connected to the ground power supply and a drain terminal connected to a second node to switch according to a signal of a first voltage level applied from the signal input unit to a gate;
A third transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to the first node such that a current according to a second voltage level flows in a logic high period;
A fourth transistor supplied with the second voltage through a source terminal, connected to the drain terminal with the second node, and configured to flow a current by a predetermined magnification of the third transistor by forming a current mirror structure with the third transistor;
A fifth transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to a first node and switching according to a signal applied from the delay cell to a gate; And
The second voltage is supplied through a source terminal, and a drain terminal is connected to the gate of the third transistor, the gate of the fourth transistor, and the source terminal of the fifth transistor, and is switched according to a signal applied from the delay cell to the gate. Including a sixth transistor;
And outputs a signal having a second voltage level amplified by the mirror structure to the output buffer through the second node. 5. The method of claim 4,
And the transistors constituting the level converter are high voltage transistors. The method of claim 1,
The level converting unit,
And a PMOS transistor which prevents the output of the node supplying the high signal to the output buffer from floating when the transistors constituting the mirror structure are turned off in a logic high period. The method of claim 1,
The output buffer,
A third inverter receiving the second voltage and inverting a signal of the second voltage level converted through the level converter; And
And a fourth inverter receiving the second voltage to reinvert the signal of the inverted second voltage level.
And output a signal of a second voltage level from the fourth inverter. The method of claim 1,
The delay cell,
A fifth inverter configured to receive the second voltage and invert a signal of the second voltage level converted through the level converter; And
And a sixth inverter receiving the second voltage to reinvert the signal of the inverted second voltage level.
And applying the output signals of the fifth inverter and the sixth inverter to gates of the transistors constituting the level converter, respectively, to turn off the transistors constituting the mirror structure in a logic high period. In the voltage level shifter for changing and outputting the voltage level of the input signal,
A signal input unit configured to swing a voltage level of the input signal to the first voltage by using an inverter supplied with a first voltage;
A level converting unit converting the signal of the first voltage level into the signal of the second voltage level using a current mirror structure supplied with a second voltage;
An output buffer configured to output a signal of the converted second voltage level using an inverter supplied with the second voltage; And
A logic cell for delaying the constant current of the mirror structure through a delay using the inverter supplied with the second voltage in the case of logic high;
The level converting unit,
A low voltage transistor receiving a signal of a first voltage level from the signal input unit and a low voltage transistor of a current mirror structure for converting the signal of the first voltage level into a signal of the second voltage level; The voltage level shifter characterized by converting the voltage level at high speed. The method of claim 9,
The level converting unit,
Oxide breakdown between a low voltage transistor receiving a signal of a first voltage level from the signal input unit and a low voltage transistor of a current mirror structure converting the signal of the first voltage level into a signal of the second voltage level. A voltage level shifter characterized by connecting a transistor which prevents breakdown in the form of a cascode. 11. The method of claim 10,
Applying a bias voltage to a gate of a transistor connected in the cascode form such that the drain-source voltage and the gate-source voltage of the transistor constituting the level converter do not exceed the voltage level at which the oxide breakdown occurs. Voltage level shifter characterized by. The method of claim 11,
The bias voltage is determined as a value between the first voltage level and the second voltage level. The method of claim 9,
The level converting unit,
A first transistor having a source terminal connected to a ground power source and a drain terminal connected to a first node to switch according to a signal of a first voltage level applied from the signal input unit to a gate;
A second transistor having a source terminal connected to the ground power supply and a drain terminal connected to a second node to switch according to a signal of a first voltage level applied from the signal input unit to a gate;
A third transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to the third node such that a current according to a second voltage level flows in a logic high period;
A fourth transistor supplied with the second voltage through a source terminal, connected with the drain terminal to the fourth node, and configured to flow a current by a predetermined magnification of the third transistor by forming a current mirror structure with the third transistor;
A fifth transistor supplied with the second voltage through a source terminal, and having a drain terminal connected to the third node and switching according to a signal applied from the delay cell to a gate;
The second voltage is supplied through a source terminal, and a drain terminal is connected to a gate of the third transistor, a gate of a fourth transistor, and a source terminal of the fifth transistor, and is switched according to a signal applied from the delay cell to the gate. A sixth transistor;
A seventh transistor having a source terminal connected to the first node and a drain terminal connected to a fifth node to switch according to a bias voltage applied to the gate;
An eighth transistor having a source terminal connected to the second node and a drain terminal connected to a sixth node to switch according to the bias voltage applied to the gate;
A ninth transistor connected to the third node with a source terminal connected to the third node, and switched according to the bias voltage applied to the gate; And
A tenth transistor connected to the fourth node and a drain terminal connected to the sixth node to switch according to the bias voltage applied to the gate;
And outputting a signal of the second voltage level amplified by the mirror structure to the output buffer through the sixth node. The method of claim 13,
And the fifth transistor and the sixth transistor are high voltage transistors. The method of claim 13,
The level converting unit,
And a PMOS transistor configured to prevent an output of a node supplying a high signal to the output buffer from being floated as the third and fourth transistors constituting the mirror structure are turned off in a logic high period. Voltage level shifter.

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