CN111900975A - Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal - Google Patents
Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal Download PDFInfo
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Abstract
A level conversion circuit for converting a high-voltage domain signal into a low-voltage domain signal has strong duty cycle distortion suppression capability when converting the high-voltage domain signal into the low-voltage domain signal, and well maintains the duty cycle. It includes: the circuit comprises an input signal generating circuit, a differential input pair and a mirror load circuit; the input signal generating circuit provides two paths of signals to a differential input pair, the differential input pair comprises n pairs of NMOS tubes, the mirror load circuit comprises n pairs of PMOS tubes, and n is a positive integer; one path of signal is connected with the grid electrode of one of the pair of NMOS tubes, the drain electrode of the NMOS tube is connected with the drain electrode and the grid electrode of one of the pair of PMOS tubes and the grid electrode of the second of the pair of PMOS tubes, the other path of signal is connected with the grid electrode of the second of the pair of NMOS tubes, the drain electrode of the second of the pair of NMOS tubes and the drain electrode of the second of the pair of PMOS tubes are connected to form output, the source electrodes of the two NMOS tubes are grounded, and the source electrodes of the two PMOS tubes are connected with.
Description
Technical Field
The invention relates to the technical field of level-shifter design, in particular to a level shifter circuit for converting a high-voltage domain signal into a low-voltage domain signal.
Background
When the circuit intercommunications between different voltage domains, in order to guarantee device life-span and signal identification's reliability, need carry out signal level conversion, specifically divide into two kinds of situations: (1) when a high-voltage domain signal drives a low-voltage domain circuit, in order to ensure the service life of a low-voltage domain device and ensure that the low-voltage domain device cannot be directly driven, the high-voltage domain signal level needs to be converted into a low-voltage domain signal level for driving; (2) when a low-voltage domain signal drives a high-voltage domain circuit, in order to ensure the reliability of signal identification and prevent identification errors from being directly driven, the low-voltage domain signal level needs to be raised to a high-voltage domain signal level for driving.
For a level shifter circuit for converting a high voltage domain level into a low voltage domain level, a current mainstream circuit design is shown in fig. 1, wherein a PMOS transistor MP1_ HV and an NMOS transistor MN1_ HV are high voltage domain MOS devices, a PMOS transistor MP1 and an NMOS transistor MN1 are low voltage domain MOS devices, a high voltage domain MOS transistor MP1_ HV and an NMOS transistor MN1_ HV constitute an inverter, and a power supply of the inverter is a low voltage domain. When the circuit works, the input end is a high-voltage domain signal, because two devices of MP1_ HV and NMOS tube MN1_ HV are high-voltage domain devices, the voltage domain of the two devices corresponds to the high level of an input signal, the level of the input signal can not damage the devices in the working state, because the power supply is in a low-voltage domain, the high level of an output signal of an inverter formed by PMOS device MP1_ HV and NMOS device MN1_ HV is in a low-voltage domain level, the output signal is connected to the input end of the inverter formed by PMOS device MP1 and NMOS device MN1 and is output after logic inversion, and the logic polarity of the input and output signals after level conversion is ensured to be consistent.
The conventional high-voltage to low-voltage level converter circuit has the disadvantage that the duty ratio distortion is introduced, because the input signal is a high-voltage domain signal, while the high-voltage domain MOS tube in the circuit shown in FIG. 1 forms an inverter working in a low-voltage domain, and the corresponding closing voltage value of MP1_ HV is lower than that of the high-voltage domain, so that the voltage overturning threshold value is lower relative to the input signal level, and the high-level pulse width of the output signal after level conversion is increased compared with that of the input signal, and the low-level pulse width is reduced compared with that of the input signal, so that the signal duty ratio distortion is caused.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a level conversion circuit for converting a high-voltage domain signal into a low-voltage domain signal, which has stronger duty ratio distortion inhibition capability when converting the high-voltage domain signal into the low-voltage domain signal and well keeps the duty ratio.
The technical scheme of the invention is as follows: the level converting circuit for converting a high voltage domain signal into a low voltage domain signal comprises: the circuit comprises an input signal generating circuit, a differential input pair and a mirror load circuit; the input signal generating circuit provides two paths of high-voltage domain signals to a differential input pair, the differential input pair comprises n pairs of NMOS (N-channel metal oxide semiconductor) tubes, the mirror load circuit comprises n pairs of PMOS tubes, and n is a positive integer;
one path of high voltage domain signal is connected with the grid electrode of one of the pair of NMOS tubes, the drain electrode of the NMOS tube is connected with the drain electrode and the grid electrode of one of the pair of PMOS tubes and the grid electrode of the second of the pair of PMOS tubes, the other path of high voltage domain signal is connected with the grid electrode of the second of the pair of NMOS tubes, the drain electrodes of the second of the pair of NMOS tubes and the drain electrodes of the second of the pair of PMOS tubes are connected to form output, the source electrodes of the two NMOS tubes are grounded, and the source electrodes of the two PMOS tubes are connected with.
The input signal generating circuit provides two paths of high-voltage domain signals for the differential input pair to drive the differential input pair, the differential input pair and the mirror load circuit perform push-pull type work, and the high-voltage domain signals only drive the N-type MOS tube and do not directly drive the P-type MOS tube, and the mirror load formed by the P-type MOS tube is only driven by the low-voltage domain signals, so that the problem of conversion threshold introduced by driving the low-voltage domain P-type MOS tube by the high-voltage signals can be weakened, and the duty ratio distortion of output signals is reduced; therefore, the circuit has stronger duty cycle distortion inhibiting capability when converting a high-voltage domain signal into a low-voltage domain signal, and well keeps the duty cycle.
Drawings
Fig. 1 is a circuit diagram of a level shift circuit for converting a high voltage domain signal into a low voltage domain signal in the prior art.
Fig. 2 is a circuit diagram of one embodiment of a level shifting circuit for converting a high voltage domain signal to a low voltage domain signal in accordance with the present invention.
Fig. 3 is a circuit diagram of another embodiment of a level shifting circuit for converting a high voltage domain signal to a low voltage domain signal in accordance with the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In order to make the description of the present disclosure more complete and complete, the following description is given for illustrative purposes with respect to the embodiments and examples of the present invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The embodiments are intended to cover the features of the various embodiments as well as the method steps and sequences for constructing and operating the embodiments. However, other embodiments may be utilized to achieve the same or equivalent functions and step sequences.
The level converting circuit for converting a high voltage domain signal into a low voltage domain signal comprises: the circuit comprises an input signal generating circuit, a differential input pair and a mirror load circuit; the input signal generating circuit provides two paths of high-voltage domain signals to a differential input pair, the differential input pair comprises n pairs of NMOS (N-channel metal oxide semiconductor) tubes, the mirror load circuit comprises n pairs of PMOS tubes, and n is a positive integer;
one path of high voltage domain signal is connected with the grid electrode of one of the pair of NMOS tubes, the drain electrode of the NMOS tube is connected with the drain electrode and the grid electrode of one of the pair of PMOS tubes and the grid electrode of the second of the pair of PMOS tubes, the other path of high voltage domain signal is connected with the grid electrode of the second of the pair of NMOS tubes, the drain electrodes of the second of the pair of NMOS tubes and the drain electrodes of the second of the pair of PMOS tubes are connected to form output, the source electrodes of the two NMOS tubes are grounded, and the source electrodes of the two PMOS tubes are connected with.
The input signal generating circuit provides two paths of high-voltage domain signals for the differential input pair to drive the differential input pair, the differential input pair and the mirror load circuit perform push-pull type work, and the high-voltage domain signals only drive the N-type MOS tube and do not directly drive the P-type MOS tube, and the mirror load formed by the P-type MOS tube is only driven by the low-voltage domain signals, so that the problem of conversion threshold introduced by driving the low-voltage domain P-type MOS tube by the high-voltage signals can be weakened, and the duty ratio distortion of output signals is reduced; therefore, the circuit has stronger duty cycle distortion inhibiting capability when converting a high-voltage domain signal into a low-voltage domain signal, and well keeps the duty cycle.
Preferably, as shown in fig. 2, when n is 1, the input signal generating circuit includes a first NMOS transistor MN0_ HV and a first PMOS transistor MP0_ HV, the first NMOS transistor MN0_ HV and the first PMOS transistor MP0_ HV constitute an inverter and operate in a high voltage region; the differential input pair comprises a second NMOS transistor MN1_ HV and a third NMOS transistor MN2_ HV; the mirror load circuit comprises a second PMOS tube MP1 and a third PMOS tube MP2, and works in a low voltage region; the source electrode of the first NMOS tube is connected with the ground, the source electrode of the first PMOS tube is connected with a high-voltage domain power supply HV, the grid electrode of the first NMOS tube and the grid electrode of the first PMOS tube are simultaneously connected to an input signal IN, the drain electrode of the first NMOS tube and the drain electrode of the first PMOS tube are connected and then output to the grid electrode of the third NMOS tube, the source electrodes of the second NMOS tube and the third NMOS tube are connected to the ground, the grid electrode of the second NMOS tube is connected to the input signal IN, the drain electrode of the second NMOS tube is connected to the drain electrode of the second PMOS tube and the grid electrode of the third PMOS tube, the drain electrodes of the third PMOS tube and the second PMOS tube are connected with a low-voltage domain power supply LV, and the drain electrode of the third NMOS tube is connected.
The specific working principle of the circuit is as follows:
the input signal IN of the high-voltage domain passes through an inverter formed by MN0_ HV and MP0_ HV to generate a high-voltage domain signal with opposite polarity, a differential signal is formed with the input signal, the differential signal drives a differential input pair formed by MN1_ HV and MN2_ HV, the differential input pair drives a mirror load formed by MP1 and MP2 to carry out push-pull type work, and because the high-voltage domain signal only drives an N-type MOS tube and does not directly drive a P-type MOS tube, and the mirror load formed by the P-type MOS tube is only driven by the low-voltage domain signal, the problem of conversion threshold introduced by the driving of the low-voltage domain P-type MOS tube by the high-voltage signal can be weakened, so that the duty cycle distortion of the output signal is reduced.
The second NMOS transistor MN1_ HV and the third NMOS transistor MN2_ HV are driven by differential signals, and MN1_ HV and MN2_ HV form a differential pair transistor, and the two transistors have the same or different sizes.
Preferably, as shown IN fig. 3, when n is 2, the input signal generation circuit includes a forward input signal IN +, a reverse input signal IN-; the differential input pair comprises a second NMOS transistor MN1_ HV and a third NMOS transistor MN2_ HV of the first pair of NMOS transistors, a fourth NMOS transistor MN3_ HV and a fifth NMOS transistor MN4_ HV of the second pair of NMOS transistors, the second NMOS transistor and the fourth NMOS transistor have the same size, and the third NMOS transistor and the fifth NMOS transistor have the same size; the mirror load circuit comprises a second PMOS tube MP1 and a third PMOS tube MP2 of a first pair of PMOS tubes, a fourth PMOS tube MP3 and a fifth PMOS tube MP4 of a second pair of PMOS tubes, the sizes of the second PMOS tube and the fourth PMOS tube are the same, and the sizes of the third PMOS tube and the fifth PMOS tube are the same; the source electrodes of the second NMOS tube and the third NMOS tube are connected to the ground, the grid electrode of the second NMOS tube is connected to a forward input signal, the drain electrode of the second NMOS tube is connected to the drain electrode and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube, the drain electrodes of the third PMOS tube and the second PMOS tube are connected with a low-voltage domain power source LV, the grid electrode of the third NMOS tube is connected to a reverse input signal, and the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube to form a forward output OUT +; the source electrodes of the fourth NMOS transistor and the fifth NMOS transistor are connected to the ground, the grid electrode of the fourth NMOS transistor is connected to a reverse input signal, the drain electrode of the fourth NMOS transistor is connected to the drain electrode and the grid electrode of the fourth PMOS transistor and the grid electrode of the fifth PMOS transistor, the drain electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected with a low-voltage domain power supply, the grid electrode of the fifth NMOS transistor is connected to a forward input signal, and the drain electrode of the fifth NMOS transistor is connected with the drain electrode of the fifth PMOS transistor to form a reverse output OUT-.
The basic working principle of the circuit is the same as that of the circuit in fig. 2, and because the differential pair transistor load driven by the differential input signal in the differential working mode of the invention is completely the same as the mirror load driven by the differential pair transistor load, the output duty ratio change caused by the input common mode change can be well inhibited, and simultaneously, the output signals OUT + and OUT-after level conversion can still well keep the phase characteristics of the differential input signal.
The sizes of the second NMOS transistor MN1_ HV and the third NMOS transistor MN2_ HV are the same or different; the sizes of the fourth NMOS transistor MN3_ HV and the fifth NMOS transistor MN4_ HV are the same or different.
In addition, the second NMOS tube and the third NMOS tube are MOS devices resistant to high-voltage domain voltage.
The invention has the following beneficial effects:
(1) the level converter has stronger duty ratio distortion inhibition capability when converting a high-voltage domain signal into a low-voltage domain signal.
(2) The level shifter can better restrain the output duty ratio change caused by the input common mode change in the differential working mode.
(3) The level shifter can still well keep the phase characteristics of differential input signals in a differential working mode.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications, equivalent variations and modifications made to the above embodiment according to the technical spirit of the present invention still belong to the protection scope of the technical solution of the present invention.
Claims (6)
1. A level shift circuit for converting a high voltage domain signal to a low voltage domain signal, comprising: it includes: the circuit comprises an input signal generating circuit, a differential input pair and a mirror load circuit; the input signal generating circuit provides two paths of high-voltage domain signals to a differential input pair, the differential input pair comprises n pairs of NMOS (N-channel metal oxide semiconductor) tubes, the mirror load circuit comprises n pairs of PMOS tubes, and n is a positive integer;
one path of high voltage domain signal is connected with the grid electrode of one of the pair of NMOS tubes, the drain electrode of the NMOS tube is connected with the drain electrode and the grid electrode of one of the pair of PMOS tubes and the grid electrode of the second of the pair of PMOS tubes, the other path of high voltage domain signal is connected with the grid electrode of the second of the pair of NMOS tubes, the drain electrodes of the second of the pair of NMOS tubes and the drain electrodes of the second of the pair of PMOS tubes are connected to form output, the source electrodes of the two NMOS tubes are grounded, and the source electrodes of the two PMOS tubes are connected with.
2. The level shift circuit of claim 1, wherein: when n is equal to 1, the input signal generating circuit comprises a first NMOS transistor (MN0_ HV) and a first PMOS transistor (MP0_ HV), wherein the first NMOS transistor (MN0_ HV) and the first PMOS transistor (MP0_ HV) form an inverter and work in a high-voltage region; the differential input pair comprises a second NMOS transistor (MN1_ HV), a third NMOS transistor (MN2_ HV); the mirror load circuit comprises a second PMOS tube (MP1) and a third PMOS tube (MP2) and works in a low voltage region; the source electrode of the first NMOS tube is connected with the ground, the source electrode of the first PMOS tube is connected with a high voltage domain power supply (HV), the grid electrode of the first NMOS tube and the grid electrode of the first PMOS tube are simultaneously connected to an input signal (IN), the drain electrode of the first NMOS tube and the drain electrode of the first PMOS tube are connected and then output to the grid electrode of the third NMOS tube, the source electrodes of the second NMOS tube and the third NMOS tube are connected to the ground, the grid electrode of the second NMOS tube is connected to the input signal (IN), the drain electrode of the second NMOS tube is connected to the drain electrode of the second PMOS tube and the grid electrode of the third PMOS tube, the drain electrodes of the third PMOS tube and the second PMOS tube are connected with a low voltage domain power supply (LV), and the drain electrode of the third NMOS tube and the drain electrode of the third.
3. The level shift circuit of claim 2, wherein: the sizes of the second NMOS transistor (MN1_ HV) and the third NMOS transistor (MN2_ HV) are the same or different.
4. The level shift circuit of claim 1, wherein: when n is 2, the input signal generating circuit includes a forward input signal (IN +), an inverse input signal (IN-); the differential input pair comprises a second NMOS transistor (MN1_ HV), a third NMOS transistor (MN2_ HV) of the first pair of NMOS transistors, a fourth NMOS transistor (MN3_ HV) and a fifth NMOS transistor (MN4_ HV) of the second pair of NMOS transistors, the second NMOS transistor and the fourth NMOS transistor are the same in size, and the third NMOS transistor and the fifth NMOS transistor are the same in size; the mirror load circuit comprises a second PMOS (P-channel metal oxide semiconductor) tube (MP1) and a third PMOS tube (MP2) of a first pair of PMOS tubes, a fourth PMOS tube (MP3) and a fifth PMOS tube (MP4) of a second pair of PMOS tubes, the sizes of the second PMOS tube and the fourth PMOS tube are the same, and the sizes of the third PMOS tube and the fifth PMOS tube are the same; the source electrodes of the second NMOS tube and the third NMOS tube are connected to the ground, the grid electrode of the second NMOS tube is connected to a forward input signal, the drain electrode of the second NMOS tube is connected to the drain electrode and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube, the drain electrodes of the third PMOS tube and the second PMOS tube are connected with a low-voltage domain power supply (LV), the grid electrode of the third NMOS tube is connected to a reverse input signal, and the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube to form a forward output (OUT +); the source electrodes of the fourth NMOS tube and the fifth NMOS tube are connected to the ground, the grid electrode of the fourth NMOS tube is connected to a reverse input signal, the drain electrode of the fourth NMOS tube is connected to the drain electrode and the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube, the drain electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with a low-voltage domain power supply, the grid electrode of the fifth NMOS tube is connected to a forward input signal, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the fifth PMOS tube to form a reverse output (OUT-).
5. The level shift circuit of claim 4, wherein: the sizes of the second NMOS tube (MN1_ HV) and the third NMOS tube (MN2_ HV) are the same or different; the sizes of the fourth NMOS transistor (MN3_ HV) and the fifth NMOS transistor (MN4_ HV) are the same or different.
6. The level shift circuit of claim 1, wherein: the second NMOS tube and the third NMOS tube are MOS devices resistant to high-voltage domain voltage.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112332833A (en) * | 2020-11-16 | 2021-02-05 | 海光信息技术股份有限公司 | Level conversion circuit and CPU chip with same |
| CN114326899A (en) * | 2021-12-27 | 2022-04-12 | 上海贝岭股份有限公司 | Integrated circuit and clamping circuit thereof |
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| CN209072341U (en) * | 2018-10-23 | 2019-07-05 | 珠海市一微半导体有限公司 | The level shifter and chip across voltage domain based on DMOS pipe |
| TWM576365U (en) * | 2018-10-29 | 2019-04-01 | 修平學校財團法人修平科技大學 | Low power voltage level converter |
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| CN110690865A (en) * | 2019-10-24 | 2020-01-14 | 杭州雄迈集成电路技术有限公司 | High transconductance low input capacitance rail-to-rail operational amplifier |
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| CN110729995A (en) * | 2019-11-28 | 2020-01-24 | 华中科技大学 | Level conversion circuit and level conversion method |
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| CN114326899A (en) * | 2021-12-27 | 2022-04-12 | 上海贝岭股份有限公司 | Integrated circuit and clamping circuit thereof |
| CN114326899B (en) * | 2021-12-27 | 2023-09-15 | 上海贝岭股份有限公司 | Integrated circuit and clamping circuit thereof |
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