CN110417403A - A kind of high speed level shift circuit - Google Patents
A kind of high speed level shift circuit Download PDFInfo
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- CN110417403A CN110417403A CN201910698765.XA CN201910698765A CN110417403A CN 110417403 A CN110417403 A CN 110417403A CN 201910698765 A CN201910698765 A CN 201910698765A CN 110417403 A CN110417403 A CN 110417403A
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 13
- 230000010355 oscillation Effects 0.000 claims description 13
- 230000005611 electricity Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000000630 rising effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 4
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 8
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 8
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- 238000005516 engineering process Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The invention discloses a kind of high speed level shift circuits, including the first inverter modules, and the high-voltage signal for exporting high level circuit part rapidly realizes overturning to be converted into low pressure inversion signal in logically high change logic low；Second inverter modules, for low pressure inversion signal to be converted to low pressure in-phase signal, the present invention passes through in an existing level shift circuit first order PMOS device NMOS device in parallel, during VinH is lower level by high level, power supply is enhanced to the charging current of second level parasitic gate capacitor, shorten the charging time, can than existing level shift circuit arrangement works under higher frequency condition.
Description
Technical field
It the present invention relates to a kind of level shift circuit, can apply more particularly to one kind at intermediate frequency (< 1GHz), and can
Guarantee the novel high speed level shift circuit of the duty ratio (45%~55%) of preferable output signal.
Background technique
(such as oscillator, phaselocked loop etc.) often requires to use level shift circuit for high level in double power-supply system
The level signal of the high voltage of circuit part output moves to the level signal of lower voltage, then gives subsequent low-voltage high speed logic
Circuit is handled.
It is existing to apply the current potential translation LVDN in low frequency as shown in Figure 1.The structure mainly includes the first phase inverter and
Two phase inverters are used for wherein the first phase inverter is made of high tension apparatus PMOS tube PM0, NMOS tube NM0 by high level circuit part
The high-voltage signal of output is converted to reverse phase low-voltage signal, and the second phase inverter is made of low-voltage device PMOS tube PM1, NMOS tube NM1,
For low pressure inversion signal to be converted to low pressure in-phase signal；Corresponding input/output signal as shown in Fig. 2, the structure work
Principle is:
(1) during VinH rises to high level by low level, the state of PM0 by opening to turning off, and NM0 be then by
Unlatching is turned off, then the potential in the parasitic capacitance of the grid of PM1 and NM1, which is then discharged by NM0, to be reduced, while PM1 is opened
It opens, NM1 shutdown, VoutL becomes high level (high level < VinH high level of VoutL) from low；
(2) VinH by high level drop to it is low level during, the state of PM0 by shutdown to unlatching, and NM0 be then by
Shutdown is opened, is increased then the potential in the parasitic capacitance of the grid of PM1 and NM1 is then charged by PM0, while PM1 is closed
Disconnected, NM1 is opened, and VoutL becomes low level by height.
However, the structure is suitable for low-frequency channel, chief reason is as follows: when the frequency of input signal VinH increases
In the case where, during VinH drops to low level by high level, PM0 is by turning off to opening, due to the electricity of PM0 device itself
Ductility limit system, so that it is too long to the settling time of PM1 and NM1 parasitic gate capacitor charging by PM0, so will lead to NM1 also
It does not fully open, and input signal VinH has been switched to another state at this time, i.e., by the conversion of low level to high level, because
This VoutL is easy for that mistake occurs, and variation range of the duty ratio of output signal under the conditions of PVT is big.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of high speed current potential translation electricity
Road, to solve to need to carry out the current potential translation problem of Mid Frequency in double power-supply system.
In view of the above and other objects, the present invention proposes a kind of high speed level shift circuit, comprising:
First inverter modules, the high-voltage signal for exporting high level circuit part is in logically high change logic low
Rapidly realize overturning to be converted into low pressure inversion signal；
Second inverter modules, for low pressure inversion signal to be converted to low pressure in-phase signal.
Preferably, first inverter modules include:
First phase inverter, for completing the conversion of high-voltage signal to low pressure inversion signal；
Distribution capacity charging accelerating circuit, it is anti-to second for being completed when inputting high-voltage signal by logically high change logic low
The charging of the distribution capacity of phase device module accelerates.
Preferably, first phase inverter is realized by the first PMOS high-voltage tube PM0, the first NMOS high-voltage tube NM0.
Preferably, the high-voltage signal VinH of the high amplitude of oscillation is connected to grid, the first NMOS of the first PMOS high-voltage tube PM0
The drain electrode of the grid of high-voltage tube NM0, the first PMOS high-voltage tube PM0 is connect with the drain electrode of the first NMOS high-voltage tube NM0, and is connected to
The distribution capacity charging accelerating circuit and the second inverter modules, the source electrode of the first PMOS high-voltage tube PM0 connect low supply voltage
VDDL。
Preferably, the distribution capacity charging accelerating circuit is by the 3rd NMOS high-voltage tube NM2 and third high pressure phase inverter
INV2 is realized.
Preferably, the drain electrode of the source electrode and the first PMOS high-voltage tube PM0 of the 3rd NMOS high-voltage tube NM2 and the first NMOS
The drain electrode of high-voltage tube NM0, drain electrode meet the low supply voltage VDDL, and grid connects the third high pressure phase inverter INV2 output end,
The input of the third high pressure phase inverter INV2 terminates the high-voltage signal VinH of the high amplitude of oscillation, and power positive end connects high power supply electricity
Press VDDH, power supply negative terminal ground connection.
Preferably, second inverter modules are real by the 2nd PMOS low-voltage tube PM1 and the 2nd NMOS low-voltage tube NM1
It is existing.
Preferably, the grid of the 2nd PMOS low-voltage tube PM1 and the 2nd NMOS low-voltage tube NM1 are connected, and are connected to described the
Source electrode, the drain electrode of the first PMOS high-voltage tube PM0 and the drain electrode of the first NMOS high-voltage tube NM0 of three NMOS high-voltage tube NM2, it is described
The source electrode of 2nd PMOS low-voltage tube PM1 meets low supply voltage VDDL, and drain electrode is connected with the drain electrode of the 2nd NMOS low-voltage tube NM1
Form low swing signal VoutL output node.
Preferably, during the high-voltage signal VinH of the high amplitude of oscillation rises to high level by low level, described
The state of one PMOS high-voltage tube PM0 and the 3rd NMOS high-voltage tube NM2 are by opening to shutdown, and the first NMOS high-voltage tube NM0
Then by shutdown to opening, then in the parasitic capacitance of the grid of the 2nd PMOS low-voltage tube PM1 and the 2nd NMOS low-voltage tube NM1
Potential then discharged and reduce by the first NMOS high-voltage tube NM0, while the 2nd PMOS low-voltage tube PM1 is opened, the
Two NMOS low-voltage tube NM1 shutdown, low swing signal VoutL become high level from low level.
Preferably, during the high-voltage signal VinH of the high amplitude of oscillation drops to low level by high level, described
The state of one PMOS high-voltage tube PM0 and the 3rd NMOS high-voltage tube NM2 are by turning off to unlatching, and the first NMOS high-voltage tube NM0
Then by opening to shutdown, then in the parasitic capacitance of the grid of the 2nd PMOS low-voltage tube PM1 and the 2nd NMOS low-voltage tube NM1
Potential then increased by the first PMOS high-voltage tube PM0, the 3rd NMOS high-voltage tube NM2 quick charge, while the 2nd PMOS is low
Pressure pipe PM1 shutdown, the 2nd NMOS low-voltage tube NM1 are opened, and low swing signal VoutL becomes low level by high level.
Compared with prior art, a kind of high speed level shift circuit of the present invention passes through in the existing level shift circuit first order
PMOS device one NMOS device of parallel connection enhances power supply to the second level grid during VinH is lower level by high level
The charging current of pole parasitic capacitance, shortens the charging time, can than existing level shift circuit arrangement works more
Under high frequency condition.
Detailed description of the invention
Fig. 1 is existing low frequency level shift circuit structure chart；
Fig. 2 is the input and output sequential chart of Fig. 1 level shift circuit；
Fig. 3 is a kind of circuit structure diagram of the preferred embodiment of high speed level shift circuit of the present invention；
Fig. 4 is the input and output sequential chart of the high speed level shift circuit of the present invention；
Inputting in Fig. 5 (a), Fig. 5 (b) specific embodiment of the invention becomes high level, input from low level is become by high level
For low level working principle diagram；
Fig. 6 is RC oscillator structure figure of the present invention work in dual power supply domain.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 3 is a kind of circuit structure diagram of the preferred embodiment of high speed level shift circuit of the present invention.As shown in figure 3, this
Invent a kind of high speed level shift circuit, comprising: the first inverter modules 10 and the second inverter modules 20.
Wherein, the first inverter modules 10 are made of the first phase inverter 101 and distribution capacity charging accelerating circuit 102, are used
Rapidly realize overturning to be converted when the high-voltage signal for exporting high level circuit part is in logically high change logic low
For low pressure inversion signal, specifically, the first phase inverter is by the first PMOS high-voltage tube PM0 of high tension apparatus, the first NMOS high-voltage tube NM0
Composition, for completing the conversion of high-voltage signal to reverse phase low-voltage signal, distribution capacity charging accelerating circuit 102 is by high tension apparatus the
Three NMOS high-voltage tube NM2 and third high pressure phase inverter INV2 composition, for when inputting high-voltage signal by logically high change logic low
The charging to the distribution capacity (Cp) of the second inverter modules 20 is completed to accelerate；Second inverter modules 20 are by low-voltage device second
PMOS low-voltage tube PM1, the 2nd NMOS low-voltage tube NM1 composition, for low pressure inversion signal to be converted to low pressure in-phase signal.
The present invention is powered by two sets of power supplys (being VDDH, VDDL respectively), and input signal is the high-voltage signal VinH of the high amplitude of oscillation
(the high amplitude of oscillation level powered by high power supply voltage VDDH), output signal are the low-voltage signal VoutL of the low amplitude of oscillation (by low power supply electricity
Press the low amplitude of oscillation level of VDDL power supply).The high-voltage signal VinH of the high amplitude of oscillation is connected to the grid of the first PMOS high-voltage tube PM0,
The grid of one NMOS high-voltage tube NM0 and the input terminal of third phase inverter INV2, the output end of third phase inverter INV2 are connected to
The grid of three NMOS high-voltage tube NM2, the drain electrode and first of the source electrode and the first PMOS high-voltage tube PM0 of the 3rd NMOS high-voltage tube NM2
The grid of the drain electrode of NMOS high-voltage tube NM0, the 2nd PMOS low-voltage tube PM1 and the 2nd NMOS low-voltage tube NM1 is connected, the 3rd NMOS high
The drain electrode of pressure pipe NM2 and the source electrode of the first PMOS high-voltage tube PM0 and the source electrode of the 2nd PMOS low-voltage tube PM1 connect low supply voltage
VDDL, the power positive end of third phase inverter INV2 connect high power supply voltage VDDH, the power supply negative terminal of third phase inverter INV2, first
The source electrode of the source electrode of NMOS high-voltage tube NM0 and the 2nd NMOS low-voltage tube NM1 ground connection, the 2nd PMOS low-voltage tube PM1 and the 2nd NMOS
The drain electrode of low-voltage tube NM1 is connected to form low swing signal VoutL output node.
The present invention realizes a kind of novel high speed level shift circuit (Level down, LVDN), in PVT (Precess
Voltage Temperature, technique, voltage, temperature process angle) under the conditions of the structure can work at Mid Frequency (< 1GHz),
It can guarantee the duty ratio (DC, Duty Cycle) of output signal between 45%~55%, and structure is simply easily integrated.
In Mid Frequency compared to existing structure, to solve, first order PMOS tube charging current is weak to be easy to cause system function to the present invention structure
Energy mistake provides a kind of reliable scheme, and main principle is in one NMOS of existing LVDN first order PMOS device parallel connection
Device enhances power supply to the charging current of the second level parasitic gate capacitor during VinH is lower level by high level
Size shortens the charging time, can be than existing arrangement works under higher frequency condition.
Fig. 4 is the time diagram of input signal and output signal.The working principle of LVDN is as follows:
(1) during VinH rises to high level by low level, the state of PM0 and NM2 are by opening to shutdown, and NM0
It is then by shutdown to opening, then the potential in the parasitic capacitance of the grid of PM1 and NM1, which is then discharged by NM0, to be reduced, simultaneously
PM1 is opened, and NM1 shutdown, VoutL becomes high level (high level < VinH high level of VoutL) from low level；Such as Fig. 5 (a)
It is shown.
(2) VinH by high level drop to it is low level during, the state of PM0 and NM2 is by shutdown to unlatching, and NM0
It is then by opening to shutdown, then the potential in the parasitic capacitance of the grid of PM1 and NM1 then passes through PM0, NM2 quick charge
It increases, while PM1 is turned off, NM1 is opened, and VoutL becomes low level by high level；As shown in Fig. 5 (b).
It is demonstrated experimentally that the present invention can work normally under the conditions of 55nm platform and PVT in 500MHz, and guarantee to export
The duty ratio of signal is 45%~55%.
Fig. 6 show present invention work in the RC oscillator structure figure in dual power supply domain.Wherein first module is charge/discharge
Current module (Charge-Discharge, can trimming), second module are comparators, and third module is then the present invention
LVDN module.The work of charge/discharge module in the domain high voltage (VDD25, such as 2.5V), and LVDN work low-voltage (VDD, such as
The output in 1.5V) domain, comparator is converted to input signal of the low level as other subsequent logics by high level by LVDN.
In conclusion a kind of high speed level shift circuit of the present invention passes through in existing level shift circuit first order PMOS device
Part one NMOS device of parallel connection enhances power supply to the second level parasitic gate during VinH is lower level by high level
The charging current of capacitor, shortens the charging time, can than existing level shift circuit arrangement works in higher frequency
Under the conditions of rate.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. a kind of high speed level shift circuit, comprising:
First inverter modules, the high-voltage signal for exporting high level circuit part are quick in logically high change logic low
Realize overturning to be converted into low pressure inversion signal in ground；
Second inverter modules, for low pressure inversion signal to be converted to low pressure in-phase signal.
2. a kind of high speed level shift circuit as described in claim 1, which is characterized in that the first inverter modules packet
It includes:
First phase inverter, for completing the conversion of high-voltage signal to low pressure inversion signal；
Distribution capacity charging accelerating circuit, for completing when inputting high-voltage signal by logically high change logic low to the second phase inverter
The charging of the distribution capacity of module accelerates.
3. a kind of high speed level shift circuit as claimed in claim 2, it is characterised in that: first phase inverter is by first
PMOS high-voltage tube, the first NMOS high-voltage tube are realized.
4. a kind of high speed level shift circuit as claimed in claim 3, it is characterised in that: the high-voltage signal of the high amplitude of oscillation is connected to
The grid of the grid of the first PMOS high-voltage tube, the first NMOS high-voltage tube, the drain electrode of the first PMOS high-voltage tube and the first NMOS
The drain electrode of high-voltage tube connects, and is connected to the distribution capacity charging accelerating circuit and the second inverter modules, the first PMOS high
The source electrode of pressure pipe connects low supply voltage.
5. a kind of high speed level shift circuit as claimed in claim 4, it is characterised in that: the distribution capacity charging accelerates electricity
It routes the 3rd NMOS high-voltage tube and third high pressure phase inverter is realized.
6. a kind of high speed level shift circuit as claimed in claim 5, it is characterised in that: the source of the 3rd NMOS high-voltage tube
The drain electrode and the drain electrode of the first NMOS high-voltage tube of pole and the first PMOS high-voltage tube, drain electrode connect the low supply voltage, and grid meets institute
Third high pressure inverter output is stated, the input of the third high pressure phase inverter terminates the high-voltage signal of the high amplitude of oscillation, electricity
Source just terminates high power supply voltage, power supply negative terminal ground connection.
7. a kind of high speed level shift circuit as claimed in claim 6, it is characterised in that: second inverter modules are by the
Two PMOS low-voltage tubes and the 2nd NMOS low-voltage tube are realized.
8. a kind of high speed level shift circuit as claimed in claim 7, it is characterised in that: the 2nd PMOS low-voltage tube and second
The grid of NMOS low-voltage tube is connected, and be connected to the 3rd NMOS high-voltage tube source electrode, the first PMOS high-voltage tube drain electrode with
And the first NMOS high-voltage tube drain electrode, the source electrode of the 2nd PMOS low-voltage tube connects low supply voltage, drain electrode and described second
The drain electrode of NMOS low-voltage tube is connected to form low swing signal output node.
9. a kind of high speed level shift circuit as claimed in claim 8, it is characterised in that: in the high-voltage signal of the high amplitude of oscillation
During rising to high level by low level, the state of the first PMOS high-voltage tube and the 3rd NMOS high-voltage tube is by opening
Shutdown, and the first NMOS high-voltage tube then by shutdown to unlatching, then the 2nd PMOS low-voltage tube and the 2nd NMOS low pressure
Potential in the parasitic capacitance of the grid of pipe is then reduced by the first NMOS high pressure tube discharge, while the 2nd PMOS
Low-voltage tube is opened, and the 2nd NMOS low-voltage tube shutdown, low swing signal becomes high level from low level.
10. a kind of high speed level shift circuit as claimed in claim 9, it is characterised in that: believe in the high pressure of the high amplitude of oscillation
Number by high level drop to it is low level during, the state of the first PMOS high-voltage tube and the 3rd NMOS high-voltage tube is by turning off
To unlatching, and the first NMOS high-voltage tube is then by opening to turning off, then the 2nd PMOS low-voltage tube is low with the 2nd NMOS
Potential in the parasitic capacitance of the grid of pressure pipe is then risen by the first PMOS high-voltage tube, the 3rd NMOS high-voltage tube quick charge
Height, while the 2nd PMOS low-voltage tube turns off, the 2nd NMOS low-voltage tube is opened, and low swing signal becomes low level by high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910698765.XA CN110417403A (en) | 2019-07-31 | 2019-07-31 | A kind of high speed level shift circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910698765.XA CN110417403A (en) | 2019-07-31 | 2019-07-31 | A kind of high speed level shift circuit |
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| Publication Number | Publication Date |
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| CN110417403A true CN110417403A (en) | 2019-11-05 |
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ID=68364480
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910698765.XA Pending CN110417403A (en) | 2019-07-31 | 2019-07-31 | A kind of high speed level shift circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900975A (en) * | 2020-08-06 | 2020-11-06 | 中科亿海微电子科技（苏州）有限公司 | Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal |
| CN113381747A (en) * | 2021-08-13 | 2021-09-10 | 上海奥令科电子科技有限公司 | High-speed low-swing level conversion circuit |
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| JPH10190377A (en) * | 1996-11-08 | 1998-07-21 | Sharp Corp | Differential amplifier and voltage follower circuit |
| CN1411150A (en) * | 2001-10-03 | 2003-04-16 | 日本电气株式会社 | Sample level shift circuit, two phase and multi-phase developing circuit and display |
| CN101686042A (en) * | 2009-05-19 | 2010-03-31 | 中国电子科技集团公司第二十四研究所 | 64 to 1 analog switch circuit of T-switch structure |
| CN103546126A (en) * | 2013-10-28 | 2014-01-29 | 无锡中星微电子有限公司 | Low noise relay circuit |
| CN105897230A (en) * | 2016-05-20 | 2016-08-24 | 西安紫光国芯半导体有限公司 | Gated power circuit and generation method of gated power supply |
| CN106130536A (en) * | 2016-06-20 | 2016-11-16 | 华为技术有限公司 | Level shifting circuit and electronic equipment |
-
2019
- 2019-07-31 CN CN201910698765.XA patent/CN110417403A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10190377A (en) * | 1996-11-08 | 1998-07-21 | Sharp Corp | Differential amplifier and voltage follower circuit |
| CN1411150A (en) * | 2001-10-03 | 2003-04-16 | 日本电气株式会社 | Sample level shift circuit, two phase and multi-phase developing circuit and display |
| CN101686042A (en) * | 2009-05-19 | 2010-03-31 | 中国电子科技集团公司第二十四研究所 | 64 to 1 analog switch circuit of T-switch structure |
| CN103546126A (en) * | 2013-10-28 | 2014-01-29 | 无锡中星微电子有限公司 | Low noise relay circuit |
| CN105897230A (en) * | 2016-05-20 | 2016-08-24 | 西安紫光国芯半导体有限公司 | Gated power circuit and generation method of gated power supply |
| CN106130536A (en) * | 2016-06-20 | 2016-11-16 | 华为技术有限公司 | Level shifting circuit and electronic equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900975A (en) * | 2020-08-06 | 2020-11-06 | 中科亿海微电子科技（苏州）有限公司 | Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal |
| CN113381747A (en) * | 2021-08-13 | 2021-09-10 | 上海奥令科电子科技有限公司 | High-speed low-swing level conversion circuit |
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