CN107276384A - A kind of soft starting circuit based on pulse charge - Google Patents
A kind of soft starting circuit based on pulse charge Download PDFInfo
- Publication number
- CN107276384A CN107276384A CN201710451189.XA CN201710451189A CN107276384A CN 107276384 A CN107276384 A CN 107276384A CN 201710451189 A CN201710451189 A CN 201710451189A CN 107276384 A CN107276384 A CN 107276384A
- Authority
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- China
- Prior art keywords
- pmos
- nmos tube
- grid
- input
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
Abstract
A kind of soft starting circuit based on pulse charge, belongs to electric and electronic technical field.Including pulse signal generation unit, charhing unit and error amplifier block, pulse signal generating circuit carries out digital processing to clock signal clk, has obtained narrow pulse signal Vpulse；Charhing unit passes through narrow pulse signal VpulseThe slow charging to soft start capacitor C is realized, the raised voltage V of slow rising has been obtainedraise, because mean charging current is smaller, so soft start capacitor C need not be large, can accomplish in piece；Pass through the raised voltage V slowly risenraiseControl the soft start voltage V of error amplifier block outputoutIt is slow to rise, soft start is realized, and as the soft start voltage V of outputoutCharhing unit produces stop signal effect pulse signal generation unit after stable, so as to close soft starting circuit.Switched over The present invention reduces chip pin number and plate level space, and without the input to error amplifier, effectively reduce burr, realize smooth transition.
Description
Technical field
The invention belongs to electric and electronic technical field, and in particular to the pulse signal produced using clock signal is to electric in piece
Appearance is charged so that the soft start voltage of the output of error amplifier slowly rises and is applied to the soft start electricity of late-class circuit
Road, is mainly used in DC-DC switch converters field.
Background technology
In four kinds of basic circuits of DC-DC switch converters, by taking Buck converters as an example, Buck converters have output
The characteristics of voltage is less than input voltage, not isolated DC, be otherwise known as decompression transducer, therefore is widely used in movement just
Take in equipment.But Buck circuits are also easy to produce voltage overshoot and current surge phenomenon in powered on moment, it is possible to cause Buck electricity
Road and the damage of electronic equipment, accordingly, it would be desirable to quote soft starting circuit, control error amplifier defeated with the voltage slowly risen
Go out the slow rising of voltage, so that Buck circuit output voltages slowly rise, reach after predetermined value, system just enters normal
Working condition.Avoid the damage that above-mentioned voltage overshoot and current surge phenomenon are caused to system.
Traditional soft starting circuit is that electric capacity is charged by current source, with restraining error amplifier output voltage,
So as to limit dutycycle, and then limit startup stage Buck circuit output voltage.Typical soft starting circuit charges for current source
Scheme, is charged using μ A magnitudes electric currents to electric capacity outside nF grades of pieces, the shortcoming of this method be the increase in chip pin number and
The outer soft start capacitor of a piece is needed, this will increase application cost and application plate level space.
Some existing solutions are to produce ramp voltage using the mode of digital analog converter DAC controls, i.e.,
Ramp voltage is obtained come the resistance that control electric current lens array flows through by multi-bit counter, or passes through multi-bit counter control electric current
Source stream crosses electric resistance array and obtains ramp voltage, but its circuit is more complicated and jagged occurs.
The content of the invention
A kind of pulse is based on for, to the weak point of the charging circuit of soft start capacitor, the present invention is provided in prior art
The soft starting circuit of charging, the circuit more stablizes and burr is less, and soft start capacitor is accomplished in piece to reduce chip pin
Number and plate level space, and then reduce application cost and application plate level space.
The technical scheme is that：
A kind of soft starting circuit based on pulse charge, including pulse signal generation unit, charhing unit and error amplification
Device unit,
Pulse signal generation unit includes first and delayed with door AND1, second and door AND2, the first NAND gate NAND1, first
Device BUFFER1 and the first NOT gate INV1 are rushed,
First is connected enable signal VEN with door AND1 first input end, and its output end output control signal VE simultaneously connects
First NAND gate NAND1 first input end；First NAND gate NAND1 the second input connection clock signal clk, it is exported
The first buffer BUFFER1 of end connection input and the first NOT gate INV1 input；Second inputs with the first of door AND2
The first buffer BUFFER1 of end connection output end, its second input connects the first NOT gate INV1 output end, its output end
Export narrow pulse signal Vpulse；
Charhing unit include the second phase inverter INV2, the 3rd phase inverter INV3, the first PMOS P1, the second PMOS P2,
First NMOS tube N1, the second NMOS tube N2, the first schmitt inverter SINV1 and soft start capacitor C,
Second phase inverter INV2 input connection control signal VE, its output end connects the first PMOS P1 grid；
3rd phase inverter INV3 input connection enables signal VEN, and its output end connects the second NMOS tube N2 grid；First NMOS
Pipe N1 grid connection narrow pulse signal Vpulse, its first PMOS P1 of connection that drains drain electrode, the 2nd NMOS of its source electrode connection
Pipe N2 drain electrode, the input of the second PMOS P2 drain electrode and the first schmitt inverter SINV1 are simultaneously used as charhing unit
Output end output raised voltage Vraise；First schmitt inverter SINV1 output end connects the second PMOS P2 grid simultaneously
Export the second input of first and door AND1 in stop signal connection pulse signal generation unit；Soft start capacitor C is connected on
Between two PMOS P2 drain electrode and ground, the second NMOS tube N2 source ground, the first PMOS P1 and the second PMOS P2's
Source electrode meets supply voltage VDD；
The positive input connection reference voltage V of the error amplifier blockref, its negative input connection feedback electricity
Press VFB, the raised voltage V that its control end connection charhing unit is producedraise, its output end output soft start voltage Vout。
Specifically, error amplifier block includes the 3rd PMOS P3, the 4th PMOS P4, the 5th PMOS P5, the 6th
PMOS P6, the 7th PMOS P7, the 8th PMOS P8, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5,
Six NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8 and reference current source Iref,
7th PMOS P7 grid is used as the negative input of error amplifier block, its 4th NMOS tube of connection that drains
N4 grid, the 5th NMOS tube N5 grid and drain electrode；8th PMOS P8 grid as error amplifier block forward direction
Input, its 8th NMOS tube N8 of connection that drains grid, the 7th NMOS tube N7 grid and drain electrode；7th PMOS P7 and
Eight PMOS P8 source electrode is connected and connects the 6th PMOS P6 drain electrode；
3rd NMOS tube N3 grid is as the control end of error amplifier block, and it drains the 5th PMOS P5's of connection
Grid, the 4th PMOS P4 grid and drain electrode, its source electrode connect the 4th NMOS tube N4 drain electrode and the 6th NMOS tube N6 source
Pole；
3rd PMOS P3 grid leak short circuit and the grid for connecting the 6th PMOS P6, the 5th PMOS P5 drain electrode connection
The drain electrode of 6th NMOS tube N6 drain and gate and the 8th NMOS tube N8 is simultaneously used as the output end of error amplifier block；Base
Quasi- current source IrefIt is connected between the 3rd PMOS P3 drain electrode and ground；
3rd PMOS P3, the 4th PMOS P4, the 5th PMOS P5, the 6th PMOS P6 source electrode connect supply voltage
VDD, the 4th NMOS tube N4, the 5th NMOS tube N5, the 7th NMOS tube N7 and the 8th NMOS tube N8 source ground.
The present invention operation principle be：When the present invention is by BUFFER1 pairs of the first buffer in pulse signal generating circuit
Clock signal clk carries out fine delay processing, then is handled by Digital Logic, has obtained narrow pulse signal Vpulse；Charhing unit leads to
Cross narrow pulse signal VpulseThe slow charging to soft start capacitor C is realized, the raised voltage V of slow rising has been obtainedraise, by
It is smaller in mean charging current, so soft start capacitor C need not be large, it can accomplish in piece；Pass through the rising electricity slowly risen
Press VraiseControl the soft start voltage V of error amplifier block outputoutIt is slow to rise, soft start is realized, and when output
Soft start voltage VoutCharhing unit produces stop signal effect pulse signal generation unit after stable, so as to close soft start electricity
Road.
Beneficial effects of the present invention are：The soft starting circuit based on pulse charge that the present invention is provided is realizing soft start electricity
Pressure reduces soft start capacitor while slowly rising, and soft start capacitor is accomplished in piece, reduces chip pin number and plate level
Space, and then reduce application cost and application plate level space；And the circuit is switched over without the input to error amplifier, is had
Effect reduces burr, realizes smooth transition.
Brief description of the drawings
A kind of soft starting circuit overall structure based on pulse charge that Fig. 1 provides for the present invention.
Fig. 2 is the circuit structure of pulse signal generation unit in Fig. 1.
Fig. 3 is the physical circuit of charhing unit in Fig. 1.
Fig. 4 is a kind of particular circuit configurations of the error amplifier block in Fig. 1 in embodiment.
Pulse signal generating circuit timing diagram when Fig. 5 is soft starting circuit normal work.
Output voltage figure when Fig. 6 is soft starting circuit normal work.
Embodiment
The present invention is described in detail with reference to embodiment and accompanying drawing.
It is as shown in Figure 1 the specific schematic diagram of the soft starting circuit proposed by the present invention based on pulse charge, including pulse
Physical circuit figure such as Fig. 2 institutes of signal generation unit, charhing unit and error amplifier block, wherein pulse signal generation unit
Show, pulse signal generation unit includes first and door AND1, second and door AND2, the first NAND gate NAND1, the first buffer
BUFFER1 and the first NOT gate INV1, first is connected enable signal VEN, the output control of its output end with door AND1 first input end
Signal VE processed and the first input end for connecting the first NAND gate NAND1；First NAND gate NAND1 the second input connection clock
Signal clk, its output end connects the first buffer BUFFER1 input and the first NOT gate INV1 input；Second and door
AND2 first input end connects the first buffer BUFFER1 output end, and its second input connects the first NOT gate INV1's
Output end, its output end output narrow pulse signal Vpulse.The physical circuit figure of charhing unit is as shown in figure 3, charhing unit includes
Second phase inverter INV2, the 3rd phase inverter INV3, the first PMOS P1, the second PMOS P2, the first NMOS tube N1, the 2nd NMOS
Pipe N2, the first schmitt inverter SINV1 and soft start capacitor C, the second phase inverter INV2 input connection control signal VE,
Its output end connects the first PMOS P1 grid；3rd phase inverter INV3 input connection enables signal VEN, its output end
Connect the second NMOS tube N2 grid；First NMOS tube N1 grid connection narrow pulse signal Vpulse, its connection first that drains
PMOS P1 drain electrode, the drain electrode, the second PMOS P2 drain electrode and the first Schmidt that its source electrode connects the second NMOS tube N2 is anti-
Phase device SINV1 input simultaneously exports raised voltage V as the output end of charhing unitraise；First schmitt inverter SINV1
Output end connect the second PMOS P2 grid and export first and door in stop signal connection pulse signal generation unit
AND1 the second input；Soft start capacitor C is connected between the second PMOS P2 drain electrode and ground, the second NMOS tube N2 source electrode
Ground connection, the first PMOS P1 and the second PMOS P2 source electrode meet supply voltage VDD；The positive input of error amplifier block
Connect reference voltage Vref, its negative input connection feedback voltage VFB, the raised voltage that its control end connection charhing unit is produced
Vraise, its output end output soft start voltage Vout。
The physical circuit figure of error amplifier block in the present embodiment is as shown in figure 4, including the 3rd PMOS P3, the 4th
PMOS P4, the 5th PMOS P5, the 6th PMOS P6, the 7th PMOS P7, the 8th PMOS P8, the 3rd NMOS tube N3,
Four NMOS tube N4, the 5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8 and reference current source
Iref, the 7th PMOS P7 grid is as the negative input of error amplifier block, and it drains the 4th NMOS tube N4's of connection
Grid, the 5th NMOS tube N5 grid and drain electrode；8th PMOS P8 grid is inputted as the forward direction of error amplifier block
End, its 8th NMOS tube N8 of connection that drains grid, the 7th NMOS tube N7 grid and drain electrode；7th PMOS P7 and the 8th
PMOS P8 source electrode is connected and connects the 6th PMOS P6 drain electrode；3rd NMOS tube N3 grid is used as error amplifier list
The control end of member, its 5th PMOS P5 of connection that drains grid, the 4th PMOS P4 grid and drain electrode, its source electrode connection the
Four NMOS tube N4 drain electrode and the 6th NMOS tube N6 source electrode；3rd PMOS P3 grid leak short circuit simultaneously connects the 6th PMOS P6
Grid, the 5th PMOS P5 drain electrode connection the 6th NMOS tube N6 drain and gate and the 8th NMOS tube N8 drain electrode simultaneously
It is used as the output end of error amplifier block；Reference current source IrefIt is connected between the 3rd PMOS P3 drain electrode and ground；3rd
PMOS P3, the 4th PMOS P4, the 5th PMOS P5, the 6th PMOS P6 source electrode meet supply voltage VDD, the 4th NMOS tube
N4, the 5th NMOS tube N5, the 7th NMOS tube N7 and the 8th NMOS tube N8 source ground.
The course of work of the present embodiment is：
Soft starting circuit enables signal VEN before starting be low level, and stop signal~stop is high level, stop signal
~stop is that low level is effective.
Before charhing unit is started working, it is low level to enable signal VEN so that the 3rd phase inverter INV3 is output as high electricity
It is flat, so that the second NMOS tube N2 is opened.Now control signal VE is low potential so that the second phase inverter INV2 output ends are height
Current potential, so that the first PMOS P1 is closed, and stop signal~stop is high potential, and the second PMOS P2 is closed, from
And cause raised voltage VraiseFor low potential.
When it is high level to enable signal VEN by low transition, pulse signal generation unit is started working, and produces narrow arteries and veins
Rush signal Vpulse, signal timing diagram is as shown in Figure 5；Control signal VE is high potential, and the second phase inverter INV2 is output as low electricity
Flat, the first PMOS P1 is opened, and enables signal VEN for high level so that the 3rd phase inverter INV3 is output as low level, from
And close the second NMOS tube N2.The narrow pulse signal V that pulse signal generating circuit is producedpulseControl the first NMOS tube N1 weeks
Phase property it is of short duration open, to soft start capacitor C carry out periodically of short duration charging so that raised voltage VraiseOn current potential is slow
Rise, after it rises to the 3rd NMOS tube N3 cut-in voltage, the 3rd NMOS tube N3 in error amplifier block is opened, and
Soft start voltage VoutWith raised voltage VraiseThe rising of current potential and slowly rise, and gradually stablize.
Work as t1Moment raised voltage VraiseCurrent potential continues to rise to the first schmitt inverter SINV1 upper threshold values VHWhen, its
Output voltage is overturn, and stop signal~stop is changed into low potential so that the second PMOS P2 is opened, raised voltage VraisePort quilt
High potential is pulled to, and pulse signal generation unit is closed by stop signal~stop, error amplifier block is realized defeated
The closing of the soft starting circuit gone out after stabilization.Raised voltage VraiseWith soft start voltage VoutAs shown in fig. 6, due to clock frequency
It is very big, therefore can not find out that the ladder of current potential rises on the time shaft of ms magnitudes, but continuous rising.
According to above-mentioned explanation, the soft starting circuit of the present embodiment is carried out by impulse generating unit to clock signal clk
Digital processing, has obtained small pulse signal, is realized using charhing unit by small pulse signal to soft start capacitor C
Slow charging, obtained the raised voltage V of slow risingraise, pass through the raised voltage V slowly risenraiseControl error is put
The soft start voltage of big device unit output slowly rises, and realizes soft start, and soft starting circuit after output voltage stabilization
Close.Soft start capacitor is reduced, is easy to integrated, and burr is effectively reduced, realizes smooth transition.
One of ordinary skill in the art can make various do not depart from originally according to these technical inspirations disclosed by the invention
The other various specific deformations and combination of essence are invented, these deformations and combination are still within the scope of the present invention.
Claims (2)
1. a kind of soft starting circuit based on pulse charge, it is characterised in that including pulse signal generation unit, charhing unit and
Error amplifier block,
The pulse signal generation unit include first with door (AND1), second with door (AND2), the first NAND gate (NAND1),
First buffer (BUFFER1) and the first NOT gate (INV1),
First is connected enable signal (VEN) with the first input end of door (AND1), and its output end output control signal (VE) simultaneously connects
Connect the first NAND gate (NAND1) first input end；The second input connection clock signal of first NAND gate (NAND1)
(clk), its output end connects the input of the first buffer (BUFFER1) and the input of the first NOT gate (INV1)；Second with
The first input end of door (AND2) connects the output end of the first buffer (BUFFER1), and its second input connects the first NOT gate
(INV1) output end, its output end output narrow pulse signal (Vpulse)；
The charhing unit includes the second phase inverter (INV2), the 3rd phase inverter (INV3), the first PMOS (P1), the 2nd PMOS
(P2), the first NMOS tube (N1), the second NMOS tube (N2), the first schmitt inverter (SINV1) and soft start capacitor (C) are managed,
The input of second phase inverter (INV2) connects the control signal (VE), and its output end connects the first PMOS (P1)
Grid；The input connection of 3rd phase inverter (INV3) enables signal (VEN), and its output end connects the grid of the second NMOS tube (N2)
Pole；The grid of first NMOS tube (N1) connects the narrow pulse signal (Vpulse), the leakage of its first PMOS of connection (P1) that drains
Pole, its source electrode connects drain electrode, the drain electrode of the second PMOS (P2) and the first schmitt inverter of the second NMOS tube (N2)
(SINV1) input and the output end output raised voltage (V for being used as the charhing unitraise)；First schmitt inverter
(SINV1) output end, which connects the grid of the second PMOS (P2) and exports stop signal, connects the pulse signal generation unit
In first with the second input of door (AND1)；Soft start capacitor (C) is connected between drain electrode and the ground of the second PMOS (P2), the
The source electrode of the source ground of two NMOS tubes (N2), the first PMOS (P1) and the second PMOS (P2) connects supply voltage (VDD)；
The positive input connection reference voltage (V of the error amplifier blockref), its negative input connection feedback voltage
(VFB), its control end connects the raised voltage (V that the charhing unit is producedraise), its output end output soft start voltage
(Vout)。
2. a kind of soft starting circuit based on pulse charge according to claim 1, it is characterised in that the error amplification
Device unit includes the 3rd PMOS (P3), the 4th PMOS (P4), the 5th PMOS (P5), the 6th PMOS (P6), the 7th
PMOS (P7), the 8th PMOS (P8), the 3rd NMOS tube (N3), the 4th NMOS tube (N4), the 5th NMOS tube (N5), the 6th
NMOS tube (N6), the 7th NMOS tube (N7), the 8th NMOS tube (N8) and reference current source (Iref),
The grid of 7th PMOS (P7) is used as the negative input of the error amplifier block, its 4th NMOS of connection that drains
Manage grid, the grid of the 5th NMOS tube (N5) and the drain electrode of (N4)；The grid of 8th PMOS (P8) amplifies as the error
The positive input of device unit, grid, the grid of the 7th NMOS tube (N7) and the drain electrode of its 8th NMOS tube (N8) of connection that drains；
7th PMOS (P7) is connected with the source electrode of the 8th PMOS (P8) and connects the drain electrode of the 6th PMOS (P6)；
The grid of 3rd NMOS tube (N3) is used as the control end of the error amplifier block, its 5th PMOS of connection that drains
(P5) grid, the grid of the 4th PMOS (P4) and drain electrode, its source electrode connect the drain electrode and the 6th of the 4th NMOS tube (N4)
The source electrode of NMOS tube (N6)；
The grid leak short circuit of 3rd PMOS (P3) and the grid for connecting the 6th PMOS (P6), the drain electrode of the 5th PMOS (P5) connect
Connect the drain and gate of the 6th NMOS tube (N6) and the drain electrode of the 8th NMOS tube (N8) and as the error amplifier block
Output end；Reference current source (Iref) be connected between drain electrode and the ground of the 3rd PMOS (P3)；
3rd PMOS (P3), the 4th PMOS (P4), the 5th PMOS (P5), the source electrode of the 6th PMOS (P6) connect power supply electricity
Press (VDD), the 4th NMOS tube (N4), the 5th NMOS tube (N5), the source electrode of the 7th NMOS tube (N7) and the 8th NMOS tube (N8) connect
Ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710451189.XA CN107276384A (en) | 2017-06-15 | 2017-06-15 | A kind of soft starting circuit based on pulse charge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710451189.XA CN107276384A (en) | 2017-06-15 | 2017-06-15 | A kind of soft starting circuit based on pulse charge |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107276384A true CN107276384A (en) | 2017-10-20 |
Family
ID=60066270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710451189.XA Pending CN107276384A (en) | 2017-06-15 | 2017-06-15 | A kind of soft starting circuit based on pulse charge |
Country Status (1)
| Country | Link |
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| CN (1) | CN107276384A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108376967A (en) * | 2018-02-23 | 2018-08-07 | 扬州海通电子科技有限公司 | A kind of multiple-channel output low voltage difference overcurrent protector |
| CN108631575A (en) * | 2018-06-27 | 2018-10-09 | 苏州裕太车通电子科技有限公司 | A kind of soft starting circuit applied to Switching Power Supply |
| CN113037275A (en) * | 2021-03-17 | 2021-06-25 | 东南大学 | Multi-input time domain analog signal width quantizer |
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| CN108376967A (en) * | 2018-02-23 | 2018-08-07 | 扬州海通电子科技有限公司 | A kind of multiple-channel output low voltage difference overcurrent protector |
| CN108631575A (en) * | 2018-06-27 | 2018-10-09 | 苏州裕太车通电子科技有限公司 | A kind of soft starting circuit applied to Switching Power Supply |
| CN108631575B (en) * | 2018-06-27 | 2023-11-28 | 裕太微电子股份有限公司 | Soft start circuit applied to switching power supply |
| CN113037275A (en) * | 2021-03-17 | 2021-06-25 | 东南大学 | Multi-input time domain analog signal width quantizer |
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