Invention content
It is an object of the invention in view of the above-mentioned drawbacks in the prior art, provide a kind of soft start electricity of Switching Power Supply
Road, it has the characteristics that simple in structure, dependable performance.
For achieving the above object, present invention employs following technical solutions:It is a kind of to be opened applied to the soft of Switching Power Supply
Dynamic circuit, the Switching Power Supply include electric power output voltage Vout, and the soft starting circuit includes the latch control being connected with each other
Circuit, charging delay circuit and logic control circuit, the output of the input terminal and logic control circuit of the latch control circuit
End is connected, and the output end of the latch control circuit is connected with the input terminal of logic control circuit, the charging delay circuit
Output end is connected with the input terminal of logic control circuit, and the logic control circuit includes first comparator COMP1, second compares
Device COMP2, the first NAND gate NAND1 and the second NAND gate NAND2, the first comparator COMP1 output ends with second with it is non-
The input terminal of door NAND2 connects, and the output end of the second comparator COMP2 is connected with the input terminal of the first NAND gate NAND1,
Input voltages of the electric power output voltage Vout as the logic control circuit.
In addition, the present invention also proposes following attached technical scheme:The second comparator COMP2 input positive terminals, negative terminal point
The output voltage Vcharge of switch power source output voltage Vout and the charging delay circuit, the first comparator are not connect
The input positive terminal of COMP1 connects reference voltage Vref, and the first comparator COMP1 input negative terminals and the second comparator COMP2 are defeated
Enter anode to be connected.
The output end of the first comparator COMP1 while the input terminal as the latch control circuit.
The latch control circuit includes the first PMOS transistor PM1, the first NMOS transistor NM1, the 2nd NMOS crystal
Pipe NM2, the source electrode of the first PMOS transistor PM1 are connected with power end VDD, the drain electrode of the first PMOS transistor PM1
It is connected with the drain electrode of NMOS transistor NM1, the leakage of the source electrode and the second NMOS transistor NM2 of the first NMOS transistor NM1
Extremely it is connected, the source electrode ground connection of the second NMOS transistor NM2.
The latch control circuit further includes phase inverter INV, the first capacitance C1 and the first current source I1, the first PMOS
The drain electrode of transistor PM1 is connected with phase inverter INV input terminals, and described one end first capacitance C1 is with the first PMOS transistor PM1's
Drain electrode connects, and the other end connects with the source electrode of the second NMOS transistor NM2.
The output end of the first comparator COMP1 respectively with the first PMOS transistor PM1, the first NMOS transistor
The grid of NM1 is connected.
The charging delay circuit includes the second PMOS transistor PM2, third NMOS transistor NM3, the 2nd PMOS
The source electrode of transistor PM2 is connected with supply voltage VDD, drain electrode and the second comparator COMP2 of the second PMOS transistor PM2
Input negative terminal be connected, the drain electrode of the third NMOS transistor NM3 connects with the drain electrode of the second PMOS transistor PM2, described
The source electrode of third NMOS transistor NM3 is grounded, the grid point of the second PMOS transistor PM2 and third NMOS transistor NM3
It is not connected with phase inverter INV input terminals.
It further includes the second capacitance C2 and the second current source 12, described one end second capacitance C2 and the second PMOS transistor
The drain electrode of PM2 is connected, and other end ground connection, the second capacitance C2 is charged by the second current source I2.
The switch power supply system further includes that feedback control passes through with driving circuit and driving tube DP, the soft starting circuit
Feedback control opens and closes driving tube DP with driving circuit.
Compared with the prior art, the advantage of the invention is that:Soft start is realized using a kind of simple on piece design method
Function had not both needed exterior and provides control signal, and need not generate additional clock signal yet.Simultaneously as using
The mode that intermittent charging is carried out to output realizes soft start function, does not need prodigious soft start charging capacitor, therefore can be with
Soft starting circuit is fully seated to realize in piece, significantly reduces the complexity of circuit design, improves integrated level, and reduce
Design cost.
Specific implementation mode
Technical solution of the present invention is further non-limitingly described in detail below in conjunction with preferred embodiment and its attached drawing.
It is for switching power circuit, including driving tube DP, rectifying tube DN, inductance L, capacitance C, feedback and drive as shown in Figure 1
Dynamic circuit and soft starting circuit.The input terminal of the driving tube DP output end that is connected with power vd D is connected with the input terminal of rectifier DN,
The output end of rectifier DN is grounded, and the control terminal of driving tube DP and the control terminal of rectifying tube DN are electric with driving with feedback control respectively
Road is connected.Inductance L is arranged between driving tube DP and switch power source output voltage Vout, and the one end capacitance C is connected with inductance L.Separately
One end is grounded.Electric power output voltage Vout slowly rises under soft starting circuit effect, avoids switch power supply system startup stage
Prodigious surge current is generated, output voltage is made to overshoot.
A kind of soft starting circuit as shown in Figure 2 and Figure 3, including latch control circuit 100, charging delay circuit 200 and logic
Control circuit 300, latch control circuit 100, logic control circuit 300 are connected with charging delay circuit 200 respectively, latch control
Circuit 100 is connected with logic control circuit 300.The input terminal of the latch control circuit 100 is defeated with logic control circuit 300
Outlet is connected, and the output end of the latch control circuit 100 is connected with the input terminal of logic control circuit 300, and the charging is prolonged
When circuit 200 output end be connected with the input terminal of logic control circuit 300.The input of latch control circuit 100 is as logic
The output signal latch_set of control circuit 300, input signal soft_ of its output as logic control circuit 300
start_en.The input of logic control circuit 300 is as the charge output voltage Vcharge of delay circuit 200, Switching Power Supply
The signal soft_start_en that output voltage Vout, reference level Vref and latch control circuit 100 export.
Latch control circuit 100 be used to latch soft starting circuit it is enabled whether state, latch control circuit 100 includes the
One PMOS transistor PM1, the first NMOS transistor NM1, the second NMOS transistor NM2, phase inverter INV, the first capacitance C1 and
One current source I1, the source electrode of the first PMOS transistor PM1 are connected with power end VDD, the drain electrode of the first PMOS transistor PM1 and the
The drain electrode of one NMOS transistor NM1 is connected, the drain electrode phase of the source electrode of the first NMOS transistor NM1 and the second NMOS transistor NM2
Even, the source electrode ground connection of the second NMOS transistor NM2, the drain electrode of the first PMOS transistor PM1 are connected with phase inverter INV.First electricity
Hold the one end C1 with the drain electrode of the first PMOS transistor PM1 to connect, the other end connects with the source electrode of the 2nd NMOS collectives pipe NM2.The
One one end current source I1 is connected with the first PMOS transistor PM1 drain electrodes, and the other end is connected with the second NMOS transistor NM2 source electrodes,
First current source I1 moves 1 initial voltage of node to low level, determines the original operating state of latch control circuit, ensures switch
Power-supply system works normally when starting.
Logic control circuit 300 include first comparator COMP1, the second comparator COMP2, the first NAND gate NAND1 and
The input positive terminal of second NAND gate NAND2, the second comparator COMP2 is switch power source output voltage Vout, the second comparator
The input negative terminal voltage of COMP2 is the output voltage Vcharge of charging delay circuit 200, the output end of the second comparator COMP2
It is connected with the first NAND gate NAND1, the grid phase of another input terminal of the first NAND gate NAND1 and the first NMOS transistor NM1
Even.The input positive terminal voltage of first comparator COMP1 is reference voltage Vref, the input negative terminal of first comparator COMP1 and the
The input positive terminal of two comparator COMP2 is connected, and output end is connected with the second NAND gate NAND2 input terminals, the second NAND gate NAND2
Another input terminal be connected respectively with the grid of the first PMOS transistor PM1 and the second NMOS transistor NM2.
The delay circuit 200 that charges includes the second PMOS transistor PM2, third NMOS transistor NM3, the second capacitance C2 and the
Two current source I2, the source electrode of the second PMOS transistor PM2 are connected with supply voltage VDD, the drain electrode of the second PMOS transistor PM2 with
The input negative terminal of second comparator COMP2 is connected, the leakage of the drain electrode and the second PMOS transistor PM2 of third NMOS transistor NM3
Pole connects, the source electrode ground connection of third NMOS transistor NM3, the grid of the second PMOS transistor PM2 and third NMOS transistor NM3
It is connected respectively with phase inverter INV input terminals.Second one end capacitance C2 is connected with the drain electrode of the second PMOS transistor PM2, the other end
Ground connection, the second current source I2 mono- terminate power end VDD, and the other end connects with the second PMOS transistor PM2 source electrodes.
It is illustrated in figure 4 soft starting circuit function chard, when system starts power up, the first PMOS transistor PM1 source electrodes
For hot end, the first PMOS transistor PM1 conductings, the first current source I1 moves the initial voltage of node 1 to low level, described
The voltage of signal soft_start_en is set to height, the grid of the first NMOS transistor NM1 by low level voltage by phase inverter INV
Extremely high level, the first NMOS transistor NM1 are connected, and switch power source output voltage Vout is less than reference voltage Vref at this time, the
One comparator COMP1 exports high level, and the second NMOS transistor NM2 grids are high level, and the second NMOS transistor NM2 is connected,
First PMOS transistor PM1 grids are also high level, the first PMOS transistor PM1 shutdowns so that signal soft_start_en is protected
It holds in high level, soft start function is opened.
Since the voltage of node 1 is low level, the grid of third NMOS transistor NM3 and the second PMOS transistor PM2's
Grid is low level, so third NMOS transistor NM3 is turned off at this time, the second PMOS transistor PM2 conductings, the second current source
I2 is to the second capacitance C2 chargings, and the second comparator COMP2 input negative terminal voltages Vcharge is slowly increased, when input positive terminal power supply
When output voltage Vout is less than input negative terminal voltage Vcharge, under being acted on by the second comparator COMP2, the node 2 of output
Voltage is low level, and the voltage through the first NAND gate NAND1 posterior nodal points 3 is high level, another input of the second NAND gate NAND2
It is high level to hold latch_set also, and the signal Vdrive voltages after the second NAND gate NAND2 are low level, signal
Vdrive opens the driving tube DP of Switching Power Supply after feedback control and driving circuit, and electric power output voltage Vout chargings make
Electric power output voltage Vout gradually rises, when the voltage Vout of output is more than voltage Vcharge, the voltage of node 2 at this time
For high level, since another input terminal of the first NAND gate NAND1 is high level, so the voltage of node 3 is low level, signal
Drive voltages are high level, and driving tube DP is turned off, and power supply pause charges to voltage Vout, when I2 pairs second of the second current source
Capacitance C2 charges so that voltage Vcharge is higher than voltage Vout again when, power supply starts to charge to voltage Vout again.It is opened soft
During dynamic, voltage Vout slowly rises, and avoids drastically surge current and voltage overshoot caused by charging.
When electric power output voltage Vout charges, if electric power output voltage Vout is higher than reference voltage Vref, first compares
Device COMP1 output voltages are low level, at this time the first PMOS transistor PM1 conductings, the second MOS transistor NM2 shutdowns, node 1
Voltage be raised, the grid of third MOS transistor NM3 and the second PMOS transistor PM2 are high level, third MOS transistor
NM3 is connected, and the second PMOS transistor PM2 shutdowns, the second capacitance C2 stops charging, and voltage Vcharge is pulled low, 1 position of node
The signal soft_start_en voltages that the inverted device INV of voltage is reversely exported afterwards are set to low, and the first MOS transistor NM1 grids are
Low level, the first MOS transistor NM1 shutdowns.The first PMOS transistor PM1, the first MOS transistor NM1, the 2nd MOS are brilliant at this time
Body pipe NM2, phase inverter INV, the first current source I1 and the first capacitance C1 constitute a latch, very due to the first current source I1
It is small, and have the first capacitance C1 as electric capacity of voltage regulation, ensure that node 1 is maintained at high electricity to Switching Power Supply in normal operation
It is flat, therefore signal soft_start_en is maintained at the normal work that low level does not interfere with system, so far soft start terminates, and opens
Powered-down source steady operation.
The invention has the advantages that realizing soft start function using simple on piece design method, system is not both needed
Outside provides control signal, need not also generate additional clock signal, simultaneously because using intermittent to output end progress
The method of charging does not need prodigious soft start charging capacitor, therefore can be fully seated to soft starting circuit to realize in piece, shows
Reduce circuit design complexity with writing, not only saves resource, and cost is relatively low, and circuit of the present invention is portable high, practical
Property is strong.
It is pointed out that the technical concepts and features of above-mentioned preferred embodiment only to illustrate the invention, its object is to
Those skilled in the art can understand the contents of the present invention and implements according to this, and the protection of the present invention can not be limited with this
Range.Any equivalent change or modification in accordance with the spirit of the invention should be covered by the protection scope of the present invention.