CN103645792B - Power management unit - Google Patents

Power management unit Download PDF

Info

Publication number
CN103645792B
CN103645792B CN201310632914.5A CN201310632914A CN103645792B CN 103645792 B CN103645792 B CN 103645792B CN 201310632914 A CN201310632914 A CN 201310632914A CN 103645792 B CN103645792 B CN 103645792B
Authority
CN
China
Prior art keywords
inverter
transistor
connected
signal
start
Prior art date
Application number
CN201310632914.5A
Other languages
Chinese (zh)
Other versions
CN103645792A (en
Inventor
王搏
王钊
王才宝
Original Assignee
无锡中感微电子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡中感微电子股份有限公司 filed Critical 无锡中感微电子股份有限公司
Priority to CN201310632914.5A priority Critical patent/CN103645792B/en
Publication of CN103645792A publication Critical patent/CN103645792A/en
Application granted granted Critical
Publication of CN103645792B publication Critical patent/CN103645792B/en

Links

Abstract

本发明公开了一种电源管理单元,包括:启动模块、被划分为至少两个启动组的多个电源转换器,启动控制模块;启动模块产生初始启动信号;启动控制信号基于所述初始启动信号通过延时的方式产生分别对应所述至少两个启动组的至少两个直接启动信号,并将所述直接启动信号发送给对应的启动组中的电源转换器;每个启动组中的电源转换器在接收到对应的直接启动信号后开始启动;不同直接启动信号之间相互间隔预定时间,以使得不同启动组中的电源转换器在不同的时间开始启动。 The present invention discloses a power management unit, comprising: a starting module is divided into a plurality of power converters of the at least two groups start, start control module; launch module generating an initial enable signal; start control signal based on the initial starting signal generating at least two signals corresponding to a direct start of said at least two groups started by a delayed manner, and the direct starting group corresponding starting signal to the power converter; start the power converter in each group It is started after receiving a direct enable signal corresponding; predetermined time interval from each other between different direct activation signal, so that different groups of starting the power converter started at different times. 本发明采用分组启动模式,能够减小PMU芯片上瞬时电流带来的冲击,降低PMU系统的安全隐患,同时也减小了PCB板上的大电源电容的使用,既节约了成本,又具有很好的实用性。 The present invention employs a packet start mode, it is possible to reduce the impact on the instantaneous current caused PMU chip, reducing security risks PMU system, while also reducing the use of large capacitance PCB power board, not only cost savings, but also has very good practicality.

Description

电源管理单元 Power management unit

技术领域 FIELD

[0001]本发明涉及电子电路领域,尤其涉及一种电源管理单元。 [0001] The present invention relates to electronic circuits, and more particularly relates to a power management unit.

背景技术 Background technique

[0002]电源管理单元(Power Management Unit,PMU)在片上系统(System On Chip,S0C)有着广泛的应用,主要用于为各个模块提供电源。 [0002] PMU (Power Management Unit, PMU) in the system (System On Chip, S0C) the sheet has been widely used, mainly used to provide power to each module. PMU—般由多个低压差线性稳压器(LowDropout Regulator,LD0)、直流-直流转换器DCDC及充电器charger等模块组成。 A plurality of generally PMU- low-dropout linear regulator (LowDropout Regulator, LD0), DC - DC converters and chargers, DCDC charger other modules. 如图1所示,一般在PMU中各个模块的启动信号OFF是由中的模块EN产生,图中LDO与DCDC的OFF信号都是由模块EN产生,在LDO与DCDC内部再由逻辑电路选择相应模块的开关,这样上电会同时有电源模块开启,导致产生瞬时冲击电流。 1, generally in the PMU modules start signal is OFF Central EN generation module, and FIG LDO DCDC the OFF signal EN is generated by the module, with a corresponding internal LDO DCDC then selected by a logic circuit switching module, so that the electric power module will also open, resulting in an instantaneous rush current.

[0003]在系统上电时,由于存在多路LDO与DCDC等模块同时启动的现象,电源模块会受到较大的瞬时电流冲击,这给PMU带来很大的安全隐患。 [0003] when the system power, due to the phenomenon of multi-channel LDO DCDC modules simultaneously started, the power module will be a large transient current impact, which gives the PMU has brought great security risk. 目前,主要在印刷电路板(Printed OnBoard,PCB)上采用大电容来保证系统的安全。 At present, the main printed circuit board (Printed OnBoard, PCB) using a large capacitance to secure the system. 然而,大电容的使用也带来了一系列的问题:首先,大电容不但要占用PCB板较大的空间,也不利于电路的设计;其次,大电容的使用给电路设计带来了较高的成本。 However, the use of large capacitors also brought a series of problems: First, large capacitance not only to take up a larger PCB space, is not conducive to the circuit design; secondly, the use of large capacitance to the circuit design brings higher the cost of.

发明内容 SUMMARY

[0004]本发明的目的是针对上述问题,提供了一种防止PMU多模块启动时较大电流对电路冲击的电源管理单元。 [0004] The object of the present invention is to solve the problem, there is provided a power management unit to prevent a large shock when the circuit current multi-module PMU starting.

[0005]为实现上述目的,本发明实施例提供了一种电源管理单元,其包括启动模块、被划分为至少两个启动组的多个电源转换器,启动控制模块; [0005] To achieve the above object, the present invention provides a power management unit, which includes a starting module is divided into a plurality of power converters of the at least two groups start, start control module;

[0006]所述启动模块产生初始启动信号; [0006] The startup module generates an initial enable signal;

[0007]所述启动控制信号基于所述初始启动信号通过延时的方式产生分别对应所述至少两个启动组的至少两个直接启动信号,并将所述直接启动信号发送给对应的启动组中的电源转换器; [0007] The start signal is generated at least two control signals respectively corresponding to a direct start of said at least two groups started by a delayed manner based on the initial starting signal, and the corresponding direct start signal to start the group the power converter;

[0008]每个启动组中的电源转换器在接收到对应的直接启动信号后开始启动; [0008] Each group start the power converter started after receiving a direct enable signal corresponding;

[0009]不同直接启动信号之间相互间隔预定时间,以使得不同启动组中的电源转换器在不同的时间开始启动。 [0009] each predetermined time interval between different direct activation signal, so that different groups of starting the power converter started at different times.

[0010]优选地,所述直接启动信号中有一个与所述初始启动信号之间的延时为零。 [0010] Preferably, the direct signal has a start delay between the start of the initial signal is zero.

[0011]优选地,所述启动控制模块直接将所述初始启动信号作为第一直接启动信号输出,并将该第一直接启动信号输出给其对应的一个启动组中的电源转换器, [0011] Preferably, the start control module directly to the initial start enable signal is directly output as the first signal and the first enable signal is directly output to a corresponding group of starting the power converter,

[0012]所述启动控制模块包括至少一个延时单元,所述延时单元的输入端接收所述初始启动信号,所述延时单元的输出端输出第二直接启动信号,并将该第二直接启动信号输出给其对应的一个启动组中的电源转换器,每个延时单元对输入的信号进行预定时间的延时。 [0012] the start control module comprises at least one delay unit, said delay unit receiving input of said initial activation signal, said delay unit outputting a second output terminal of the direct enable signal, and the second direct start signal to start a corresponding group of power converters, each delay unit to delay the input signal a predetermined time.

[0013]优选地,其特征在于,所述延时单元为多个并且相互级联,第一个延时单元接收所述初始启动信号,每个延时单元输出一个直接启动信号。 [0013] Preferably, wherein said delay unit and a plurality of mutually cascaded first delay unit receives the initial activation signal, each delay unit outputs a start signal directly.

[0014]所述延时单元包括第一反相器、第二反相器、电容、反馈电路; [0014] The delay unit comprises a first inverter, a second inverter, a capacitor, a feedback circuit;

[0015]所述第一反相器的输入端作为延时单元的输入端接收输入信号,所述第一反相器的输出端与所述第二反相器的输入端连接于公共节点A,所述第二反相器的输出端作为延时单元的输出端输出信号; [0015] The input of the first inverter receiving an input signal as an input terminal of the delay unit, the input of the output of the first inverter and the second inverter is connected to a common node A , the second output terminal of the inverter as a delay unit, a signal output terminal;

[0016]所述电容连接在公共节点A与地之间; [0016] The capacitor is connected between the common node A and the ground;

[0017]所述反馈电路包括两个控制端和两个连接端,两个连接端分别与所述公共节点和电源端相连,两个控制端分别与第一反相器的输入端和第二反相器的输出端相连,当第一反相器的输入端和第二反相器的输出端同时为第一电平时将公共节点与电源端相连,当第一反相器的输入端和第二反相器的输出端不同时为第一电平时,将公共节点A与电源端相连。 [0017] The feedback circuit comprises two control terminals and two connection terminals, two connection ends connected to the common node and a power supply terminal, respectively, are two control terminals of the first inverter and a second input terminal the output terminal of the inverter is connected to the output terminal when the input of the first inverter and a second inverter connected to the common node while usually the first electrical power supply terminal, when the input of the first inverter, and the output terminal of the second inverter is not the same level, the common node a is connected to a first power supply terminal is electrically.

[0018]优选地,其还包括有整形电路,所述整形电路的输入端连接第二反相器的输出端,整形电路的输出端作为延时单元的输出端。 [0018] Preferably, it further comprises a shaping circuit, a shaping circuit connected to the output terminal of the input terminal of the second inverter, the output of the shaping circuit as an output of the delay unit.

[0019]所述第一反相器包括电流源、第一晶体管、第二晶体管; [0019] The first inverter includes a current source, a first transistor, a second transistor;

[0020]所述第一晶体管的栅极与所述第二晶体管的栅极相连接作为第一反相器的输入端,所述第一晶体管的源极经过所述电流源连接电源,所述第二晶体管的源极接地,所述第一晶体管和第二晶体管的漏极相连接作为所述第一反相器的输出端。 [0020] The gate of the first transistor and the gate of the second transistor is connected to an input terminal of the first inverter, the source of the first transistor is connected to the power supply through the current source, the source of the second transistor is grounded, the drain of the first transistor and a second transistor connected as the output terminal of the first inverter.

[0021 ]所述第二反相器包括第五晶体管和第六晶体管; [0021] The second inverter comprises a fifth transistor and a sixth transistor;

[0022]所述第五晶体管栅极和第六晶体管栅极相连接作为所述第二反相器信号输入端,所述第五晶体管漏极和第六晶体管漏极相连接作为所述第二反相器信号的输出端输出信号,所述第六晶体管源极接地,第五晶体管源极连接电源,所述第一反相器的输出端与所述第二反相器输入端相连接。 [0022] The gate of the fifth transistor and the sixth transistor is connected to a gate of the second inverter signal input terminal, the drain of the fifth transistor and the sixth transistor is connected to a drain as the second output of the output signal of the inverter signal, the sixth source-grounded transistor, the fifth transistor source connected to the power output of the first inverter and the second inverter connected to the input.

[0023]优选地,所述反馈电路包括第三晶体管和第四晶体管; [0023] Preferably, the feedback circuit comprises a third transistor and a fourth transistor;

[0024]优选地,所述第三晶体管的栅极作为反馈电路的一个控制端与所述第一反相器输入端相连接,所述第四晶体管的栅极作为反馈电路的一个控制端与所述第二反相器输出端相连,所述第三晶体管漏极和第四晶体管源极相连接,所述第四晶体管漏极作为反馈电路的一个连接端与公共节点A相连接,所述第三晶体管源极作为反馈电路的一个连接端连接电源; A gate [0024] Preferably, the third transistor is connected to the first input terminal of inverter control terminal as a feedback circuit, a gate of the fourth transistor control terminal as a feedback circuit and said second inverter output terminal is connected to the drain of the third transistor and a fourth transistor with a source connected to the drain of the fourth transistor is connected as a feedback circuit and the terminal a is connected to a common node, the a third transistor source connected to a feedback circuit connected to the power supply terminal;

[0025]当所述第一反相器输入端和所述第二反相器输出端同时为第一电平时,所述第三晶体管和所述第四晶体管导通,电源和公共节点A相连接,当所述第一反相器输入端和所述第二反相器输出端不同时为第一电平时,所述第三晶体管和所述第四晶体管断开。 [0025] When the first inverter input terminal and output terminal of the second inverter simultaneously at the first level, the third transistor and the fourth transistor is turned on, the node A and the common power supply connection, when said first inverter input terminal and output terminal of the second inverter are not simultaneously at the first level, the third transistor and said fourth transistor is turned off.

[0026] 优选地,所述第一电平为低电平。 [0026] Preferably, the first level is low.

[0027]本发明的有益效果是:采用本发明的电源管理电路,采用分组启动模式,能够有效减小PMU芯片上瞬时电流带来的冲击,降低了PMU系统的安全隐患,同时也减小了PCB板上的大电源电容的使用,既节约了成本,又具有很好的实用性。 [0027] Advantageous effects of the invention are: The power management circuit according to the present invention, using the packet start mode, the PMU is possible to effectively reduce the impact caused by the instantaneous current chip, reducing security risks PMU system, but also reduces large capacitance PCB power board, not only cost savings, but also has good usability.

附图说明 BRIEF DESCRIPTION

[0028]图1为本发明现有技术中PMU系统开关控制示意图; [0028] FIG. 1 prior art schematic diagram of the switching control system PMU invention;

[0029]图2为本发明一实施例中电源管理单元示意图; [0029] Fig 2 a schematic view of managing a power supply unit according to the present embodiment of the invention;

[0030]图3为本发明一实施例中延时单元示意图; [0030] FIG. 3 a schematic diagram of an embodiment of the invention, the delay unit;

[0031]图4为本发明一实施例中延时单元电路图; [0031] Figure 4 a circuit diagram of a delay unit in the embodiment of the present invention;

[0032]图5为本发明一实施例延时启动信号的波形图。 [0032] FIG. 5 delayed start signal waveform diagram illustrating an embodiment of the invention.

具体实施方式 Detailed ways

[0033]下面通过附图和实施例,对本发明的技术方案做进一步的详细描述。 [0033] The following drawings and embodiments, detailed description of the further aspect of the present invention.

[0034]图2示出了本发明一施例电源管理单元示意图。 [0034] FIG. 2 shows a schematic diagram of managing an embodiment of the present invention a power supply unit.

[0035]如图2所示,在实施例中的电源管理单元中,存在多个电源转换器UXKDCDC等电路模块,考虑到电源管理单元的面积与冲击电路的折中,根据启动瞬时态电流把电源模块分为不同启动组,保证每个启动组上的瞬时电流不超过额定值。 [0035] 2, in the embodiment of the power management unit embodiment, there are a plurality of power converters and other circuits UXKDCDC module, taking into account the impact of trade-off area of ​​the power management circuit unit, according to the starting transient state the current the power module is divided into groups of different promoters, to ensure instantaneous current on each startup group rated value. 其中,PMU中各个模块的启动信号由启动模块20产生。 Wherein, PMU start signal generated by each module startup module 20.

[0036]启动控制模块10利用启动模块20提供的初始启动信号OFF产生直接启动信号(也可以被称为延迟启动信号)。 [0036] start control module 10 generates a direct enable signal (also referred to as a delayed start signal may be) with the initial start signal OFF startup module 20 is provided. 本实施例中,优选的将D⑶C21与LD021、D⑶C22与LD022、D⑶C23与LD023依次分为三个启动组。 In this embodiment, the preferred D⑶C21 and LD021, D⑶C22 and LD022, D⑶C23 LD023 and sequentially divided into three groups to start. 其中,启动模块20发出控制的启动信号OFF经过启动控制模块20产生信号0FF_delay0。 Wherein the enabling module 20 issues a start signal via the start OFF control module generates a control signal 0FF_delay0 20. 其中,信号0FF_delay0可以是不经过延时的信号,信号0FF_delayO发送给第一启动组DCDC21与LD021,0FF信号经过启动控制模块20产生启动信号0FF_delayl,并将其提供给到达第二启动组D⑶C22与LD022,0FF信号经过启动控制模块20产生直接启动信号0FF_delay2,并将其提供给第三启动组DCDC23与LD023。 Wherein, the signal may be 0FF_delay0 without signal delay, a signal is sent to a first promoter 0FF_delayO group DCDC21 LD021,0FF signal through the control module generates a start enable signal 0FF_delayl 20, and supplies it to the second set of start and LD022 D⑶C22 , 0FF start signal through the control module 20 generates a start signal directly 0FF_delay2, and supplies it to the third group DCDC23 start and LD023. 其中,启动控制模块10可以包括多个级联的延时单元30,每一级联的直接启动信号比上一级的直接启动信号延时10ys左右。 Wherein the start control module 10 may include a plurality of cascaded delay units 30, each cascade activation signal than the direct signal is a start delay directly around 10ys. 当然,在其他实施例中,启动控制模块10也可以只包括一个延时单元30。 Of course, in other embodiments, the startup control module 10 may also include a delay unit 30 only.

[0037]每个启动组在收到对应的延时启动信号后才开始启动,并且由于各个延时启动信号之间相隔一定时间(本发明实施例中优选10ys左右),因此不同启动组中的电源转换器在不同的时间开始启动,这样可以有效降低电源管理电路上电时的瞬时电流冲击过大的问题。 [0037] Each group started to start only after receiving the corresponding delayed activation signal, and since each of the delay between the start signal separated by a time (in the preferred embodiment of the present invention about embodiments 10ys), so different promoters groups the power converter started at different times, which can effectively reduce the impact of instantaneous current power management circuit when an electrical problem of excessive.

[0038I图3示出了本发明一实施例图2中启动控制模块10中的延时单元30的电路示意图。 [0038I FIG. 3 shows a schematic circuit diagram of the present invention of FIG. 2 to start the control module 10 is a delay unit 30 embodiment.

[0039] 如图3所示,延时单元30包括:反相器31,反馈电路32,反相器33,整形电路34和电容35。 [0039] shown in FIG delay unit 330 comprises: an inverter 31, a feedback circuit 32, an inverter 33, shaping circuit 34 and a capacitor 35.

[0040]反相器31的输入端作为延时单元30的输入端接收输入信号,反相器31的输出端与反相器33的输入端连接于公共节点A,反相器33的输出端作为延时单元30的输出端输出信号。 Input [0040] The inverter 31 as a delay unit input terminal 30 receives an input signal, the input terminal of the inverter output of the inverter 31 is connected to a common node 33 A, the output of the inverter 33 signal as the output terminal of the delay unit 30.

[0041 ]电容35连接在公共节点A与地之间。 [0041] The capacitor 35 is connected between the common node A and ground.

[0042]反馈电路32包括两个控制端和两个连接端,两个连接端分别与所述公共节点和电源端相连,两个控制端分别与反相器31的输入端和反相器33的输出端相连,当反相器31的输入端和反相器33的输出端同时为低电平时将公共节点A与电源端相连,当反相器31的输入端和反相器33的输出端不同时为低电平时,将公共节点A与电源端相连。 [0042] The feedback circuit 32 includes two control terminals and two connection ends, two ends are connected to the common node and a power supply terminal is connected, respectively two control terminals and the input terminal of the inverter 31, inverter 33 connected to the output, when the output of the input inverter 33 and the inverter 31 is low while the common node is connected to the power supply terminal a and the output of the inverter 31 and the input terminal of inverter 33 when ends are not simultaneously low, the node A is connected to the common power supply terminal.

[0043]在一个实施例中,启动模块20发出初始启动信号OFF进入反相器31,当PMU发出的初始启动信号OFF为低电平时,电流源发出的小电流可经过反相器31为电容35充电,电容35的充电过程使信号OFF得到延时。 [0043] In one embodiment, the startup module sends an initial actuation signal 20 enters the inverter 31 OFF, when the initial small current start signal issued by the PMU OFF is a low level, the current source may be emitted through the inverter 31 to capacitor 35, the charging process of the capacitor 35 to give a signal OFF delay. 反馈电路32为延时单元30提供一个正反馈,减少由于电路中较大电流的涌入而在电流与接地之间产生大量噪声的现象。 The feedback circuit 32 a delay unit 30 to provide positive feedback to reduce the circuit phenomenon due to the influx of a large amount of noise generated by the current between the current and the ground is. PMU发出的低电平信号OFF经过反相器31之后变为高电平信号OFF,高电平信号OFF经过反相器33的作用后变为低电平信号OFF,并且输出的低电平信号OFF经过整形电路34作用进行整形,然后延时单元30输出延时启动信号0FF_delay。 Low-level OFF signal sent via the PMU OFF signal becomes a high level after the inverter 31, a high level signal after the OFF action of inverter 33 becomes a low level OFF signal, and outputs a low level signal OFF action after shaping circuit 34 for shaping and delay unit 30 outputs the start signal delayed 0FF_delay.

[0044]如图4所示是本发明图3延时单元30的电路图。 [0044] As shown in FIG. 4 is a circuit diagram of the present invention, the delay unit 30 3. 其中: among them:

[0045] 反相器31,包括PMOS型晶体管Ml、匪OS型晶体管M2和电流源I,用于信号的反转。 [0045] The inverter 31 includes PMOS transistors of Ml, M2 bandit OS type transistor and the current source I, for inverting the signal. 其中,Ml与M2的栅极相连接并作为反相器31的输入端,Ml与M2的漏极相连接并作为反相器31的输出端。 Wherein, the gate of Ml and M2 is connected to an input terminal of the inverter 31, and the drain of Ml and M2 is connected to an output terminal of the inverter 31. 电流源I的一端分别与PMOS型晶体管M3、M5的源极及整形电路34相连接,一端与Ml的源极相连接,电容的一端分别与Ml、M2的漏极及PMOS型晶体管M5和匪OS型晶体管M6的栅极相连接,一端接地。 End of the current source I are respectively the PMOS transistor M3, a source electrode of M5 and the shaping circuit 34 is connected to one end of the source electrode Ml is connected to one end of the capacitor, respectively Ml, M2 and the drain of the PMOS transistor M5 and bandit OS gate type transistor M6 is connected to one end grounded. PMU的启动信号OFF从反相器31的输入端输入,从输出端输出。 PMU start signal OFF, the output from the input terminal of the inverter 31 from the output terminal. 当启动信号OFF电平变低时,Ml导通,电源经过Ml为电容35充电,电源为电容35的充电用于启动信号OFF的延时。 When the start signal is OFF level becomes low, Ml is turned on, the power supply capacitor 35 is charged through Ml, power for charging of the capacitor 35 for delaying the start signal OFF. 电容35的一端连接公共节点A,一端接地,其大小可以用来调节延时时间,本发明实施例中启动信号OFF的延时时间为10ys左右。 One end of the capacitor 35 is connected to a common node A, an end of the ground, the size of which can be used to adjust the delay time, the delay time in Example embodiments OFF start signal is approximately 10ys present invention.

[0046] 反馈电路32,包括PMOS型晶体管M3和PMOS型晶体管M4,M3的漏极与M4的源极相连接形成反馈电路32。 [0046] The feedback circuit 32, the PMOS transistors comprising the PMOS transistors M3 and M4, the source and the drain of M3, M4 is connected to the feedback circuit 32 is formed. 其中,M3的栅极分别与Ml和M2的栅极相连接,M2的栅极分别与PMOS型晶体管M5和NMOS型晶体管M6的漏极相连接。 Wherein, M3 are respectively the gate connected to the gate of Ml and M2, the gate of M2 are connected to the drain of the PMOS transistor M5 and NMOS transistor M6. M2的漏极连接公共节点A。 The drain of M2 is connected to a common node A. 反馈电路32用于为延时单元30提供正反馈,用于减少电路中接地反弹(ground bounce)现象对电路造成的影响。 The feedback circuit 32 to delay unit 30 for providing positive feedback, a circuit for reducing ground bounce impact (ground bounce) caused by the phenomenon of the circuit. 当反相器31的输入端信号和反相器33输出端信号都为低电平时,反馈电路32导通。 When the inverter input signal and the signal at the output 33 of the inverter 31 are low, the feedback circuit 32 is turned on.

[0047]反相器33,包括PMOS型晶体管M5和NMOS型晶体管M6。 [0047] The inverter 33 includes the PMOS transistor M5 and NMOS transistor M6. 其中,M5与M6的栅极相连接作为反相器33的输入端,M5与M6的漏极相连接并作为反相器33的输出端,M6的源极接地。 Wherein, M5 and M6 is connected to a gate input of the inverter 33, and the drain of M5 and M6 is connected to an output terminal of the inverter 33, the source is grounded M6. PMU发出的启动信号OFF从反相器31的输出端输出后,经过延时得到延时启动信号OFF并进入反相器31的输入端,延时启动信号OFF经过反相器33的作用反转,然后从反相器33的输出端输出。 The PMU OFF start signal sent from the output of the inverter 31 output, after a brief delay to obtain a delayed start signal is OFF and into the input of the inverter 31, the delay through the OFF action of the start signal of the inverter 33 is inverted and then output from the output terminal of the inverter 33.

[0048]整形电路34,其中一端到连接反相器33的输出端,一端作为延时单元30的输出端,用于延时启动信号的输出,用于延时启动信号OFF的整形。 [0048] The shaping circuit 34, wherein one end is connected to the output terminal of inverter 33, one end of an output terminal of the delay unit 30 for outputting the delayed start signal, for delaying the start signal OFF shaping. 实施例中输出延时启动信号0FF_delay ο Example output enable signal delayed 0FF_delay ο

[0049]如图5所示是本发明实施例中延时启动信号的波形图。 [0049] The embodiment shown in FIG. 5 is a waveform diagram of signals delayed start embodiment of the present invention. 实施例中,第一启动组DCDC21与LD021电路模块经过延时单元30,输出的延时启动信号0FF_delay0可以与启动信号OFF同步,也可以延时输出,本实施例优选0FF_delay0与启动信号同步,即没有延时。 Embodiment, a first set of start and LD021 DCDC21 circuit module 30 via a delay unit, the delayed activation signal output may be synchronized with 0FF_delay0 OFF start signal, the output may be delayed, with the present preferred embodiment 0FF_delay0 synchronization start signal, i.e., there is no delay. 第二启动组D⑶C32与LD032电路模块经过一级的延时单元30,即经过延时单元30的一次延时,其输入的启动信号OFF为0FF_delayl,比第一启动组DCDC31与LD031模块收到的启动信号OFF延时10ys左右。 The second set of start and LD032 D⑶C32 circuit module via a delay unit 30, i.e., through a delay unit 30 delays the start signal input is OFF 0FF_delayl, receive than the first set of start and LD031 module DCDC31 OFF delay start signal about 10ys. 第三启动组D⑶C33与LD033模块输入的0FF_delay2信号经过了两级的延时单元30延时,其输入的启动信号OFF比第二组DCDC32与LD032模块输入的启动信号OFF延时10ys左右。 0FF_delay2 start signal of the third group and the LD033 D⑶C33 module inputs through a two-stage delay unit 30 delays its input start signal OFF delay than about 10ys start signal OFF LD032 and a second set of DCDC32 module inputs. 可以说的是,实施例中利用本发明提供的包括多级延时单元30的启动控制模块10可以很好的避免较大电流对多个模块同时启动带来的电流冲击。 It can be said that the use of a multi-stage embodiment of the present invention provides a delay unit activation control module 30 can be a good 10 to avoid large current surge current caused by a plurality of modules will start.

[0050]根据本发明上述的实施例可以看出,本发明的电源管理单元可以对多个电路转换器模块同时启动时提供电路保护,限制瞬时较大电流对电路的冲击,同是也避免了PCB上较大电容的使用,进而可以降低电路设计的成本及节约PCB板的使用空间。 [0050] As can be seen in accordance with the present invention, the above-described embodiment, the power management unit according to the present invention may provide a plurality of circuits to start while the converter circuit protection module, an instantaneously large current limiting impact on the circuit, the same is also to avoid the the use of larger capacitance in the PCB, and thus can reduce the cost of circuit design and economical use of PCB space.

[0051]以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 [0051] The foregoing specific embodiments, objectives, technical solutions, and advantages of the invention will be further described in detail, it should be understood that the above descriptions are merely specific embodiments of the present invention, but not intended to limit the scope of the present invention, all within the spirit and principle of the present invention, any changes made, equivalent substitutions and improvements should be included within the scope of the present invention.

Claims (8)

1.一种电源管理单元,其包括启动模块、被划分为至少两个启动组的多个电源转换器,其特征在于,其包括启动控制模块; 所述启动模块产生初始启动信号; 所述启动控制模块直接将所述初始启动信号作为第一直接启动信号输出,并将该第一直接启动信号输出至一个启动组中的多个电源转换器,以便所述一个启动组中的多个电源转换器在接收到所述第一直接启动信号后开始启动; 所述启动控制模块包括至少一个延时单元,所述延时单元的输入端接收所述初始启动信号,并在对所述初始启动信号进行预定时间的延时后产生第二直接启动信号,并将所述第二直接启动信号输出至另一个启动组中的多个电源转换器,以便所述另一个启动组中的多个电源转换器在接收到所述第二直接启动信号后开始启动; 每个所述延时单元均包括第一反相器、第二反相器 1. A power management unit, which includes a starting module is divided into a plurality of at least two power converters start groups, characterized in that it comprises a start control module; launch module generates the initial enable signal; the promoter the control module of the initial activation signal directly to the first output signal as a direct start, and the first enable signal is directly output to a plurality of power converters start the group, the plurality of power supply to said converter group in a starting is started after receiving the first enable signal directly; the start control module comprises at least one delay unit, said delay unit receiving input of said initial activation signal, the start signal and initial after a predetermined delay time to generate a second direct enable signal and said second enable signal is directly output to the other group of a plurality of starting power converter to a plurality of other power converter startup group is started after receiving the second enable signal directly; each of said delay unit comprises a first inverter, a second inverter 电容、反馈电路; 所述第一反相器的输入端作为延时单元的输入端接收输入信号,所述第一反相器的输出端与所述第二反相器的输入端连接于公共节点A,所述第二反相器的输出端作为延时单元的输出端输出信号; 所述电容连接在公共节点A与地之间; 所述反馈电路包括两个控制端和两个连接端,两个连接端分别与所述公共节点和电源端相连,两个控制端分别与第一反相器的输入端和第二反相器的输出端相连,当第一反相器的输入端和第二反相器的输出端同时为第一电平时将公共节点与电源端相连,当第一反相器的输入端和第二反相器的输出端不同时为第一电平时,将公共节点A与电源端相连。 Capacitive feedback circuit; said first input terminal of the inverter as an input terminal of the delay unit receives an input signal, an input terminal an output terminal of the first inverter and the second inverter is connected to a common node a, the output of the second inverter output terminal as an output signal of the delay unit; said capacitor is connected between the common node a and the ground; the feedback circuit comprises two control terminals and two connection terminals , two ends are connected to the common node and a power supply terminal is connected to two control terminals coupled to the output of the second inverter and the input terminal of the first inverter, respectively, when the input of the first inverter and an output terminal of the second inverter while normally electrically connecting the common node to a first power supply terminal, an output terminal when the input of the first inverter and the second inverter is not the same as the first electrical usually, the A common node is connected to the power supply terminal.
2.如权利要求1所述的电源管理单元,其特征在于,所述直接启动信号中有一个与所述初始启动信号之间的延时为零。 Said power management unit as claimed in claim 1, wherein said direct signal has a start delay between the start of the initial signal is zero.
3.如权利要求1所述的电源管理单元,其特征在于,所述至少一个延时单元相互级联,第一个延时单元接收所述初始启动信号,每个延时单元输出一个直接启动信号。 3. The power management unit according to claim 1, wherein said at least one delay units are cascaded, the first delay unit receives the initial activation signal, each delay unit outputs a direct start signal.
4.如权利要求1所述的电源管理单元,其特征在于,其还包括有整形电路,所述整形电路的输入端连接第二反相器的输出端,整形电路的输出端作为延时单元的输出端。 4. The power management unit according to claim 1, characterized in that it further comprises a shaping circuit, the input of the shaping circuit is connected to the output terminal of the second inverter, the output of the shaping circuit as a delay unit an output terminal.
5.如权利要求1所述的电源管理单元,其特征在于, 所述第一反相器包括电流源、第一晶体管、第二晶体管; 所述第一晶体管的栅极与所述第二晶体管的栅极相连接作为第一反相器的输入端,所述第一晶体管的源极经过所述电流源连接电源,所述第二晶体管的源极接地,所述第一晶体管和第二晶体管的漏极相连接作为所述第一反相器的输出端。 The power management unit as recited in claim 1, wherein the first inverter includes a current source, a first transistor, a second transistor; a gate of the first transistor and the second transistor a gate connected to an input terminal of the first inverter, the source of the first transistor is connected to the current source through the power source of the second transistor is grounded, the first transistor and the second transistor an output terminal connected to a drain as the first inverter.
6.如权利要求1所述的电源管理单元,其特征在于, 所述第二反相器包括第五晶体管和第六晶体管; 所述第五晶体管栅极和第六晶体管栅极相连接作为所述第二反相器信号输入端,所述第五晶体管漏极和第六晶体管漏极相连接作为所述第二反相器信号的输出端输出信号,所述第六晶体管源极接地,第五晶体管源极连接电源,所述第一反相器的输出端与所述第二反相器输入端相连接。 6. The power management unit as recited in claim 1, wherein the second inverter comprises a fifth transistor and a sixth transistor; the fifth transistor and the gate of the sixth transistor is connected to a gate of the said second signal input terminal of the inverter, the drain of the fifth transistor and the drain of the sixth transistor is connected to an output terminal as an output signal of the second inverter signal, said sixth transistor and a source grounded, a first five transistor source connected to the power output of the first inverter and the second inverter connected to the input.
7.如权利要求1或5所述的电源管理单元,其特征在于, 所述反馈电路包括第三晶体管和第四晶体管; 所述第三晶体管的栅极作为反馈电路的一个控制端与所述第一反相器输入端相连接,所述第四晶体管的栅极作为反馈电路的一个控制端与所述第二反相器输出端相连,所述第三晶体管漏极和第四晶体管源极相连接,所述第四晶体管漏极作为反馈电路的一个连接端与公共节点A相连接,所述第三晶体管源极作为反馈电路的一个连接端连接电源; 当所述第一反相器输入端和所述第二反相器输出端同时为第一电平时,所述第三晶体管和所述第四晶体管导通,电源和公共节点A相连接,当所述第一反相器输入端和所述第二反相器输出端不同时为第一电平时,所述第三晶体管和所述第四晶体管断开。 7. The power management unit as claimed in claim 1 or claim 5, wherein said feedback circuit comprises a third transistor and a fourth transistor; a gate of the third transistor as a feedback circuit to the control terminal a first inverter connected to the input gate of the fourth transistor is connected to the output terminal of the second inverter as a feedback circuit of a control terminal, the drain of the third transistor and a fourth transistor source It is connected to the drain of the fourth transistor is connected as a terminal of the feedback circuit is connected to the common node a, the third transistor source connected to a power source terminal connected to a feedback circuit; and when said first inverter input terminal and output terminal of the second inverter simultaneously at the first level, the third transistor and the fourth transistor is turned on, and the common power supply is connected to the node A, when said first inverter input terminal and said second inverter output terminal is not the same level, the third transistor and the fourth transistor is electrically disconnected first.
8.如权利要求7所述的电源管理单元,其特征在于,所述第一电平为低电平。 8. The power management unit according to claim 7, wherein said first level is low.
CN201310632914.5A 2013-11-30 2013-11-30 Power management unit CN103645792B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310632914.5A CN103645792B (en) 2013-11-30 2013-11-30 Power management unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310632914.5A CN103645792B (en) 2013-11-30 2013-11-30 Power management unit

Publications (2)

Publication Number Publication Date
CN103645792A CN103645792A (en) 2014-03-19
CN103645792B true CN103645792B (en) 2017-01-04

Family

ID=50251020

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310632914.5A CN103645792B (en) 2013-11-30 2013-11-30 Power management unit

Country Status (1)

Country Link
CN (1) CN103645792B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106788485B (en) * 2016-11-29 2019-05-14 华南理工大学 A kind of low-power transmitters

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200413896A (en) * 2003-01-24 2004-08-01 Mitac Technology Corp Power management and control method of power supply and device thereof
CN101000518A (en) * 2006-01-13 2007-07-18 英业达股份有限公司 System for controlling hard disk sequential start
CN202475390U (en) * 2011-10-24 2012-10-03 中兴通讯股份有限公司 Apparatus for controlling powering-on order of plurality of power supplies

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7028200B2 (en) * 2002-05-15 2006-04-11 Broadcom Corporation Method and apparatus for adaptive power management of memory subsystem

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200413896A (en) * 2003-01-24 2004-08-01 Mitac Technology Corp Power management and control method of power supply and device thereof
CN101000518A (en) * 2006-01-13 2007-07-18 英业达股份有限公司 System for controlling hard disk sequential start
CN202475390U (en) * 2011-10-24 2012-10-03 中兴通讯股份有限公司 Apparatus for controlling powering-on order of plurality of power supplies

Also Published As

Publication number Publication date
CN103645792A (en) 2014-03-19

Similar Documents

Publication Publication Date Title
Le et al. A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19 W/mm 2 at 73% efficiency
TW201320566A (en) Cascade frequency converter and power unit with bypass module thereof
TW201351881A (en) Hybrid on-chip regulator for limited output high voltage
KR20160066034A (en) Feedback control in hybrid voltage regulators
Luo Switched-capacitorized DC/DC converters
CN101090203A (en) On-line uninterrupted UPS system
US8125806B2 (en) Multi-stage switching power supply
CN203086213U (en) Rapid charger and mobile power supply with the charger
US9843262B2 (en) Systems and methods for switched-inductor integrated voltage regulators
CN105429247B (en) One kind of glasses vr charging apparatus and the mobile terminal
WO2012129892A1 (en) Power battery simulation system
US9484755B2 (en) In-vehicle charging control device, vehicle charging system and vehicle
CN101764517B (en) Positive-negative dual power supply system based on single input
CN102158082B (en) Power supply management system with multipath output
Senanayake et al. Multiphase voltage regulator module with current amplification and absorption technique
CN204145302U (en) Multi-transformer-parallel-connection wide-voltage-input DC-DC switching power supply circuit
CN101783582A (en) Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time
CN203434863U (en) Power supply circuit and power supply having same power supply circuit
CN101631028B (en) Time-sharing starting method and time-sharing starting device of communication system
CN101577537B (en) Relaxation oscillator
CN103368403B (en) The control device employed in the switching power supply system
JP2015505236A (en) Device and method for controlling a pulse output
CN104426344A (en) Snubber circuit and buffering method for snubber circuit
CN204190607U (en) Circuit for suppressing power-on impact current of electrolytic capacitor
CN102882493B (en) A continuous high-frequency high voltage pulse source weight

Legal Events

Date Code Title Description
C10 Entry into substantive examination
COR Change of bibliographic data
C14 Grant of patent or utility model