CN108631575B - Soft start circuit applied to switching power supply - Google Patents
Soft start circuit applied to switching power supply Download PDFInfo
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- CN108631575B CN108631575B CN201810674805.2A CN201810674805A CN108631575B CN 108631575 B CN108631575 B CN 108631575B CN 201810674805 A CN201810674805 A CN 201810674805A CN 108631575 B CN108631575 B CN 108631575B
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- 238000000034 method Methods 0.000 description 4
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- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a soft start circuit applied to a switching power supply, which comprises a power supply output voltage Vout, wherein the soft start circuit comprises a latch control circuit (100), a charging delay circuit (200) and a logic control circuit (300) which are connected with each other, the logic control circuit (300) comprises a first comparator COMP1, a second comparator COMP2, a first NAND gate NAND1 and a second NAND gate NAND2, the output end of the first comparator COMP1 is connected with the input end of the first NAND gate NAND2, the output end of the second comparator COMP2 is connected with the input end of the first NAND gate NAND1, and the power supply output voltage Vout is used as the input voltage of the logic control circuit. The invention adopts a simple on-chip design mode to realize the soft start function by intermittently charging the output, and can completely put the soft start circuit into the chip to realize, thereby improving the integration level and reducing the design cost.
Description
Technical Field
The present invention relates to a soft start circuit, and more particularly to a soft start circuit for a switching power supply.
Background
In recent years, along with the increasing demand of electronic products, the application field of power management ICs is expanding, wherein the switching power supply is widely used in terms of its wide input/output voltage range and outstanding energy conversion efficiency. A typical switching power supply circuit is shown in fig. 1, which includes a drive transistor DP, a rectifier DN, an inductor L, a capacitor C, feedback control and drive circuitry, and a soft start circuit. In the start-up phase, a large surge current is generated, and a large overshoot is generated in the output voltage, so that circuit elements are damaged, and a soft start circuit is needed to avoid the occurrence of the phenomenon.
The prior art adopts different ways to realize the soft start function, for example, extra clock signals are generated inside the system to control the start speed, and the method increases the complexity of the circuit; for example, a complicated feedback circuit is used for realizing a soft start function, the complicated feedback circuit is very sensitive to parasitic parameters of a chip, so that the stability problem is brought, and the realization risk of the circuit is increased; for example, the soft start module is arranged outside the chip to be independently realized, but the method reduces the integration level of the system, increases the pin and material cost of the chip, and the like.
Disclosure of Invention
The invention aims at overcoming the defects in the prior art and provides a soft start circuit of a switching power supply, which has the characteristics of simple structure and reliable performance.
In order to achieve the aim of the invention, the invention adopts the following technical scheme: the soft start circuit comprises a power output voltage Vout, the soft start circuit comprises a latch control circuit, a charging delay circuit and a logic control circuit which are mutually connected, the input end of the latch control circuit is connected with the output end of the logic control circuit, the output end of the latch control circuit is connected with the input end of the logic control circuit, the output end of the charging delay circuit is connected with the input end of the logic control circuit, the logic control circuit comprises a first comparator COMP1, a second comparator COMP2, a first NAND gate NAND1 and a second NAND gate NAND2, the output end of the first comparator COMP1 is connected with the input end of the second NAND gate NAND2, the output end of the second comparator COMP2 is connected with the input end of the first NAND gate NAND1, and the power output voltage Vout is used as the input voltage of the logic control circuit.
In addition, the invention also provides the following auxiliary technical scheme: the positive end and the negative end of the input of the second comparator COMP2 are respectively connected with the output voltage Vout of the switching power supply and the output voltage Vcharge of the charging delay circuit, the positive end of the input of the first comparator COMP1 is connected with the reference voltage Vref, and the negative end of the input of the first comparator COMP1 is connected with the positive end of the input of the second comparator COMP 2.
The output terminal of the first comparator COMP1 is simultaneously used as the input terminal of the latch control circuit.
The latch control circuit comprises a first PMOS transistor PM1, a first NMOS transistor NM1 and a second NMOS transistor NM2, wherein the source electrode of the first PMOS transistor PM1 is connected with a power end VDD, the drain electrode of the first PMOS transistor PM1 is connected with the drain electrode of the NMOS transistor NM1, the source electrode of the first NMOS transistor NM1 is connected with the drain electrode of the second NMOS transistor NM2, and the source electrode of the second NMOS transistor NM2 is grounded.
The latch control circuit further comprises an inverter INV, a first capacitor C1 and a first current source I1, wherein the drain electrode of the first PMOS transistor PM1 is connected with the input end of the inverter INV, one end of the first capacitor C1 is connected with the drain electrode of the first PMOS transistor PM1, and the other end is connected with the source electrode of the second NMOS transistor NM 2.
The output end of the first comparator COMP1 is connected to the gates of the first PMOS transistor PM1 and the first NMOS transistor NM1, respectively.
The charging delay circuit comprises a second PMOS transistor PM2 and a third NMOS transistor NM3, wherein the source electrode of the second PMOS transistor PM2 is connected with a power supply voltage VDD, the drain electrode of the second PMOS transistor PM2 is connected with the input negative terminal of the second comparator COMP2, the drain electrode of the third NMOS transistor NM3 is connected with the drain electrode of the second PMOS transistor PM2, the source electrode of the third NMOS transistor NM3 is grounded, and the grid electrodes of the second PMOS transistor PM2 and the third NMOS transistor NM3 are respectively connected with the input end of the inverter INV.
It further includes a second capacitor C2 and a second current source 12, one end of the second capacitor C2 is connected to the drain of the second PMOS transistor PM2, and the other end is grounded, and the second capacitor C2 is charged by the second current source I2.
The switching power supply system further comprises a feedback control and driving circuit and a driving tube DP, and the soft start circuit opens and closes the driving tube DP through the feedback control and driving circuit.
Compared with the prior art, the invention has the advantages that: the soft start function is realized by adopting a simple on-chip design mode, and no control signal is required to be provided outside the system or an additional clock signal is required to be generated. Meanwhile, the soft start function is realized by intermittently charging the output, and a large soft start charging capacitor is not needed, so that the soft start circuit can be completely placed in a chip for realization, the complexity of circuit design is obviously reduced, the integration level is improved, and the design cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a switching power supply system of the present invention.
FIG. 2 is a schematic diagram of the connection of the various parts of the soft start circuit of the present invention.
FIG. 3 is a schematic diagram of a soft start circuit according to the present invention.
Fig. 4 is a table of the soft start circuit implementation functions of the present invention.
Detailed Description
The technical scheme of the present invention is further described in non-limiting detail below with reference to the preferred embodiments and the accompanying drawings.
The switching power supply circuit shown in fig. 1 comprises a driving tube DP, a rectifying tube DN, an inductor L, a capacitor C, a feedback and driving circuit and a soft start circuit. The input end of the driving tube DP is connected with the power supply VDD, the output end of the driving tube DP is connected with the input end of the rectifier DN, the output end of the rectifier DN is grounded, and the control end of the driving tube DP and the control end of the rectifying tube DN are respectively connected with the feedback control and the driving circuit. The inductor L is arranged between the driving tube DP and the output voltage Vout of the switching power supply, and one end of the capacitor C is connected with the inductor L. The other end is grounded. The output voltage Vout of the power supply slowly rises under the action of the soft start circuit, so that the generation of large surge current in the starting stage of the switching power supply system is avoided, and the overshoot of the output voltage is caused.
As shown in fig. 2 and 3, a soft start circuit includes a latch control circuit 100, a charge delay circuit 200, and a logic control circuit 300, where the latch control circuit 100 and the logic control circuit 300 are respectively connected to the charge delay circuit 200, and the latch control circuit 100 is connected to the logic control circuit 300. An input end of the latch control circuit 100 is connected with an output end of the logic control circuit 300, an output end of the latch control circuit 100 is connected with an input end of the logic control circuit 300, and an output end of the charge delay circuit 200 is connected with an input end of the logic control circuit 300. The latch control circuit 100 has its input as the output signal latch_set of the logic control circuit 300 and its output as the input signal soft_start_en of the logic control circuit 300. The inputs of the logic control circuit 300 are the output voltage Vcharge of the charge delay circuit 200, the output voltage Vout of the switching power supply, the reference level Vref, and the signal soft_start_en output from the latch control circuit 100.
The latch control circuit 100 is configured to latch a state of enabling or disabling the soft start circuit, where the latch control circuit 100 includes a first PMOS transistor PM1, a first NMOS transistor NM1, a second NMOS transistor NM2, an inverter INV, a first capacitor C1, and a first current source I1, a source of the first PMOS transistor PM1 is connected to the power supply terminal VDD, a drain of the first PMOS transistor PM1 is connected to a drain of the first NMOS transistor NM1, a source of the first NMOS transistor NM1 is connected to a drain of the second NMOS transistor NM2, a source of the second NMOS transistor NM2 is grounded, and a drain of the first PMOS transistor PM1 is connected to the inverter INV. One end of the first capacitor C1 is connected to the drain of the first PMOS transistor PM1, and the other end is connected to the source of the second NMOS collective transistor NM 2. One end of a first current source I1 is connected with the drain electrode of the first PMOS transistor PM1, the other end of the first current source I1 is connected with the source electrode of the second NMOS transistor NM2, the first current source I1 pulls the initial voltage of the node 1 to a low level, the initial working state of the latch control circuit is determined, and the normal working of the switch power supply system during starting is ensured.
The logic control circuit 300 includes a first comparator COMP1, a second comparator COMP2, a first NAND gate NAND1, and a second NAND gate NAND2, where an input positive terminal of the second comparator COMP2 is a switching power supply output voltage Vout, an input negative terminal voltage of the second comparator COMP2 is an output voltage Vcharge of the charging delay circuit 200, an output terminal of the second comparator COMP2 is connected to the first NAND gate NAND1, and another input terminal of the first NAND gate NAND1 is connected to a gate of the first NMOS transistor NM 1. The input positive terminal voltage of the first comparator COMP1 is the reference voltage Vref, the input negative terminal of the first comparator COMP1 is connected to the input positive terminal of the second comparator COMP2, the output terminal is connected to the input terminal of the second NAND gate NAND2, and the other input terminal of the second NAND gate NAND2 is connected to the gates of the first PMOS transistor PM1 and the second NMOS transistor NM2, respectively.
The charging delay circuit 200 includes a second PMOS transistor PM2, a third NMOS transistor NM3, a second capacitor C2, and a second current source I2, where a source of the second PMOS transistor PM2 is connected to the power supply voltage VDD, a drain of the second PMOS transistor PM2 is connected to an input negative terminal of the second comparator COMP2, a drain of the third NMOS transistor NM3 is connected to a drain of the second PMOS transistor PM2, a source of the third NMOS transistor NM3 is grounded, and gates of the second PMOS transistor PM2 and the third NMOS transistor NM3 are respectively connected to an input terminal of the inverter INV. One end of the second capacitor C2 is connected with the drain electrode of the second PMOS transistor PM2, the other end of the second capacitor C2 is grounded, one end of the second current source I2 is connected with the power supply end VDD, and the other end of the second current source I2 is connected with the source electrode of the second PMOS transistor PM 2.
As shown in fig. 4, when the system starts to power up, the source of the first PMOS transistor PM1 is at a high voltage end, the first PMOS transistor PM1 is turned on, the first current source I1 pulls the initial voltage of the node 1 to a low level, the low level voltage sets the voltage of the signal soft_start_en to be high through the inverter INV, the gate of the first NMOS transistor NM1 is at a high level, the first NMOS transistor NM1 is turned on, the switching power supply output voltage Vout is smaller than the reference voltage Vref, the first comparator COMP1 outputs a high level, the gate of the second NMOS transistor NM2 is at a high level, the second NMOS transistor NM2 is turned on, the gate of the first PMOS transistor PM1 is also at a high level, the first PMOS transistor PM1 is turned off, so that the signal soft_start_en is kept at a high level, and the soft start function is turned on.
The voltage of the node 1 is low, the gate of the third NMOS transistor NM3 and the gate of the second PMOS transistor PM2 are low, so that the third NMOS transistor NM3 is turned off, the second PMOS transistor PM2 is turned on, the second current source I2 charges the second capacitor C2, the second comparator COMP2 inputs the negative voltage Vcharge to slowly rise, when the input positive power output voltage Vout is smaller than the input negative voltage Vcharge, the voltage of the node 2 outputted by the second comparator COMP2 is low, the voltage of the node 3 is high after passing through the first NAND gate NAND1, the voltage of the other input terminal latch_set of the second NAND gate NAND2 is also high, the signal Vdrive voltage after passing through the second NAND gate NAND2 is low, the driving transistor DP of the switching power supply is turned on after passing through the feedback control and the driving circuit, the power output voltage Vout is gradually raised, when the output voltage Vout is larger than the input negative voltage Vcharge, the voltage Vout is high, the voltage of the other node 2 is high after passing through the first NAND gate NAND1, the voltage Vout is high, the voltage of the other node is high, and the voltage of the other node is high when the voltage Vout is high, the voltage is high, and the voltage is turned off again, and the voltage of the other node is high, and the voltage is stopped when the voltage is high, the voltage is turned off, the voltage is 2, and the voltage is high, and the voltage is turned off. In the soft start process, the voltage Vout rises slowly, and surge current and voltage overshoot caused by sharp charging are avoided.
When the power output voltage Vout is charged, if the power output voltage Vout is higher than the reference voltage Vref, the output voltage of the first comparator COMP1 is at a low level, at this time, the first PMOS transistor PM1 is turned on, the second MOS transistor NM2 is turned off, the voltage of the node 1 is pulled up, the gate of the third MOS transistor NM3 and the second PMOS transistor PM2 are at a high level, the third MOS transistor NM3 is turned on, the second PMOS transistor PM2 is turned off, the second capacitor C2 stops charging, the voltage Vcharge is pulled down, the voltage at the node 1 position is set to be low by the signal soft_start_en output after the inverter INV is inverted, the gate of the first MOS transistor NM1 is at a low level, and the first MOS transistor NM1 is turned off. At this time, the first PMOS transistor PM1, the first MOS transistor NM1, the second MOS transistor NM2, the inverter INV, the first current source I1, and the first capacitor C1 form a latch, and since the first current source I1 is small and the first capacitor C1 is used as a voltage stabilizing capacitor, it is ensured that the node 1 is kept at a high level under a normal operating state of the switching power supply, and therefore, the signal soft_start_en is kept at a low level, which does not affect the normal operation of the system, so that the soft start is finished, and the switching power supply stably operates.
The invention has the advantages that the soft start function is realized by adopting a simple on-chip design mode, the control signal is not required to be provided outside the system, and the additional clock signal is not required to be generated, meanwhile, the method for intermittently charging the output end is adopted, and a large soft start charging capacitor is not required, so that the soft start circuit can be completely put into the chip for realization, the complexity of circuit design is obviously reduced, the resource is saved, the cost is lower, the circuit portability is high, and the practicability is strong.
It should be noted that the foregoing description of the preferred embodiments is merely illustrative of the technical concept and features of the present invention, and is not intended to limit the scope of the invention, as long as the scope of the invention is defined by the claims and their equivalents. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (4)
1. A soft start circuit for a switching power supply, the switching power supply comprising a power supply output voltage Vout, the soft start circuit comprising a latch control circuit (100), a charge delay circuit (200) and a logic control circuit (300) connected to each other, characterized in that: the logic control circuit (300) comprises a first comparator (COMP 1), a second comparator (COMP 2), a first NAND gate NAND1 and a second NAND gate NAND2, wherein the input negative end of the first comparator (COMP 1) is connected with the input positive end of the second comparator (COMP 2), the input positive end of the first comparator (COMP 1) is connected with a reference voltage Vref, the output end of the second comparator (COMP 2) is connected with the first input end of the first NAND gate NAND1, the output end of the first NAND gate NAND1 is connected with the first input end of the second NAND gate NAND2, the output end of the first comparator (COMP 1) is connected with the second input end of the second NAND gate NAND2, the input end of the latch control circuit (100) is connected with the second input end of the first NAND gate NAND1, the output end of the charge delay circuit (200) is connected with the second input end of the second NAND gate NAND2, and the output end of the latch control circuit (100) is connected with the second input end of the second NAND gate NAND2 as the power supply voltage Vout;
the latch control circuit (100) comprises a first PMOS transistor PM1, a first NMOS transistor NM1 and a second NMOS transistor NM2, wherein the source electrode of the first PMOS transistor PM1 is connected with a power supply end VDD, the drain electrode of the first PMOS transistor PM1 is connected with the drain electrode of the NMOS transistor NM1, the source electrode of the first NMOS transistor NM1 is connected with the drain electrode of the second NMOS transistor NM2, the source electrode of the second NMOS transistor NM2 is grounded, the grid electrode of the NMOS transistor NM1 is connected with the second input end of the first NAND gate NAND1, and the grid electrodes of the first PMOS transistor PM1 and the second NMOS transistor NM2 are both connected with the output end of the first comparator COMP 1;
the latch control circuit (100) further comprises an inverter INV, a first capacitor C1 and a first current source I1, wherein the drain electrode of the first PMOS transistor PM1 is connected with the input end of the inverter INV, the output end of the inverter INV is connected with the gate electrode of the NMOS transistor NM1, one end of the first capacitor C1 is connected with the drain electrode of the first PMOS transistor PM1, the other end of the first capacitor C1 is connected with the source electrode of the second NMOS transistor NM2, the positive electrode of the first current source I1 is connected with the drain electrode of the first PMOS transistor PM1, the negative electrode of the first current source I1 is connected with the source electrode of the second NMOS transistor NM2, and the input end of the charge delay circuit (200) is connected with the input end of the inverter INV.
2. The soft start circuit for a switching power supply of claim 1, wherein: the charging delay circuit (200) comprises a second PMOS transistor PM2 and a third NMOS transistor NM3, wherein the source electrode of the second PMOS transistor PM2 is connected with a power supply voltage VDD, the drain electrode of the second PMOS transistor PM2 is connected with the input negative terminal of the second comparator COMP2, the drain electrode of the third NMOS transistor NM3 is connected with the drain electrode of the second PMOS transistor PM2, the source electrode of the third NMOS transistor NM3 is grounded, and the grid electrodes of the second PMOS transistor PM2 and the third NMOS transistor NM3 are respectively connected with the input end of the inverter INV.
3. The soft start circuit for a switching power supply of claim 2, wherein: the charging delay circuit (200) further comprises a second capacitor C2 and a second current source I2, one end of the second capacitor C2 is connected with the drain electrode of the second PMOS transistor PM2, the other end of the second capacitor C2 is grounded, the positive electrode of the second current source I2 is connected with the power supply voltage VDD, the negative electrode of the second current source I2 is connected with the source electrode of the second PMOS transistor PM2, and the second capacitor C2 is charged through the second current source I2.
4. The soft start circuit for a switching power supply of claim 1, wherein: the switching power supply further comprises a feedback control and driving circuit and a driving tube DP, and the soft start circuit opens and closes the driving tube DP through the feedback control and driving circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810674805.2A CN108631575B (en) | 2018-06-27 | 2018-06-27 | Soft start circuit applied to switching power supply |
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| CN201810674805.2A CN108631575B (en) | 2018-06-27 | 2018-06-27 | Soft start circuit applied to switching power supply |
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| CN108631575B true CN108631575B (en) | 2023-11-28 |
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| CN110752836B (en) * | 2019-09-11 | 2023-08-18 | 上海智浦欣微电子有限公司 | Signal control circuit and driving signal generation circuit |
| CN111600475B (en) * | 2020-05-24 | 2024-05-24 | 拓尔微电子股份有限公司 | Switching power supply soft start control circuit and control method |
| CN113922654B (en) * | 2021-09-13 | 2023-09-22 | 深圳市创芯微微电子股份有限公司 | Soft start circuit, switching power supply device, and electronic device |
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| CN101102076A (en) * | 2007-08-20 | 2008-01-09 | 威盛电子股份有限公司 | Soft startup circuit of switch power supply and its startup method |
| US7342328B1 (en) * | 2004-01-20 | 2008-03-11 | Linear Technology Corporation | Methods and circuits for tracking and sequencing multiple power supplies |
| CN101483386A (en) * | 2009-02-27 | 2009-07-15 | 华硕电脑股份有限公司 | DC to DC transformer and control method for reducing overshooting phenomenon |
| CN107276384A (en) * | 2017-06-15 | 2017-10-20 | 电子科技大学 | A kind of soft starting circuit based on pulse charge |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7800923B2 (en) * | 2008-02-29 | 2010-09-21 | System General Corp. | Offline synchronous switching regulator |
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| US7342328B1 (en) * | 2004-01-20 | 2008-03-11 | Linear Technology Corporation | Methods and circuits for tracking and sequencing multiple power supplies |
| CN101102076A (en) * | 2007-08-20 | 2008-01-09 | 威盛电子股份有限公司 | Soft startup circuit of switch power supply and its startup method |
| CN101483386A (en) * | 2009-02-27 | 2009-07-15 | 华硕电脑股份有限公司 | DC to DC transformer and control method for reducing overshooting phenomenon |
| CN107276384A (en) * | 2017-06-15 | 2017-10-20 | 电子科技大学 | A kind of soft starting circuit based on pulse charge |
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