CN204046448U - Output voltage dynamic sampling circuit in AC-DC converter - Google Patents
Output voltage dynamic sampling circuit in AC-DC converter Download PDFInfo
- Publication number
- CN204046448U CN204046448U CN201420422108.5U CN201420422108U CN204046448U CN 204046448 U CN204046448 U CN 204046448U CN 201420422108 U CN201420422108 U CN 201420422108U CN 204046448 U CN204046448 U CN 204046448U
- Authority
- CN
- China
- Prior art keywords
- voltage signal
- output
- sampled voltage
- nmos tube
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model relates to the output voltage dynamic sampling circuit in a kind of AC-DC converter.Described circuit comprises: oscillator, for generation of the first impulse oscillation signal and the second impulse oscillation signal; First sample holding unit, for receiving described first impulse oscillation signal, described output voltage signal of sampling when described first impulse oscillation signal is high level, obtains the first sampled voltage signal; Second sample holding unit, for receiving described second impulse oscillation signal, described output voltage signal of sampling when described second impulse oscillation signal is high level, obtains the second sampled voltage signal; Line or unit, for receiving described first sampled voltage signal and described second sampled voltage signal and exporting the 3rd sampled voltage signal; 3rd sample holding unit, obtains the 4th sampled voltage signal for receiving and carrying out sampling to described 3rd sampled voltage signal.The utility model achieves and can compare accurate detection to output voltage under any loading condition.
Description
Technical field
The utility model relates to integrated circuit (IC) design field, is specifically related to the output voltage dynamic sampling circuit in AC-DC converter.
Background technology
In AC-DC converter circuit, can be realized by the voltage of transformer inductance of sampling the detection of output voltage, and primary inductance voltage can assist winding to be transferred to control chip by transformer.Fig. 1 is the structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter of the prior art.As shown in Figure 1, resistance R1 represent the series parasitic resistance of secondary winding and the series parasitic resistance of output lead and.Under different output load currents, the voltage of secondary winding is distinguishing.Fig. 2 is the waveform comparison figure of the output voltage in prior art under different output load current in AC-DC converter.As can be seen from Figure 2, due to the difference of load, within the degaussing time (Tdmg), the output current of secondary winding is also different, causes the pressure drop on resistance R1 different, finally makes at the waveform of FB pin different.But at the end of the degaussing time, the electric current of secondary winding reduces to 0A, and the pressure drop on resistance R1 also reduces to 0V.Therefore, ideally, control chip should carry out the sampling of output voltage before the secondary winding degaussing time terminates.
Utility model content
The purpose of this utility model is for the deficiencies in the prior art, in AC-DC converter circuit, propose a kind of circuit of before the degaussing time terminates, output voltage being sampled, thus make control chip can compare accurate detection to output voltage under any loading condition.
For achieving the above object, the utility model provides the output voltage dynamic sampling circuit in a kind of AC-DC converter, and described circuit comprises:
Oscillator, for generation of the first impulse oscillation signal and the second impulse oscillation signal;
First sample holding unit, is connected with described oscillator, and for receiving described first impulse oscillation signal, described output voltage signal of sampling when described first impulse oscillation signal is high level, obtains the first sampled voltage signal;
Second sample holding unit, is connected with described oscillator, and for receiving described second impulse oscillation signal, described output voltage signal of sampling when described second impulse oscillation signal is high level, obtains the second sampled voltage signal;
Line or unit, be connected with the second sample holding unit with described first sample holding unit respectively, for receiving described first sampled voltage signal and described second sampled voltage signal and exporting the 3rd sampled voltage signal;
3rd sample holding unit, is connected with described line or unit, obtains the 4th sampled voltage signal for receiving and carrying out sampling to described 3rd sampled voltage signal.
Preferably, described oscillator comprises the first current source, the second current source, the first switch, second switch, electric capacity, the first comparator, the second comparator, the 3rd comparator, rest-set flip-flop, inverter, the first d type flip flop, the second d type flip flop, the first three value and gate and the second three value and gate;
Described second switch is connected with described second current source and ground connection, described first current source is connected with described first switch and accesses the positive input of described first comparator and the positive input of described second comparator respectively, described electric capacity is connected between the positive input of described first switch and described first comparator, the negative input of described first comparator accesses the first compare threshold, the output of described first comparator is held with the R of described rest-set flip-flop and is connected, the negative input of described second comparator accesses the second compare threshold, the output of described second comparator is held with the S of described rest-set flip-flop and is connected, the output of described rest-set flip-flop is connected with described first d type flip flop, the output of described rest-set flip-flop is connected with described second d type flip flop via after described inverter, the output of described first d type flip flop, the output of described rest-set flip-flop is connected with described first three value and gate respectively with the output of described 3rd comparator, the output of described second d type flip flop, the output of described rest-set flip-flop is connected with described second three value and gate respectively with the output of described 3rd comparator,
When described first switch closes, described second switch disconnects, described first current source charges to described electric capacity, when the voltage rise at described electric capacity two ends is to described first compare threshold, described first comparator exports high level and makes the output of described rest-set flip-flop be set to low level, thus control described first switch disconnection, described second switch closes, described second current source is described capacitor discharge, the voltage drop at described electric capacity two ends exports high level to the second comparator described in during described second compare threshold and makes the output of described rest-set flip-flop be reset as high level, thus it is closed to control described first switch, described second switch disconnects.
Preferably, described line or unit comprise the first operational amplifier, the second operational amplifier, the first NMOS tube, the second NMOS tube, the 3rd current source, the 4th current source and power supply;
The described first sampled voltage signal of positive input access of described first operational amplifier, the negative input of described first operational amplifier connects with the source electrode of described first NMOS tube via described 3rd current source ground connection, the described second sampled voltage signal of positive input access of described second operational amplifier, the negative input of described second operational amplifier connects with the source electrode of described second NMOS tube via described 4th current source ground connection, the drain electrode of described first NMOS tube and the drain electrode of described second NMOS tube connect power supply respectively, the source electrode of described first NMOS tube and the source electrode of described second NMOS tube connect and as the output of described line or unit, thus export described 3rd sampled voltage signal,
When described first sampled voltage signal is greater than described second sampled voltage signal, the grid voltage of described first NMOS tube is greater than the grid voltage of described second metal-oxide-semiconductor, the source electrode of described first NMOS tube drives described 3rd current source and described 4th current source to make described first NMOS tube conducting second NMOS tube cut-off simultaneously, makes described 3rd sampled voltage signal equal described first sampled voltage signal;
When described first sampled voltage signal is less than described second sampled voltage signal, the grid voltage of described first NMOS tube is less than the grid voltage of described second metal-oxide-semiconductor, the source electrode of described first NMOS tube drives described 3rd current source and described 4th current source to make described first NMOS tube end the second NMOS tube conducting simultaneously, makes described 3rd sampled voltage signal equal described second sampled voltage signal.
Preferably, the phase place of described first impulse oscillation signal and the phase half period of described second impulse oscillation signal.
Preferably, described first compare threshold is greater than described second compare threshold.
Output voltage dynamic sampling circuit in a kind of AC-DC converter provided by the utility model embodiment, the oscillator of this circuit produces two impulse oscillation signals, control the first sample holding unit and the second sample holding unit respectively, output voltage in AC-DC converter obtains the first sampled voltage signal and the second sampled voltage signal by the first sample holding unit and the second sample holding unit, first sampled voltage signal and the second sampled voltage signal obtain the 3rd sampled voltage signal by line or unit, 3rd sampled voltage signal carries out sampling by the 3rd sample holding unit and obtains the 4th sampled voltage signal under control signal, thus the sampling achieved to output voltage before the degaussing time terminates, make control chip can compare accurate detection to output voltage under any loading condition.
Accompanying drawing explanation
Fig. 1 is the structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter of the prior art;
Fig. 2 is the waveform comparison figure of the output voltage in prior art under different output load current in AC-DC converter;
The structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 3 provides for the utility model embodiment;
The sequential chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 4 provides for the utility model embodiment;
The structural representation of the pierce circuit that Fig. 5 provides for the utility model embodiment;
The sequential chart of the pierce circuit that Fig. 6 provides for the utility model embodiment;
The structural representation of the line that Fig. 7 provides for the utility model embodiment or unit.
Embodiment
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
The utility model proposes a kind of circuit of before the degaussing time terminates, output voltage being sampled, thus make control chip can compare accurate detection to output voltage under any loading condition.
The structure chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 3 provides for the utility model embodiment, as shown in Figure 3, this output voltage dynamic sampling circuit comprises: oscillator U1, the first sample holding unit U21, the second sample holding unit U22, line or unit U3 and the 3rd sample holding unit U23.
The voltage signal that the input of oscillator U1 is the FB node shown in Fig. 1, oscillator U1 is for generation of the first impulse oscillation signal CLK1 and the second impulse oscillation signal CLK2.Due to the negative feedback of whole Switching Power Supply, the high level of FB voltage waveform finally can approximate another input of Fig. 1 medial error amplifier, i.e. reference voltage Vref.Therefore oscillator U1 inside can by FB voltage waveform compared with a reference voltage (Vref-Voff) being less than Vref voltage, the scope that wherein Voff can select is 0.01V-Vref: when FB voltage waveform ratio (Vref-Voff) is high, and the output first impulse oscillation signal CLK1 of oscillator U1 and the second impulse oscillation signal CLK2 is the impulse oscillation signal of two phase half period; When FB voltage waveform ratio (Vref-Voff) is low, output first impulse oscillation signal CLK1 and the second impulse oscillation signal CLK2 of oscillator U1 are logic low.
The sequential chart of the output voltage dynamic sampling circuit in a kind of AC-DC converter that Fig. 4 provides for the utility model embodiment, as shown in Figure 4.When FB voltage is higher than (Vref-Voff), the first impulse oscillation signal CLK1 is high level at once, and the time of high level is t1, and the low level time is (t1+2*t2), and therefore the pulse period is (2*t1+2*t2); Second impulse oscillation signal CLK2 is high level in time delay (t1+t2) afterwards, and the time of high level is t1, and the low level time is (t1+2*t2), and therefore the pulse period is (2*t1+2*t2).The delay of the rising edge of CLK2 and the rising edge of CLK1 is (t1+t2), therefore phase half period.
First sample holding unit U21 is connected with oscillator U1, the input of the first sample holding unit U21 is respectively FB and the first impulse oscillation signal CLK1, output is the first sampled voltage signal VFBA, when the first impulse oscillation signal CLK1 is logic height, the magnitude of voltage of VFBA sampling FB, when the first pulse signal CLK1 is logic low, VFBA keeps last sampled value;
Second sample holding unit U22 is connected with oscillator U1, the input of the second sample holding unit U22 is respectively FB and the second impulse oscillation signal CLK2, output is the second sampled voltage signal VFBB, when impulse oscillation signal CLK2 is logic height, the magnitude of voltage of VFBB sampling FB, when pulse signal CLK2 is logic low, VFBB keeps last sampled value.
Line or unit U3 are connected with the second sample holding unit U22 with described first sample holding unit U21 respectively, the input of line or unit U3 is the first sampled voltage signal VFBA and the second sampled voltage signal VFBB, VFBA and VFBB is carried out line or process and exports the 3rd sampled voltage signal VFBC.Particularly, the 3rd sampled voltage signal VFBC is magnitude of voltage maximum in output VFBA and VFBB two voltages of line or unit.
3rd sample holding unit U23 is connected with line or unit U3, carries out sampling obtain the 4th sampled voltage signal VFB to the 3rd sampled voltage signal VFBC.Concrete, the input of the 3rd sample holding unit U23 is the Gate signal in the 3rd sampled voltage signal VFBC and Fig. 1, exports the voltage signal for the VFB node in shown in Fig. 1, namely with an input of error amplifier.When Gate signal is logic height, the magnitude of voltage of VFB sampling VFBC, when Gate signal is logic low, VFB keeps last sampled value.
Further, the specific implementation of oscillator U1 as shown in Figure 5.Oscillator U1 comprises: the first current source I1, the second current source I2, the first interrupteur SW 1, second switch SW2, electric capacity C1, the first comparator, the second comparator, the 3rd comparator, rest-set flip-flop, inverter, the first d type flip flop, the second d type flip flop, the first three value and gate AND1 and the second three value and gate AND2.
Second switch SW2 is connected with the second current source I2 and ground connection, first current source I1 is connected with the first interrupteur SW 1 and accesses the positive input of the first comparator and the positive input of the second comparator respectively, electric capacity C1 is connected between the first interrupteur SW 1 and the positive input of the first comparator, the negative input of the first comparator accesses the first compare threshold VthH, the output of the first comparator is held with the R of rest-set flip-flop and is connected, the negative input of the second comparator accesses the second compare threshold VthL, the output of the second comparator is held with the S of rest-set flip-flop and is connected, the output of rest-set flip-flop is connected with the first d type flip flop, the output of rest-set flip-flop is connected with the second d type flip flop via after inverter, the output of the first d type flip flop, the output of described rest-set flip-flop is connected with the first three value and gate AND1 respectively with the output of the 3rd comparator, the output of the second d type flip flop, the output of rest-set flip-flop is connected with the second three value and gate AND2 respectively with the output of the 3rd comparator.
Wherein, the first current source I1, the second current source I2, the first interrupteur SW 1, second switch SW2, electric capacity C1, the first comparator, the second comparator, and rest-set flip-flop constitutes traditional oscillator.
The sequential chart of the pierce circuit that Fig. 6 provides for the utility model embodiment.As shown in Figure 6, when the first interrupteur SW 1 closes, when 2nd SW2 disconnects, first current source I1 charges to electric capacity C1, the voltage rise at electric capacity C1 two ends, namely sawtooth waveforms Saw rises, when rising to the first compare threshold VthH of the first comparator, first comparator exports high level, the output Q1 of rest-set flip-flop is reset as low level, thus control the first interrupteur SW 1 disconnect second switch SW2 close, second current source I2 is that electric capacity C1 discharges, when the voltage sawtooth waveforms Saw at electric capacity C1 two ends drops to the second compare threshold VthL of the second comparator, second comparator exports high level, the output Q1 of rest-set flip-flop is set to high level, thus control the first interrupteur SW 1 closed second switch SW2 disconnects.The output Q1 of rest-set flip-flop is made to be oscillating pulse wave and so forth.Q1 is that the time t1 of high level and low level time t2 are respectively:
Oscillating pulse wave Q1 and the reverse signal of Q1 that produces via inverter, respectively by the first d type flip flop and the second d type flip flop frequency division, produce two fractional frequency signal Q2 and Q3.
The voltage waveform of FB compared with threshold value (Vref-Voff), is produced logic control signal VFBHigh by the 3rd comparator.When FB is lower than threshold value (Vref-Voff), VFBHigh is low, and output first impulse oscillation signal CLK1 and the second impulse oscillation signal CLK2 of the first three value and gate AND1 and the second three value and gate AND2 are low; When FB is higher than threshold value (Vref-Voff), VFBHigh is low, the output first impulse oscillation signal CLK1 of the first three value and gate AND1 be Q1 and Q2 with the output second impulse oscillation signal CLK2 of, the second three value and gate AND2 be Q1 and Q3 with.
Further, as shown in Figure 7, line or unit U3 comprise the specific implementation of line or unit U3: line or unit comprise the first operational amplifier, the second operational amplifier, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd current source I3 and the 4th current source I4.
The positive input of the first operational amplifier accesses the first sampled voltage signal VFBA, the negative input of the first operational amplifier connects via the 3rd current source I3 ground connection with the source electrode of the first NMOS tube NM1, the positive input of the second operational amplifier accesses the second sampled voltage signal VFBB, the negative input of the second operational amplifier connects via the 4th current source I4 ground connection with the source electrode of the second NMOS tube NM2, the drain electrode of the first NMOS tube NM1 and the drain electrode of the second NMOS tube NM2 connect power supply respectively, the source electrode of the first NMOS tube NM1 and the source electrode of the second NMOS tube NM2 connect and as output the 3rd sampled voltage signal VFBC of line or unit U3.
The negative input of the first operational amplifier and the source shorted of the first NMOS tube NM1 form the amplifier that gain is 1, and positive input is connected with the first sampled voltage signal VFBA in Fig. 3.Operational amplifier drives the class A amplifier be made up of the first NMOS tube NM1 and the 3rd current source I3.
Equally, the negative input of the second operational amplifier and the source shorted of the second NMOS tube NM2 form the amplifier that gain is 1, and positive input is connected with the second sampled voltage signal VFBB in Fig. 3.Operational amplifier drives the class A amplifier be made up of the second NMOS tube NMOS tube NM2 and the 4th current source I4.
The class A amplifier that first NMOS tube NM1 and the 3rd current source I3 is formed has larger high level driving force, with the low level driving force limited by the 3rd current source I3, the class A amplifier that second NMOS tube NM2 and the 4th current source I4 is formed has larger high level driving force equally, and by the low level driving force that the 4th current source I4 limits.As shown in Figure 7, when NM1 with NM2 source shorted to together with and when being connected to VFBC, the voltage of VFBC is determined by the ceiling voltage of VFBA and VFBB, " line or " function of Here it is line or unit.Such as, as VFBA>VFBB, the grid voltage of NM1 is greater than the grid voltage of NM2, so the source electrode of NM1 will simultaneously drive current source I3 and I4, NM1 conducting, makes VFBC=VFBA, and the negative input voltage of the second operational amplifier equals VFBA is greater than VFBB, therefore the output of the second operational amplifier is lower, and NM2 is ended.Otherwise as VFBB>VFBA, the grid voltage of NM2 is greater than the grid voltage of NM1, so the source electrode of NM2 will simultaneously drive current source I3 and I4, NM2 conducting, make VFBC=VFBB, and the negative input voltage of the first operational amplifier equals VFBB and is greater than VFBA, and therefore the output of the first operational amplifier is lower, makes NM1 end.
The utility model embodiment proposes a kind of circuit of sampling to output voltage before the degaussing time terminates, comprising: oscillator produces two impulse oscillation signals and controls two sample holding units respectively, these two sample holding units carry out sampling to output voltage respectively and obtain two sampled signals, these two sampled signals obtain the 3rd sampled voltage signal by line or unit again, 3rd sampled voltage signal obtains the final sampled voltage of sampling to output voltage again by a sample holding unit, thus make control chip can compare accurate detection to output voltage under any loading condition.
Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; be understood that; the foregoing is only embodiment of the present utility model; and be not used in restriction protection range of the present utility model; all within spirit of the present utility model and principle, any amendment made, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.
Claims (5)
1. the output voltage dynamic sampling circuit in AC-DC converter, is characterized in that, described circuit comprises:
Oscillator, for generation of the first impulse oscillation signal and the second impulse oscillation signal;
First sample holding unit, is connected with described oscillator, and for receiving described first impulse oscillation signal, described output voltage signal of sampling when described first impulse oscillation signal is high level, obtains the first sampled voltage signal;
Second sample holding unit, is connected with described oscillator, and for receiving described second impulse oscillation signal, described output voltage signal of sampling when described second impulse oscillation signal is high level, obtains the second sampled voltage signal;
Line or unit, be connected with the second sample holding unit with described first sample holding unit respectively, for receiving described first sampled voltage signal and described second sampled voltage signal and exporting the 3rd sampled voltage signal;
3rd sample holding unit, is connected with described line or unit, obtains the 4th sampled voltage signal for receiving and carrying out sampling to described 3rd sampled voltage signal.
2. the output voltage dynamic sampling circuit in AC-DC converter according to claim 1, it is characterized in that, described oscillator comprises the first current source, the second current source, the first switch, second switch, electric capacity, the first comparator, the second comparator, the 3rd comparator, rest-set flip-flop, inverter, the first d type flip flop, the second d type flip flop, the first three value and gate and the second three value and gate;
Described first current source is connected with described first switch and accesses the positive input of described first comparator and the positive input of described second comparator respectively, described electric capacity is connected between the positive input of described first switch and described first comparator, the negative input of described first comparator accesses the first compare threshold, the output of described first comparator is held with the R of described rest-set flip-flop and is connected, the negative input of described second comparator accesses the second compare threshold, the output of described second comparator is held with the S of described rest-set flip-flop and is connected, the output of described rest-set flip-flop is connected with described first d type flip flop, the output of described rest-set flip-flop is connected with described second d type flip flop via after described inverter, the output of described first d type flip flop, the output of described rest-set flip-flop is connected with described first three value and gate respectively with the output of described 3rd comparator, the output of described second d type flip flop, the output of described rest-set flip-flop is connected with described second three value and gate respectively with the output of described 3rd comparator,
When described first switch closes, described second switch disconnects, described first current source charges to described electric capacity, when the voltage rise at described electric capacity two ends is to described first compare threshold, described first comparator exports high level and makes the output of described rest-set flip-flop be set to low level, thus control described first switch disconnection, described second switch closes, described second current source is described capacitor discharge, the voltage drop at described electric capacity two ends exports high level to the second comparator described in during described second compare threshold and makes the output of described rest-set flip-flop be reset as high level, thus it is closed to control described first switch, described second switch disconnects.
3. the output voltage dynamic sampling circuit in AC-DC converter according to claim 1, it is characterized in that, described line or unit comprise the first operational amplifier, the second operational amplifier, the first NMOS tube, the second NMOS tube, the 3rd current source, the 4th current source and power supply;
The described first sampled voltage signal of positive input access of described first operational amplifier, the negative input of described first operational amplifier connects with the source electrode of described first NMOS tube via described 3rd current source ground connection, the described second sampled voltage signal of positive input access of described second operational amplifier, the negative input of described second operational amplifier connects with the source electrode of described second NMOS tube via described 4th current source ground connection, the drain electrode of described first NMOS tube and the drain electrode of described second NMOS tube connect power supply respectively, the source electrode of described first NMOS tube and the source electrode of described second NMOS tube connect and as the output of described line or unit, thus export described 3rd sampled voltage signal,
When described first sampled voltage signal is greater than described second sampled voltage signal, the grid voltage of described first NMOS tube is greater than the grid voltage of described second metal-oxide-semiconductor, the source electrode of described first NMOS tube drives described 3rd current source and described 4th current source to make described first NMOS tube conducting second NMOS tube cut-off simultaneously, makes described 3rd sampled voltage signal equal described first sampled voltage signal;
When described first sampled voltage signal is less than described second sampled voltage signal, the grid voltage of described first NMOS tube is less than the grid voltage of described second metal-oxide-semiconductor, the source electrode of described first NMOS tube drives described 3rd current source and described 4th current source to make described first NMOS tube end the second NMOS tube conducting simultaneously, makes described 3rd sampled voltage signal equal described second sampled voltage signal.
4. the output voltage dynamic sampling circuit in AC-DC converter according to claim 1, is characterized in that, the phase place of described first impulse oscillation signal and the phase half period of described second impulse oscillation signal.
5. the output voltage dynamic sampling circuit in AC-DC converter according to claim 2, is characterized in that, described first compare threshold is greater than described second compare threshold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420422108.5U CN204046448U (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410160556.7 | 2014-04-21 | ||
| CN201410160556.7A CN103887952A (en) | 2014-04-21 | 2014-04-21 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
| CN201420422108.5U CN204046448U (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204046448U true CN204046448U (en) | 2014-12-24 |
Family
ID=50956706
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410160556.7A Pending CN103887952A (en) | 2014-04-21 | 2014-04-21 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
| CN201410364898.0A Active CN104143928B (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
| CN201420422108.5U Active CN204046448U (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410160556.7A Pending CN103887952A (en) | 2014-04-21 | 2014-04-21 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
| CN201410364898.0A Active CN104143928B (en) | 2014-04-21 | 2014-07-29 | Output voltage dynamic sampling circuit in AC-DC converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (3) | CN103887952A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104143928A (en) * | 2014-04-21 | 2014-11-12 | 美芯晟科技（北京）有限公司 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105425008B (en) * | 2015-10-30 | 2018-06-12 | 张良 | Internet of Things high sensitivity magnetic senser sampling circuit |
| CN105915045B (en) * | 2016-03-16 | 2018-10-19 | 四川长虹电器股份有限公司 | Convertible frequency air-conditioner PFC control methods based on IGBT ring times |
| CN106645879B (en) * | 2017-01-18 | 2019-04-05 | 深圳市思远半导体有限公司 | A kind of the inductive current sampling holding meanss and method of switching power circuit |
| DE102018201925A1 (en) * | 2018-02-07 | 2019-08-08 | Würth Elektronik eiSos Gmbh & Co. KG | Apparatus for obtaining electrical energy and energy producers with such a device |
| CN112379153B (en) * | 2020-10-30 | 2023-05-26 | 阳光电源股份有限公司 | Direct current oscillation detection circuit, direct current arc detection circuit and inverter |
| CN112491281B (en) * | 2020-11-30 | 2022-08-09 | 杭州士兰微电子股份有限公司 | Switching power supply and control circuit and control method thereof |
| CN113391113B (en) * | 2021-06-18 | 2022-11-18 | 矽力杰半导体技术(杭州)有限公司 | Voltage detection circuit, switch converter and integrated circuit |
| CN113791348B (en) * | 2021-09-28 | 2023-02-24 | 中国科学院半导体研究所 | Phase signal detection device of alternating current generator |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6853563B1 (en) * | 2003-07-28 | 2005-02-08 | System General Corp. | Primary-side controlled flyback power converter |
| CN100433520C (en) * | 2005-03-04 | 2008-11-12 | 崇贸科技股份有限公司 | Switching control device for primary side control output current of power supply |
| US7400127B2 (en) * | 2005-05-23 | 2008-07-15 | Semiconductor Components Industries, L.L.C. | Method for regulating an output signal and circuit therefor |
| CN101867299B (en) * | 2010-07-20 | 2012-03-21 | 周光友 | Circuit and method for switch power supply feedback voltage detection and sampling and holding |
| US8482268B2 (en) * | 2010-09-16 | 2013-07-09 | System General Corporation | Correction circuit of a switching-current sample for power converters in both CCM and DCM operation |
| CN103107688B (en) * | 2013-02-25 | 2016-12-28 | 昂宝电子（上海）有限公司 | The system and method for the live signal sampling in power converting system |
| CN103887952A (en) * | 2014-04-21 | 2014-06-25 | 美芯晟科技（北京）有限公司 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
-
2014
- 2014-04-21 CN CN201410160556.7A patent/CN103887952A/en active Pending
- 2014-07-29 CN CN201410364898.0A patent/CN104143928B/en active Active
- 2014-07-29 CN CN201420422108.5U patent/CN204046448U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104143928A (en) * | 2014-04-21 | 2014-11-12 | 美芯晟科技（北京）有限公司 | Output voltage dynamic sampling circuit in alternating current-direct current converter |
| CN104143928B (en) * | 2014-04-21 | 2017-09-12 | 美芯晟科技（北京）有限公司 | Output voltage dynamic sampling circuit in AC-DC converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104143928A (en) | 2014-11-12 |
| CN104143928B (en) | 2017-09-12 |
| CN103887952A (en) | 2014-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204046448U (en) | Output voltage dynamic sampling circuit in AC-DC converter | |
| CN102882377B (en) | Synchronous rectifying control method and circuit | |
| CN103248207B (en) | Constant-current and constant-voltage fly-back converter based on primary side feedback | |
| CN101677240B (en) | Isolated gate bipolar transistor driving circuit | |
| CN102055344B (en) | Switch power supply | |
| CN103580000A (en) | Overvoltage protection method and circuit for switching power supply output and switching power supply provided with the circuit | |
| CN105375798A (en) | Self-adaptive sampling circuit, primary side feedback constant voltage system and switching power supply system | |
| CN103856043A (en) | Control circuit and four-switch buck-boost converter | |
| CN103825469B (en) | For control circuit and the isolated converter of isolated converter | |
| CN207021912U (en) | Multiple-channel output random waveform voltage source system | |
| CN103280995A (en) | Quasi-resonance converter synchronous rectification circuit | |
| CN104320001A (en) | Magnetic isolation feedback circuit | |
| CN103280963A (en) | Power factor correction (PFC) control circuit for reducing conducting power consumption of power tube | |
| CN104009633A (en) | Current continuous type high-gain DC-DC converter circuit | |
| CN103825457A (en) | Quasi-Z-source DC-DC boost converter circuit | |
| CN205070828U (en) | AC -DC single -stage control chip and control system thereof | |
| CN203883673U (en) | Improved Z-source boost DC-DC converter | |
| CN102437740A (en) | Primary-side feedback flyback constant-current power supply with input voltage compensation function | |
| CN205160398U (en) | Self -adaptation sampling circuit , printed circuit board , former limit feedback constant voltage system and switching power supply system | |
| CN104539177A (en) | Synchronous rectification drive circuit and synchronous rectification method of switching power supply | |
| CN205017636U (en) | A peak current detection circuitry for LED constant -current drive circuit | |
| CN103326585B (en) | Measure the sample circuit of the reflected voltage of the transformer of power converter | |
| CN202997953U (en) | Capacitor energy-storage type silicon-controlled switch power source | |
| CN102368667A (en) | Offline type AC-DC (Alternating Current-Direct Current) control circuit and converting circuit comprising same | |
| CN105515413B (en) | A kind of output voltage sampling circuit and method based on AC-DC converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 01, 10 / F, block a, Tiangong building, Keda, 30 Xueyuan Road, Haidian District, Beijing 100089 Patentee after: Meixinsheng Technology (Beijing) Co.,Ltd. Address before: 1006, office building, Crowne Plaza, No. 106, Zhichun Road, Haidian District, Beijing 100086 Patentee before: MAXIC TECHNOLOGY (BEIJING) Co.,Ltd. |