CN106685391A

CN106685391A - Level converting circuit

Info

Publication number: CN106685391A
Application number: CN201611265829.XA
Authority: CN
Inventors: 唐立伟; 任军
Original assignee: Hefei Hengshuo Semiconductor Co Ltd
Current assignee: Hefei Hengshuo Semiconductor Co Ltd
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2017-05-17

Abstract

The invention discloses level converting circuit. The level converting circuit includes NMOS transistors, wherein a grid electrode of a low voltage NMOS transistor is connected with low supply voltage; a grid electrode of a first high voltage NMOS transistor is connected with a source electrode of the low voltage NMOS transistor; a drain electrode of the first high voltage NMOS transistor and a grid electrode of a second high voltage NMOS transistor are connected with a drain electrode of the low voltage NMOS transistor; and a source electrode of the first high voltage NMOS transistor and a source electrode of the second high voltage NMOS transistor are grounded. The level converting circuit is simple and needs less quantity of transistors, thus reducing the cost.

Description

Level shifting circuit

Technical field

The present invention relates to a kind of change-over circuit, the level shifting circuit of more particularly to a kind of low pressure to high pressure.

Background technology

The level shifting circuit that prior art is realized has various, but the following defect of different degrees of presence：

One, circuit is complicated, required transistor size is more, mostly divides three big levels to realize.

Two, signal transmission delay is big, and signal is too big from the transmission delay for being input to output, for frequency is high, can give Level shifting circuit postpones that where the used time is little very big bottleneck can be run into.

Three, required circuit cost is high, because the transistor size that available circuit is used is more, causes the silicon chip shared by it Area is larger.

The content of the invention

The technical problem to be solved is to provide a kind of level shifting circuit, and its circuit is simple, required transistor Number is less, reduces cost.

The present invention is to solve above-mentioned technical problem by following technical proposals：A kind of level shifting circuit, its feature It is that it includes low voltage nmos transistor, the first high voltage PMOS transistor, the second high voltage PMOS transistor, the 3rd high voltage PMOS Transistor, the first high pressure NMOS pipe, the second high pressure NMOS pipe, the grid of low voltage nmos transistor connects low supply voltage, and first The source electrode connection of the grid of High voltage NMOS transistor and low voltage nmos transistor, the drain electrode of the first high voltage PMOS transistor, second The grid of high voltage PMOS transistor is all connected with the drain electrode of low voltage nmos transistor, the source electrode of the first high pressure NMOS pipe, second high The source electrode of pressure NMOS tube is all grounded, the grid of the first high voltage PMOS transistor, the drain electrode of the second high voltage PMOS transistor, three-hypers The grid of pressure PMOS transistor, the grid of the second high pressure NMOS pipe are all connected with the drain electrode of the first high pressure NMOS pipe, the first high pressure The source electrode of PMOS transistor, the source electrode of the second high voltage PMOS transistor are all connected and connect with the 3rd high voltage PMOS transistor source electrode To higher power supply.

Preferably, used as transmission gate, low voltage nmos transistor is conducting to the low voltage nmos transistor all the time.

Preferably, first high voltage PMOS transistor is used as pulling up transistor.

The present invention positive effect be：

One, this Power Generation Road is simple, and required transistor size is less, is realized by cutting down transistor size, this circuit letter Number path has only used six transistors, reduces cost.

Two, signal transmission delay is little, is realized by logic series before and after reduction circuit, this circuit two grades of phase inverters altogether With Primary Transmit door.

Three, reduction number of transistors purpose purpose has been reached, finally realize the silicon area shared by level shifting circuit Reduction.

Description of the drawings

Fig. 1 is the circuit diagram of level shifting circuit of the present invention.

Specific embodiment

Present pre-ferred embodiments are given below in conjunction with the accompanying drawings, to describe technical scheme in detail.

As shown in figure 1, level shifting circuit of the present invention includes low voltage nmos transistor M0, the first high voltage PMOS transistor MP0, the second high voltage PMOS transistor MP1, the 3rd high voltage PMOS transistor MP2, the first high pressure NMOS pipe MN1, the second high pressure NMOS tube MN2, the grid of low voltage nmos transistor connects low supply voltage VDD_L, the grid of the first High voltage NMOS transistor MN1 Connect with the source electrode of low voltage nmos transistor, the drain electrode of the first high voltage PMOS transistor MP0, the second high voltage PMOS transistor MP1 Grid be all connected with the drain electrode of low voltage nmos transistor, the source electrode of the first high pressure NMOS pipe MN1, the second high pressure NMOS pipe MN2 Source electrode be all grounded, the grid of the first high voltage PMOS transistor MP0, the drain electrode of the second high voltage PMOS transistor MP1, the 3rd high pressure The grid of PMOS transistor MP2, the grid of the second high pressure NMOS pipe MN2 are all connected with the drain electrode of the first high pressure NMOS pipe MN1, the The source electrode of one high voltage PMOS transistor MP0, the second high voltage PMOS transistor MP1 source electrode all with the 3rd high voltage PMOS transistor MP2 connects.

Low voltage nmos transistor M0 is used as transmission gate, and the grid of low voltage nmos transistor meets low supply voltage VDD_L, low Pressure nmos pass transistor is conducting all the time.First high voltage PMOS transistor MP0 is used as pulling up transistor.

As shown in figure 1, wherein, VDD_L is low supply voltage；VDD_H is high supply voltage；VSS is shared ground (Ground or gnd).

Input signal IN is the logical signal of low-voltage, is arrived Jing after the low voltage nmos transistor M0 for being constantly in open mode Node IN1, this node is connected by the first high voltage PMOS transistor MP0 with VDD_H, the first high voltage PMOS transistor MP0's Grid is connected with node OUT_b, and node IN1 directly drives the grid of the second high voltage PMOS transistor MP1 simultaneously.Input signal IN directly drives the grid of the first High voltage NMOS transistor MN1 simultaneously.By the second high voltage PMOS transistor MP1 and the first high pressure The output of NMOS tube MN1 obtains node OUT_b, the high voltage PMOS transistor MP2 of OUT_b Jing the 3rd and the second high pressure NMOS pipe MN2 The phase inverter of composition obtains output node OUT.OUT is the signal of the high level amplitude of oscillation, corresponding with the IN of the low level amplitude of oscillation of input, OUT slightly postpones than IN.

The circuit course of work of the present invention is as follows：

Focus on node IN from " 0 " to " 1 " and from " 1 " to the transition process of " 0 " two states：

One, IN from " 0 " to " 1 "：

Because IN is direct drive MN1, it is not necessary to through M0, which reduce the transmission delay of signal；

Because the ceiling voltage of IN is VDD_L, high voltage transistor MN1 will be in weak conducting state；

When due to IN being " 0 ", IN1 be " 0 " (0V), MP1 is conducting, OUT_b be logic high " 1 " (VDD_H), this When MP0 be off；When this process IN from " 0 " to " 1 ", through M0, thus the node voltage of IN1 also can progressively be lifted, This can cause MP1 progressively to close, and the electric current for flowing to OUT_b from VDD_H Jing MP1 is progressively reducing, simultaneously because MN1 is in weak Conducting, has the electric current that Jing MN1 flow to VSS, and this electric current can be drop-down to VSS directions OUT_b, and the voltage of OUT_b can be by Step declines；The OUT_b of decline can progressively open MP0, and this has an electric current for progressively increasing and flows to from VDD_H Jing MP0 The voltage of IN1, node IN1 can progressively be lifted in the presence of this electric current；The IN1 that this voltage is lifted is accelerated again The process stated；

Finally, node IN1 pulls to VDD_H by MP0, and OUT_b pulls to VSS by MN1, through the phase inverter that MP2 and MN2 is constituted Afterwards OUT points pull to VDD_H by MP2, which achieves IN from " 0 " to " 1 " (VDD_L), OUT from " 0 " to " 1 " turning (VDD_H) Become.

This process can smoothly be realized that MP0 grids are connected to the feedback of OUT_b points composition and have played effect.

Two, IN from " 1 " to " 0 "：

MN1 will end quickly (because IN is direct drive MN1, it is not necessary to which, through M0, the transmission for which reducing signal is prolonged Late)；

When due to IN being " 1 ", IN1 is " 1 ", when this process IN from " 1 " to " 0 ", through M0, the voltage of node IN1 Can be thus progressively drop-down, MP1 is gradually opened, and electric current flows to OUT_b from VDD_H Jing MP1, and thus the current potential of OUT_b is progressively drawn It is high；The OUT_b that this is progressively drawn high progressively closes MP0, and the electric current for flowing to point IN1 from VDD_H Jing MP0 is progressively reducing；

With the carrying out of transition processes of the IN from " 1 " to " 0 ", IN is further drop-down to VSS directions IN1 through M0, this Said process acceleration can be promoted.

Final IN1 becomes " 0 ", and OUT_b becomes VDD_H；

During processes of the OUT_b from " 0 " to " 1 ", through the phase inverter that MP2 and MN2 is constituted, the state of node OUT can be from " 1 " To " 0 " conversion.

1. as shown in figure 1,2 mistakes of (the low-voltage amplitude of oscillation) IN from " 0 " to " 1 " that said of back and from " 1 " to " 0 " Journey completes the mutual conversion of digital circuit logic " 0 " and " 1 ", and the OUT points of corresponding high-voltage region also can be completed accordingly The digital circuit logic " 0 " of the high voltage amplitude of oscillation and the mutual conversion of " 1 ".

This finally realizes the OUT of the IN of the low power work area low-voltage amplitude of oscillation to the high voltage amplitude of oscillation in high power work area Level conversion.

Particular embodiments described above, the technical problem, technical scheme and beneficial effect to the solution of the present invention is carried out Further describe, should be understood that the specific embodiment that the foregoing is only of the invention, be not limited to The present invention, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc., should be included in this Within the protection domain of invention.

Claims

1. a kind of level shifting circuit, it is characterised in that it include low voltage nmos transistor, the first high voltage PMOS transistor, Two high voltage PMOS transistors, the 3rd high voltage PMOS transistor, the first high pressure NMOS pipe, the second high pressure NMOS pipe, low pressure NMOS is brilliant The grid of body pipe connects low supply voltage, the grid of the first High voltage NMOS transistor and the source electrode connection of low voltage nmos transistor, The drain electrode of the first high voltage PMOS transistor, the grid of the second high voltage PMOS transistor all connect with the drain electrode of low voltage nmos transistor Connect, the source electrode of the first high pressure NMOS pipe, the source electrode of the second high pressure NMOS pipe are all grounded, the grid of the first high voltage PMOS transistor, The drain electrode of the second high voltage PMOS transistor, the grid of the 3rd high voltage PMOS transistor, the grid of the second high pressure NMOS pipe are all with One high pressure NMOS pipe drain electrode connection, the source electrode of the first high voltage PMOS transistor, the second high voltage PMOS transistor source electrode all with 3rd high voltage PMOS transistor source electrode connects and is connected to higher power supply.

2. level shifting circuit as claimed in claim 1, it is characterised in that the low voltage nmos transistor as transmission gate, Low voltage nmos transistor is conducting all the time.

3. level shifting circuit as claimed in claim 1, it is characterised in that first high voltage PMOS transistor is used as pull-up Transistor.