CN106330172B - The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure - Google Patents
The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure Download PDFInfo
- Publication number
- CN106330172B CN106330172B CN201510341803.8A CN201510341803A CN106330172B CN 106330172 B CN106330172 B CN 106330172B CN 201510341803 A CN201510341803 A CN 201510341803A CN 106330172 B CN106330172 B CN 106330172B
- Authority
- CN
- China
- Prior art keywords
- nmos transistor
- transistor
- signal
- transmission gate
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention provides a kind of transmission gate and its pull-down circuit structure, including the first NMOS transistor being connected in parallel between signal input part and signal output end and PMOS transistor, wherein the substrate of the PMOS transistor is connected to supply voltage and the substrate of first NMOS transistor is connected to ground, first NMOS transistor is connected to the first signal pin, the grid of PMOS transistor is connected to second signal needle, it is characterized by: the first NMOS transistor is intrinsic NMOS transistor, and the second NMOS transistor and third NMOS transistor that the grid including being connected between signal output end and ground is direct-connected with drain electrode, the grid of the third NMOS transistor is connected to second signal needle.The present invention is directed to high voltage threshold device circuitry, even if enabling to the transmission gate circuit with intrinsic NMOS transistor at lower supply voltages and input signal being to be maintained at rising edge in the case where discontented width and failing edge is smoothly connected, logic function is effectively played.Also, the pull-down circuit for adding the direct-connected NMOS transistor of grid leak can efficiently reduce leakage current within the scope of biggish supply voltage.
Description
Technical field
The present invention relates to technical field of semiconductors, transmission gate in particular to a kind of high voltage threshold device and thereafter
Continuous pull-down circuit structure.
Background technique
In the electronic device of high voltage threshold, it usually needs be followed by pull-down circuit to transmission gate.The common knot of transmission gate
Structure is made of a pair of grid-controlled NMOS transistor and PMOS transistor, their grid is connected to different signal pins.
And the pull-down circuit being followed by is usually grid-controlled NMOS transistor.In general, PMOS transistor and drop-down electricity in transmission gate
The grid of NMOS transistor in road is connected to identical signal pin, and the signal pin and the NMOS crystal that is connected in transmission gate
The high low logic of the level of the signal pin of pipe is opposite.When the grid signal needle of NMOS transistor is logic low and PMOS transistor
Grid signal needle be logic high, then transmission gate end, pull-down circuit conducting.When the grid signal needle of NMOS transistor is
The grid signal needle of logic high and PMOS transistor is logic low, then transmission gate conducting, pull-down circuit cut-off.
Effective application in field to high voltage threshold device in a wide range of supply voltage has urgent demand.And
In the prior art, in the case where low voltage power supply (usual supply voltage is one between double voltage threshold value), when input electricity
When pressure is not the full amplitude of oscillation, the gate source voltage V of the NMOS transistor in transmission gate circuitgsOr the gate source voltage V of PMOS transistorgs
Lower, close to voltage threshold, therefore, because threshold value is higher, NMOS transistor and PMOS transistor are difficult in rising edge or decline
Along opening rapidly, the exchange performance of transmission gate will be weakened significantly.The problem has become the transmission gate of high voltage threshold device
The bottleneck of circuit and its subsequent pull-down circuit.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of transmission gate and its pull-down circuit structure, including is connected in parallel on letter
Number the first NMOS transistor between input terminal and signal output end and between PMOS transistor and signal output end and ground
Second NMOS transistor, wherein the substrate of the PMOS transistor is connected to the lining of supply voltage and first NMOS transistor
Bottom is connected to ground, and the grid of first NMOS transistor is connected to the first signal pin, the PMOS transistor and the 2nd NMOS
The grid of transistor is connected to second signal needle, it is characterised in that: first NMOS transistor is intrinsic NMOS transistor.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that: described first
The drain electrode of NMOS transistor and the drain electrode of PMOS transistor are connected with signal input part, the source electrode of first NMOS transistor,
The drain electrode of the source electrode of PMOS transistor and the second NMOS transistor is connected with signal output end, the source of second NMOS transistor
Pole is connected to ground.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that the PMOS crystal
Pipe is standard PMOS transistor, and second NMOS transistor is standard NMOS transistor.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that the first NMOS
Transistor is controlled by the first signal pin for being connected to its grid, and the standard PMOS transistor is with the second NMOS transistor by common
It is connected to the second signal needle control of its grid.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that when the transmission gate
When circuit is respectively on and off state, the first signal pin of control first NMOS transistor is respectively provided with logically high
Level and logic low, and the second signal needle for controlling the PMOS transistor and the second NMOS transistor is respectively provided with logic
Low level and logic high.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that the second signal
Needle is opposite with the logic level of the first signal pin height.
In view of the deficiencies of the prior art, the present invention also provides a kind of transmission gate and its pull-down circuit structures, including parallel connection
The first NMOS transistor and PMOS transistor between signal input part and signal output end, wherein the PMOS transistor
Substrate is connected to supply voltage and the substrate of first NMOS transistor is connected to ground, and first NMOS transistor is connected to
First signal pin, the grid of PMOS transistor are connected to second signal needle, it is characterised in that: the first NMOS transistor is intrinsic
NMOS transistor, and the grid including being connected between signal output end and ground and drain direct-connected the second NMOS transistor and
The grid of third NMOS transistor, the third NMOS transistor is connected to second signal needle.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that the first NMOS
The drain electrode of transistor and the drain electrode of PMOS transistor are connected with signal input part, source electrode, the PMOS of first NMOS transistor
The source electrode of transistor, second NMOS transistor grid be connected with drain electrode with signal output end, the 3rd NMOS crystal
The drain electrode of pipe is connected with the source electrode of the second NMOS transistor, substrate and the third NMOS transistor of second NMOS transistor
Source electrode is connected to ground.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that the PMOS crystal
Pipe is standard PMOS transistor, and second NMOS transistor and third NMOS transistor are standard NMOS transistor.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that intrinsic NMOS crystal
Pipe is controlled by the first signal pin for being connected to its grid, and the standard PMOS transistor is with third NMOS transistor by connecting jointly
Second signal needle to its grid controls.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that when the transmission gate
When circuit is respectively on and off state, control the intrinsic NMOS transistor the first signal pin be respectively provided with it is logically high
Level and logic low, and the second signal needle for controlling the standard PMOS transistor and third NMOS transistor is respectively provided with
Logic low and logic high.
In one embodiment of the invention, transmission gate and its pull-down circuit structure are further characterized in that: second letter
Number needle is opposite with the logic level for the first signal pin for being connected to intrinsic NMOS transistor gate height.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the schematic diagram of existing transmission gate and its pull-down circuit structure；
Fig. 2 shows a standard NMOS transistors in transmission gate according to one of embodiment, by the prior art to replace
It is changed to the transmission gate of intrinsic NMOS transistor and its schematic diagram of pull-down circuit structure；
Fig. 3 show it is according to one of embodiment, a standard NMOS transistor in the transmission gate of the prior art is replaced
It is changed to intrinsic NMOS transistor and series gate and the direct-connected NMOS transistor of draining shows in the pull-down circuit of the prior art
It is intended to；
Fig. 4 shows according to one of embodiment, the transistor containing intrinsic NMOS transmission gate and contains standard NMOS transistor
Transmission gate AC response simulation waveform.
Fig. 5 shows according to one of embodiment, direct-connected containing intrinsic NMOS transistor and grid leak NMOS transistor
Transmission gate and its pull-down circuit structure and the transmission containing intrinsic NMOS transistor but without the direct-connected NMOS transistor of grid leak
The simulation waveform of the pull-down circuit structure electric leakage of door.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiments.
In general, high voltage threshold (V in the prior artth) device contain transmission gate circuit and subsequent pull-down circuit.It passes
Defeated door is a kind of analog switch of transmission of analogue signal, and cmos transmission gate is usually by a PMOS transistor and a NMOS crystal
Pipe is formed in parallel.Such as Fig. 1, the transmission gate of the prior art and its schematic diagram of pull-down circuit structure are shown.
Transmission gate circuit shown in FIG. 1 is made of a pair pmos transistor M1 and NMOS transistor M2, also, PMOS crystal
Pipe M1 is controlled by the signal pin IE_N that its grid connects, and NMOS transistor M2 is controlled by the signal pin IE_P that its grid connects, IE_
The logic level height of N and IE_P is opposite.The working principle of transmission gate in logic circuits are as follows:
(1) when IE_P is low level, and IE_N is high level, due to the gate source voltage V of NMOS transistor M2gs≤ 0, PMOS
The gate source voltage V of transistor M1gs>=0, therefore NMOS transistor M2 and PMOS transistor M1 are off state, transmission gate is suitable
It is disconnected in switch.
(2) when IE_P is high level, and IE_N is low level, due to the gate source voltage V of NMOS transistor M2gs>=0, PMOS
The gate source voltage V of transistor M1gs≤ 0, therefore at least a transistor is to lead in NMOS transistor M2 and PMOS transistor M1
Logical state, so that IN=OUT.This is equivalent to switch connection, and transmission gate starts to transmit information.
(3) further, work as IE_P=VDDIO, when IE_N=0V, IN is by 0- (VDDIO-Vth) range when,
The gate source voltage V of NMOS transistor M2gs≥Vth, NMOS transistor M2 conducting；When IN is by VthWhen the range of-VDDIO,
The gate source voltage V of PMOS transistor M1gs≤Vth, PMOS transistor M1 conducting；That is, when IN changes in the range of 0-VDDIO
When, an at least transistor turns in NMOS transistor M2 and PMOS transistor M1, so that IN=OUT, this is equivalent to switch
It connects, transmission gate transmits information.
The subsequent pull-down circuit of above-mentioned transmission gate is then usually by being connected between the output end of transmission gate circuit and ground
NMOS transistor M3 is made, wherein NMOS transistor M3 is also controlled by the signal pin IE_N of grid connection, signal pin IE_N
It is identical as the signal pin IE_N of PMOS transistor M1.
Further, when IE_P is logic low and IE_N is logic high, the grid source electricity of NMOS transistor M2
Press VgsThe gate source voltage V of≤0, PMOS transistor M1gs>=0, therefore NMOS transistor M2 and PMOS transistor M1 are cut-off shape
State, transmission gate circuit cut-off.And the gate source voltage V of the NMOS transistor M3 in pull-down circuitgs>Vth, transistor M3 conducting, because
And pull-down circuit is connected；
When IE_P is logic high and IE_N is logic low, the gate source voltage V of NMOS transistor M2gs>=0,
The gate source voltage V of PMOS transistor M1gs≤ 0, therefore an at least transistor in NMOS transistor M2 and PMOS transistor M1
For on state, so that IN=OUT, this is equivalent to switch connection, transmission gate circuit conducting.And the NMOS crystal in pull-down circuit
The gate source voltage V of pipe M3gs=0 < Vth, transistor M3 cut-off, i.e. pull-down circuit end.
In the prior art, supply voltage (VDDIO) it is lower (usually between one to twice threshold value, i.e. Vth<VDDIO<
2Vth) in the case where, when the input voltage of transmission gate is between the maximum value of logic low and the minimum value of logic high
(VIL-VIH) discontented width in the case of, the gate source voltage V of NMOS transistor M1gs(VIH) or PMOS transistor M2 gate source voltage
Vgs(VDDIO-VIL) lower, and close to its voltage threshold Vth, and voltage threshold VthIt is higher, therefore PMOS transistor M1 and NMOS
Transistor M2 is difficult to the communication opened rapidly in the rising edge and failing edge of input, thus will influence significantly transmission gate
Energy.
In order to solve the problems, such as the exchange performance decline of the transmission gate when input is the non-full amplitude of oscillation and lower supply voltage, this
Invention proposes a kind of new transmission gate circuit.Fig. 2 shows in transmission gate according to one of embodiment, by the prior art
One standard NMOS transistor replaces with the schematic diagram of the logic circuit of intrinsic NMOS transistor.M2 in figure is that intrinsic NMOS is brilliant
Body pipe, the M1 for forming transmission gate together is then standard PMOS transistor.Due to the threshold value V of intrinsic NMOS transistor M2thCompared with
It is low, therefore the gate source voltage V of M2gs(VDDIO-VIL) it is much higher than threshold value Vth, therefore be easy to be connected in failing edge.In addition, compared to
With high voltage threshold VthM1 for, be in rising edge when, the gate source voltage V of M2gs(VDDIO-VIH) also sufficiently high, M2
It can promptly be connected, thus also to M1 due to lower gate source voltage VgsCaused slow response forms compensation.
In the subsequent pull-down circuit of the transmission gate of the prior art, when IE_P be logic low, and IE_N be logic
When high level, the gate source voltage V of NMOS transistor M3gs>Vth, NMOS transistor M3 conducting, pull-down circuit conducting.But existing
Will appear leaky in the pull-down circuit structure of technology: i.e. no matter the threshold value V of intrinsic NMOS transistorthFor positive voltage or negative electricity
Pressure has from the leaky that ground flows to transmission gate input terminal and occurs when input is logic low and is negative voltage.It needs
It is noted that input is not lower than -0.3V, i.e., according to the V of JEDEC standardILMinimum value.
Further, if the threshold value V of intrinsic NMOS transistorthFor negative voltage, when input is logic low and is positive
When voltage, also has from the leaky on transmission gate input terminal flow direction ground and occur.It should be noted that input also should not be greater than
The absolute value of the voltage threshold of NMOS transistor | Vth|。
It should be noted that when M2 is intrinsic NMOS, it is understood that there may be from input terminal to ground or from ground to input terminal
Electrical leakage problems.This also will affect the performance of pull-down circuit.
The present invention provides a kind of methods, for solving asking there are leaky in the prior art and above-described embodiment
Topic.Fig. 3 shows a kind of schematic diagram of new logic circuit structure, and the logic circuit structure is according to one of embodiment by existing skill
Standard NMOS transistor in the transmission gate of art replaces with intrinsic NMOS transistor and connects in the pull-down circuit of the prior art
The direct-connected NMOS transistor of grid leak.In the transmission gate circuit of the logic circuit structure, it is substituted with intrinsic NMOS transistor M2
Standard NMOS transistor in the prior art, and the direct-connected NMOS transistor of grid leak of having connected in the pull-down circuit of the prior art
M4.The grid of NMOS transistor M4 and drain electrode are connected directly to the output end of transmission gate circuit, and the source electrode of NMOS transistor M4 with
The drain electrode of NMOS transistor M3 is connected.It should be noted that in PMOS transistor M1 and pull-down circuit in transmission gate circuit
The grid of NMOS transistor M3 is controlled by identical signal pin IE_N, the logic level and control intrinsic NMOS of signal pin IE_N
The logic level height of the signal pin IE_P of the grid of transistor M2 is opposite.
Further, when IE_P is logic high, and IE_N is logic low, transmission gate circuit conducting, drop-down
Circuit cut-off.Since M2 is intrinsic NMOS transistor, due to the threshold value V of intrinsic NMOS transistor M2thIt is lower, therefore the grid source of M2
Voltage Vgs(VDDIO-VIL) it is much higher than threshold value Vth, therefore be easy to be connected in failing edge.In addition, compared to high voltage threshold
VthM1 for, be in rising edge when, the gate source voltage V of M2gs(VDDIO-VIH) also sufficiently high, M2 can promptly be connected,
Thus also to M1 due to lower gate source voltage VgsCaused slow response forms compensation.Therefore, intrinsic NMOS transistor exists
Application in circuit efficiently solves the problems, such as the AC response when low voltage power supply is powered.
And when IE_P is logic low and IE_N is logic high, the gate source voltage V of PMOS transistor M1gs>=0,
Therefore PMOS transistor M1 is off state.And the gate source voltage V of the NMOS transistor M3 in pull-down circuitgs>=0, transistor M3
Conducting, thus pull-down circuit is connected.The state of intrinsic NMOS transistor is discussed below:
According to one embodiment of present invention, if the input of transmission gate circuit is the negative voltage not less than -0.3V, due to
The voltage threshold V of intrinsic NMOS transistorthIt is lower, therefore intrinsic NMOS transistor M2 can be connected.However, due to transistor M4
Grid and source electrode between voltage Vgs=0, M4 cut-off, therefore, intrinsic NMOS transistor M2 and pull-down circuit NMOS transistor
M3 works in deep triode region, and the leaky of transmission gate input terminal, the output and input one of transmission gate are not flowed to from ground
Cause is logic low.
According to another embodiment of the present invention, if the voltage threshold V of intrinsic NMOS transistorthFor negative voltage, and pass
The input of defeated door is the absolute value of the voltage threshold not higher than NMOS transistor | Vth| positive voltage, although M2 be connected, due to
The voltage threshold V of standard NMOS transistor M4thThe absolute value of voltage threshold much higher than intrinsic NMOS transistor M2 | Vth|, because
The gate source voltage V of this M4gsLower than its threshold value Vth, NMOS transistor M4 cut-off.Not from the electric leakage on transmission gate input terminal flow direction ground
Phenomenon, the output and input of transmission gate are unanimously logic low.
According to still another embodiment of the invention, when the input of transmission gate is to float, due to other no electric leakages, M3 is in
Deep triode region is simultaneously pulled down to ground, and M4 is because of its Vds=Vgs<VthAnd end, it exports as logic low.
According to an embodiment of the invention, Fig. 4 shows the transmission gate and the crystal of NMOS containing standard of the transistor containing intrinsic NMOS
The simulation waveform of the AC response of the transmission gate of pipe.Wherein, 1. supply voltage VDDIO=1.62V, curve are the defeated of transmission gate
Enter signal, frequency 5MHz, voltage amplitude is between 0.324-1.134V.2. curve is the biography with standard NMOS transistor
The response simulation figure of defeated gate circuit, the amplitude of the response is between 0.324-0.386V, due in rising edge, transmission gate circuit
PMOS gate source voltage Vgs(i.e. VIH) lower, close to its threshold voltage Vth, therefore it can not smoothly be connected, logic function
Failure.3. curve is the response simulation figure of the transmission gate circuit with intrinsic NMOS transistor, the amplitude of the response is in 0.324-
Between 1.134V, due to the gate source voltage V of the intrinsic NMOS transistor in transmission gate circuitgs(i.e. VDDIO-VIH) still enough
Height, can be in the gate source voltage V of rising edge compensation PMOS transistorgs(i.e. VIH), therefore it can smoothly be connected, logic function
Normally.
According to an embodiment of the invention, Fig. 5 shows the NMOS crystal direct-connected containing intrinsic NMOS transistor and grid leak
The transmission gate and its pull-down circuit structure of pipe and the biography containing intrinsic NMOS transistor but without the direct-connected NMOS transistor of grid leak
The simulation waveform of the pull-down circuit structure electric leakage of defeated door.Wherein, the threshold voltage V of intrinsic NMOS transistorthFor positive voltage.?
When supply voltage is 5.5V, 1. curve is the input signal of transmission gate, in the range of -0.3-5.5V.2. curve is under subsequent
Electric leakage curve when in puller circuit without the direct-connected NMOS transistor of grid leak, when input voltage is -0.3V, leakage current 42.9
μA.3. curve is electric leakage curve when in subsequent pull-down circuit containing grid leak direct-connected NMOS transistor, when input voltage be-
When 0.3V, leakage current is less than 10nA.
Further, when supply voltage is 1.62V, 4. curve is the input signal of transmission gate, in the range of -0.3V-
1.62V.5. curve is electric leakage curve when in subsequent pull-down circuit without grid leak direct-connected NMOS transistor, work as input voltage
When for -0.3V, leakage current is 40.5 μ A.6. curve is when in subsequent pull-down circuit containing grid leak direct-connected NMOS transistor
Leak electricity curve, and when input voltage is -0.3V, leakage current is less than 10nA.
By the curve in Fig. 4 and Fig. 5 as it can be seen that the transmission gate circuit with intrinsic NMOS transistor can be in rising edge under
Drop effectively plays logic function along smooth conducting.Also, the pull-down circuit for adding the direct-connected NMOS transistor of grid leak can have
Effect ground reduces leakage current, effectively overcomes the defect and deficiency of the prior art.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of transmission gate and its pull-down circuit structure, including be connected in parallel between signal input part and signal output end first
The second NMOS transistor between NMOS transistor and PMOS transistor and signal output end and ground, wherein the PMOS is brilliant
The substrate of body pipe is connected to supply voltage and the substrate of first NMOS transistor is connected to ground, first NMOS transistor
Drain electrode and the drain electrode of PMOS transistor be connected with signal input part, the source electrode of first NMOS transistor, PMOS transistor
The drain electrode of source electrode and the second NMOS transistor be connected with signal output end, the source electrode of second NMOS transistor is connected to
Ground, the grid of first NMOS transistor are connected to the first signal pin, the PMOS transistor and the second NMOS transistor
Grid is connected to second signal needle, and the second signal needle is opposite with the logic level of the first signal pin height, it is characterised in that:
First NMOS transistor is intrinsic NMOS transistor.
2. transmission gate as described in claim 1 and its pull-down circuit structure, it is characterised in that: the PMOS transistor is standard
PMOS transistor, second NMOS transistor are standard NMOS transistor.
3. transmission gate as claimed in claim 2 and its pull-down circuit structure, it is characterised in that: first NMOS transistor by
It is connected to the first signal pin control of its grid, the standard PMOS transistor and the second NMOS transistor are by being commonly connected to it
The second signal needle of grid controls.
4. transmission gate as claimed in claim 3 and its pull-down circuit structure, it is characterised in that: when the transmission gate circuit is distinguished
When being on off state, the first signal pin for controlling first NMOS transistor is respectively provided with logic high and patrols
Volume low level, and the second signal needle for controlling the PMOS transistor and the second NMOS transistor be respectively provided with logic low and
Logic high.
5. a kind of transmission gate and its pull-down circuit structure, including be connected in parallel between signal input part and signal output end first
NMOS transistor and PMOS transistor, wherein the substrate of the PMOS transistor is connected to supply voltage and the first NMOS is brilliant
The substrate of body pipe is connected to ground, and first NMOS transistor is connected to the first signal pin, and the grid of PMOS transistor is connected to
Second signal needle, it is characterised in that: the first NMOS transistor be intrinsic NMOS transistor, and including be connected on signal output end with
Grid between ground and drain direct-connected the second NMOS transistor and third NMOS transistor, the third NMOS transistor
Grid is connected to second signal needle, the drain electrode of first NMOS transistor and the drain electrode of PMOS transistor and signal input part phase
Even, the source electrode of first NMOS transistor, the source electrode of PMOS transistor, second NMOS transistor grid and drain electrode with
Signal output end is connected, and the drain electrode of the third NMOS transistor is connected with the source electrode of the second NMOS transistor, and described second
The substrate of NMOS transistor and the source electrode of third NMOS transistor are connected to ground, the second signal needle and are connected to intrinsic NMOS
The logic level height of first signal pin of transistor gate is opposite.
6. transmission gate as claimed in claim 5 and its pull-down circuit structure, it is characterised in that: the PMOS transistor is standard
PMOS transistor, second NMOS transistor and third NMOS transistor are standard NMOS transistor.
7. transmission gate as claimed in claim 6 and its pull-down circuit structure, it is characterised in that: intrinsic NMOS transistor is by connecting
The first signal pin to its grid controls, and the standard PMOS transistor and third NMOS transistor are by being commonly connected to its grid
Second signal needle control.
8. transmission gate as claimed in claim 7 and its pull-down circuit structure, it is characterised in that: when the transmission gate circuit is distinguished
When being on off state, the first signal pin for controlling the intrinsic NMOS transistor is respectively provided with logic high and patrols
Low level is collected, and the second signal needle for controlling the standard PMOS transistor and third NMOS transistor is respectively provided with logic low electricity
Gentle logic high.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510341803.8A CN106330172B (en) | 2015-06-18 | 2015-06-18 | The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510341803.8A CN106330172B (en) | 2015-06-18 | 2015-06-18 | The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106330172A CN106330172A (en) | 2017-01-11 |
| CN106330172B true CN106330172B (en) | 2019-04-09 |
Family
ID=57733047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510341803.8A Active CN106330172B (en) | 2015-06-18 | 2015-06-18 | The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106330172B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107306128B (en) * | 2016-04-18 | 2020-10-02 | 中芯国际集成电路制造(上海)有限公司 | Transmission gate circuit |
| CN108540116A (en) * | 2018-05-24 | 2018-09-14 | 上海芯圣电子股份有限公司 | A kind of transmission gate circuit of isolation high input voltage |
| WO2020056685A1 (en) * | 2018-09-20 | 2020-03-26 | 华为技术有限公司 | Transmission gate circuit, matrix switch and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1734942A (en) * | 2004-08-09 | 2006-02-15 | 三星电子株式会社 | Level shifter with low-leakage current |
| CN102945682A (en) * | 2012-11-05 | 2013-02-27 | 上海集成电路研发中心有限公司 | Static random access memory unit capable of resisting single-event upset |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3676018B2 (en) * | 1997-02-25 | 2005-07-27 | シャープ株式会社 | Voltage level shifter circuit |
-
2015
- 2015-06-18 CN CN201510341803.8A patent/CN106330172B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1734942A (en) * | 2004-08-09 | 2006-02-15 | 三星电子株式会社 | Level shifter with low-leakage current |
| CN102945682A (en) * | 2012-11-05 | 2013-02-27 | 上海集成电路研发中心有限公司 | Static random access memory unit capable of resisting single-event upset |
Non-Patent Citations (2)
| Title |
|---|
| 一种中心频率可调的VCO 电路设计;邢立冬，蒋林;《微电子学与计算机》;20110430;第28卷(第4期);第22页 |
| 电磁干扰对CMOS传输门的影响;陈杰，杜正伟;《清华大学学报(自然科学版)》;20121231;第52卷(第12期);第1710页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106330172A (en) | 2017-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101686048B (en) | Low leakage voltage level shifting circuit | |
| CN103929172B (en) | Level shift circuit | |
| CN103856205B (en) | Level shifting circuit, for driving the drive circuit of high tension apparatus and corresponding method | |
| CN101888178B (en) | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop | |
| CN101471654A (en) | Leakage output buffer for univoltage supply cmos | |
| CN104505050A (en) | Scanning driving circuit for oxide semiconductor thin film transistor | |
| CN106330172B (en) | The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure | |
| CN106921284A (en) | A kind of MOSFET floating driving circuits | |
| CN110289848A (en) | Voltage level converting | |
| CN104137418B (en) | On-off circuit | |
| CN209072341U (en) | The level shifter and chip across voltage domain based on DMOS pipe | |
| CN102064818A (en) | Complementary metal oxide semiconductor (CMOS) input/output interface circuit | |
| CN111427820B (en) | IO circuit and access control signal generation circuit for IO circuit | |
| CN111106822A (en) | Power supply power-on module | |
| CN104270138B (en) | Input/output buffer of multiple voltage domains | |
| CN108123708A (en) | A kind of pull-up circuit for I/O circuit | |
| CN104270142B (en) | Input/output buffer for multiple voltage domains | |
| CN102624370A (en) | Device and method for realizing voltage detection | |
| CN107908220A (en) | A kind of generating circuit from reference voltage suitable for wide power voltage scope | |
| CN202652065U (en) | Delayed supply circuit of high voltage and low voltage power supplies | |
| CN115037292B (en) | High-dropout level transfer circuit with enabling detection and power-down protection | |
| CN108933592A (en) | high-speed level conversion circuit, level conversion method and data transmission device | |
| US20150207508A1 (en) | Level conversion circuit | |
| CN109818492A (en) | A kind of secondary power supply generation circuit reducing interference | |
| CN206341200U (en) | Grid driving circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |