CN104638887A - Output driving circuit capable of realizing output high level conversion - Google Patents
Output driving circuit capable of realizing output high level conversion Download PDFInfo
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- CN104638887A CN104638887A CN201510050634.2A CN201510050634A CN104638887A CN 104638887 A CN104638887 A CN 104638887A CN 201510050634 A CN201510050634 A CN 201510050634A CN 104638887 A CN104638887 A CN 104638887A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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Abstract
The invention provides an output driving circuit capable of realizing output high level conversion. The output driving circuit is characterized by comprising a first power supply VDD1, a second power supply VDD2, an output control circuit T, an upwards pulling P tube pre-driving circuit, an upwards pulling output driving PMOS (P-channel metal oxide semiconductor) tube MP2, a downwards pulling output driving tube MN5, an output isolation circuit, a downwards pulling N tube pre-driving circuit, a variable driving signal MID and a downwards pulling pre-driving circuit. The upwards pulling pre-driving circuit provides the variable driving signal MID for the driving tube MP2 through the pulling of a level displacement buffer circuit SHIFT by using the feedback circuit for acceleration, so that the whole circuit realizes the output high level voltage conversion under the high-voltage-device-free condition. Compared with other circuits, the technology has the characteristics that an additional high-voltage device output tube is not needed, different selections of low level input and high level output can be realized, the load is fast driven, the power supply noise can be isolated, the area is smaller, and the power consumption is lower.
Description
Technical field
The present invention relates to one and do not utilize high tension apparatus, also can realize the output driving circuit that low level voltage turns high level voltage, more specifically, relate to level translator and integrated circuit I/O design field.
Background technology
Along with the variation of integrated circuit development, derive the integrated circuit worked under various level voltage.Correct signal level can ensure that system works reliably, prevents sensitive circuit undermined because of too high or too low voltage conditions.The input not reaching required level can reduce the surplus of signal noise, and excessive input, the loss of excessive power can be caused.For transmission of signal effectively, integrated circuit utilizes I/O (I/O) interface as the bridge changed between low pressure and high pressure usually, while making the complete transmission of low-voltage signal, from the interference of high-voltage signal.
Usually, when designing output driving circuit, mainly consider the problem of the ability of drives heavy load, ternary output and logical device interface level compatibility.Typical CMOS output driving circuit as shown in Figure 1, comprises predrive circuit module, drive circuit and output protection circuit.Wherein predrive circuit is made up of the predrive circuit of tri-state control circuit T, pulling drive signal LP and the predrive circuit of drop-down drive singal LN; Its input of tri-state control circuit T A receives internal output enable signal D, and S end is by the enable control of output control terminal OEN signal; Output Z1 connects pull-up P pipe predrive circuit, and output Z2 connects drop-down N pipe predrive circuit; Upper drop-down predrive circuit is made up of the chain of inverters of amplifying gradually usually; Be reduced to the inverter of PMOS MP01 as shown in Figure 1 and NMOS tube MN01 composition, and the inverter of PMOS MP03 and NMOS tube MN03 composition; Pulling drive signal LP is drawn in the drain electrode of PMOS MP01 and the drain electrode of NMOS tube MN01, and drop-down drive singal LN is drawn in the drain electrode of PMOS MP03 and the drain electrode of NMOS tube MN03; Pulling drive signal LP and drop-down drive singal LN, drives pull-up output pmos MP02 and drop-down output NMOS tube MN05 respectively, draws output PAD between their drain electrode; Output protection circuit is connected to output PAD.
The operation principle of this circuit is as follows: enable signal OEN is effective, when data-signal D input low level, and the equal output low level of Z1, Z2.Now, PMOS MP01 and MP03 conducting, make pulling drive signal LP and drop-down drive singal LN signal be high level, NMOS tube MN05 conducting, PAD output low level voltage.When input D is high level VDD1, Z1, Z2 all export high level VDD1.Now, NMOS tube MN01 and NMOS tube MN03 conducting, make pulling drive signal LP and drop-down drive singal LN signal be low level, and pulling drive signal LP exports driving tube PMOS MP02 conducting, PAD output high level voltage VDD1.
Described output driving circuit, is powered by supply voltage VDD1, only can export single high level signal.This output long arc of cannot satisfying the demand, the application requirement changed to high level by low level.
In existing CMOS Driving technique, the method for level shift (Level shifter) is usually adopted to realize the boosting of output driving circuit, as Fig. 2.This circuit, except the necessary module of output driving circuit, also comprises a level shift module 201, power vd D2 and high voltage PMOS device MP21, MP23, MP22.Wherein the level of power vd D2 is higher than the level value of power vd D1.High tension apparatus is adopted effectively to prevent supply voltage from when comparatively low level VDD1 is switched to VDD2, puncturing of device.Level shift module 201 instead of the predrive circuit of the pulling drive signal LP be made up of PMOS MP01 and NMOS tube MN01 in Fig. 1.This circuit has the input signal D accepting relatively low level VDD1, and the boosting exporting high level VDD2 drives function.Specifically, when D input low level, the equal output low level of Z1, Z2.The low level voltage of signal 202 obtains 203 high level voltage VDD1 after inverter INV21, and make NMOS tube MN23 conducting, the grid voltage of PMOS MP21 moves low level voltage to, MP21 conducting, and pulling drive signal LP draws high VDD2, and PMOS MP22 turns off.Meanwhile, as D input high level VDD1, Z1, Z2 all export VDD1.NMOS tube MP21 conducting makes pulling drive signal LP ground connection, high voltage PMOS pipe MP02 conducting, and PAD exports the VDD2 with higher level.
As mentioned above, in CMOS technology of the same race, this level shift output driving circuit has several shortcoming: 1, draw high the PMOS exporting high level, as MP21, MP22, MP23 need to use high tension apparatus.In same technological design, adopt high tension apparatus increases circuit design difficulty and technique are realized difficulty, increase chip area while, also can bring more than power dissipation overhead; 2, because the threshold value of high tension apparatus is higher than commonplace components, if still transmit the flat VDD1 of small electric, electric device may be made to end, cannot normally export.Therefore, this circuit only possesses the function being boosted to VDD2 by VDD1, does not possess identical high level voltage transfer function, cannot need the level flexible conversion realizing output according to back-end circuit.3, relatively export termination heavy load situation, this circuit does not have the mechanism of quick lift.
Summary of the invention
The object of the invention is for overcoming the deficiencies in the prior art, a kind of of proposition realizes the output driving circuit exporting high level conversion.Utilize variable drive signal MID, make output driving circuit only adopt commonplace components to realize boost function without the need to high tension apparatus.Meanwhile, overcome the shortcoming of the unidirectional boosting of traditional circuit, output not only can effectively be boosted, also can realize the function of equal voltage levels transfer, improve the flexibility of output port output level.Utilize feedback circuit, solve output drive signal when exporting termination heavy load and draw high not enough problem.Increase and export isolation MN4 and MP3, the noise jamming of insulating power supply ground introducing effectively, improves output interface voltage endurance and reliability.
The technical scheme that the present invention solves is: a kind of output driving circuit realizing the conversion of output high level, comprise the first power vd D1, second source VDD2, output control circuit T, pull-up P pipe predrive circuit, pull-up export and drive PMOS MP2, drop-down output driving tube MN5, output isolation circuit, drop-down N pipe predrive circuit, variable drive signal MID circuit for generating, drop-down predrive circuit;
Output control circuit T is a tri-state control circuit, comprises data signal input A, enable signal input S, the first output Z1, the second output Z2;
Pull-up P pipe predrive circuit comprises the first output buffer BUF1, level shift buffer circuit SHIFT, the first inverter INV1, the second inverter INV2, the first predrive PMOS MP1, the first predrive NMOS tube MN1, exports P pipe feedback circuit;
First output buffer BUF1 comprises the tenth inverter INV10, the 11 inverter INV11;
Level shift buffer circuit SHIFT comprises the tenth PMOS MP10, the 11 PMOS MP11, the tenth NMOS tube MN10, the 11 NMOS tube MN11, the 8th inverter INV8, the 9th inverter INV9;
Export P pipe feedback circuit and comprise the second predrive NMOS tube MN2, the 3rd predrive NMOS tube MN3, the 3rd inverter INV3, the 4th inverter INV4;
Variable drive signal MID circuit for generating comprises the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9;
Drop-down predrive circuit comprises the second output buffer BUF2, the 5th inverter INV5, hex inverter INV6, the 7th inverter INV7; Second output buffer BUF2 comprises the 12 inverter INV12, the 13 inverter INV13;
Output isolation circuit comprises the 3rd and drives PMOS MP3, four-wheel drive NMOS tube MN4;
The input A of output control circuit T receives data-signal D, and enable signal input S receives enable signal OEN, and enable signal OEN controls output control circuit T, exports two paths of data signal from the first output Z1, the second output Z2;
The input that first output Z1 connects the input of the tenth inverter INV10, the output of the tenth inverter INV10 connects the 11 inverter INV11, the first via of the output of the 11 inverter INV11 connects the grid of the 12 PMOS MP12 and the grid of the 12 NMOS tube MN12, second tunnel of the output of the 11 inverter INV11 connects the input of the first inverter INV1, the output of the first inverter INV1 connects the input of the second inverter INV2, and the output of the second inverter INV2 connects the grid of the first predrive NMOS tube MN1;
8th inverter INV8 comprises the 12 PMOS MP12, the 12 NMOS tube MN12;
9th inverter INV9 comprises the 13 PMOS MP13, the 13 NMOS tube MN13;
The source class of the 12 PMOS MP12 is connected the first power vd D1 with substrate, the drain electrode of the 12 PMOS MP12 is connected the grid of the 13 PMOS MP13 and the grid of the 13 NMOS tube MN13 with the drain electrode of the 12 NMOS tube MN12, the source class of the 12 NMOS tube MN12 and the source class input MID signal of the 13 NMOS tube MN13; The source class of the 13 PMOS MP13 is connected the first power vd D1 with substrate, the drain electrode of the 13 PMOS MP13 is connected the grid of the 11 NMOS tube MN11 with the drain electrode of the 13 NMOS tube MN13; The drain electrode first via of the 11 NMOS tube MN11 connects the grid of the tenth PMOS MP10, and drain electrode second tunnel of the 11 NMOS tube MN11 connects the drain electrode of the 11 PMOS MP11; The source class of the 11 NMOS tube MN11 and the source class input MID signal of the tenth NMOS tube MN10; The source class of the tenth PMOS MP10 is connected second source VDD2 with the source class of substrate and the 11 PMOS MP11 with substrate; The grid of the 11 PMOS MP11, the drain electrode of the tenth PMOS MP10 and the drain electrode of the tenth NMOS tube MN10 are connected the grid of the first predrive PMOS MP1 simultaneously;
The substrate of the first predrive PMOS MP1 is connected second source VDD2 with source class, the drain electrode of the first predrive PMOS MP1 is connected the grid of the 4th predrive PMOS MP4 with the first via of the drain electrode of the first predrive NMOS tube MN1, the drain electrode of the first predrive PMOS MP1 is connected the input of the 3rd inverter INV3 with the second tunnel of the drain electrode of the first predrive NMOS tube MN1, the output predrive pull-up signal LP of the drain electrode of the first predrive NMOS tube MN1; The output first via of the 3rd inverter INV3 connects the grid of the 3rd NMOS tube MN3, output second tunnel of the 3rd inverter INV3 connects the input of the 4th inverter INV4, the output of the 4th inverter INV4 connects the grid of the second NMOS tube MN2, the source class ground connection of the second NMOS tube MN2, the source class input MID signal of the 3rd NMOS tube MN3; The drain electrode of the second NMOS tube MN2 is connected the source class of the first predrive NMOS tube MN1 with the drain electrode of the 3rd NMOS tube MN3;
The source class of the second PMOS MP2 drives the substrate of PMOS MP3 to be connected second source VDD2 with substrate and the 3rd, the drain electrode of the second PMOS MP2 connects the source class that the 3rd drives PMOS MP3,3rd drives the grid of PMOS MP3 to input MID signal, and the 3rd drives the drain electrode of PMOS MP3 and the drain electrode of four-wheel drive NMOS tube MN4 can realize the output of the output driving circuit exporting high level conversion as this; The grid of four-wheel drive NMOS tube MN4 connects the first power vd D1, and the source class of four-wheel drive NMOS tube MN4 connects the drain electrode of the 7th driving N metal-oxide-semiconductor MN7, the source class ground connection of the 7th driving N metal-oxide-semiconductor MN7; The grid of the 7th driving N metal-oxide-semiconductor MN7 connects the output of the 7th inverter INV7, the input of the 7th inverter INV7 connects the output of hex inverter INV6, the input of hex inverter INV6 connects the output of the 5th inverter INV5, the input of the 5th inverter INV5 connects the output of the 13 inverter INV13, the input of the 13 inverter INV13 connects the output of the 12 inverter INV12, and the input of the 12 inverter INV12 connects the second output Z2 of output control circuit T;
The source class of the 4th PMOS MP4 is connected second source VDD2 with the substrate of substrate and the 3rd PMOS MP3, the grid of the 4th PMOS MP4 is connected the drain electrode of the 5th PMOS MP5 with the drain electrode of the 4th PMOS MP4, the grounded-grid of the 5th PMOS MP5, the drain electrode of the 5th PMOS MP5 connects the source class of the 6th PMOS MP6, the grid of the 6th PMOS MP6 and the grid of drain electrode connection the 8th NMOS tube MN8 and drain electrode, the grid of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6, the source class of the 8th NMOS tube MN8 connects drain electrode and the substrate of the 7th PMOS MP7, the grid of the 7th PMOS MP7 and source class ground connection, the source class of the 6th NMOS tube MN6 and the drain electrode of the 6th NMOS tube MN6 connect, the drain electrode of the source class of the 7th NMOS tube MN7, the grid of the 9th NMOS tube MN9, the 8th PMOS MP8 connects and exports MID signal, the grid of the 8th PMOS MP8 and source class ground connection, the substrate of the 8th PMOS MP8 connects the drain electrode of the 9th PMOS MP9, and the grounded-grid of the 9th PMOS MP9, the substrate of the 9th PMOS MP9 is connected the first power vd D1 with source class.Not elsewhere specified circuit is powered by power vd D1.
Beneficial effect compared with prior art of the present invention is:
(1) the present invention proposes a kind of output driving circuit realizing exporting high level conversion.Utilize variable drive signal MID, required high tension apparatus is all replaced to common device work.Compared with the high tension apparatus technology in background technology, processing compatibility improves, and realizes difficulty little, eliminates the problem that high tension apparatus chip area is large, reduce circuit power consumption expense.
(2) a kind of of the present invention's proposition realizes the output driving circuit exporting high level conversion, utilize variable drive signal MID, output not only effectively can be boosted, also can realize the function of equal voltage levels transfer, improve the flexibility of output port output level.
(3) a kind of of the present invention's proposition realizes the output driving circuit exporting high level conversion, utilizes predrive P pipe feedback module, drags down drive singal fast, accelerates to export driving.
(4) a kind of output driving circuit realizing the conversion of output high level of the present invention's proposition, increase to export and isolate MN4 and MP3, the noise jamming effectively introduced, improves output interface voltage endurance and reliability insulating power supply.
Accompanying drawing explanation
Fig. 1 is the present invention typical case CMOS output driving circuit theory diagram;
Fig. 2 is the output driving circuit theory diagram of band level shift of the present invention;
Fig. 3 is that the present invention is for realizing turning without the low incoming level of high tension apparatus the circuit diagram of high output level;
(a) of Fig. 4, for the present invention is for realizing the circuit theory diagrams of the first output buffer BUF1, (b) is for realizing the circuit theory diagrams of the second output buffer BUF2;
(a) of Fig. 5 is for the present invention is for realizing the circuit theory diagrams of pull-up P pipe pre-output level shift buffer circuit SHIFT, the inverter INV8 schematic diagram of (b) auxiliary level shift circuit, the inverter INV9 schematic diagram of (c) auxiliary level shift circuit.
Fig. 6 is the biasing circuit schematic diagram of the present invention for generation of variable drive signal MID.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is explained.
As shown in Figure 3, the present invention proposes a kind of output driving circuit realizing exporting high level conversion, comprise the first power vd D1, second source VDD2, output control circuit T, pull-up P pipe predrive circuit, pull-up export and drive PMOS MP2, drop-down output driving tube MN5, output isolation circuit, drop-down N pipe predrive circuit, variable drive signal MID circuit for generating, drop-down predrive circuit.
As shown in Figure 3, output control circuit T is a tri-state control circuit, comprises data signal input A, enable signal input S, the first output Z1, the second output Z2;
As shown in Figure 3, pull-up P pipe predrive circuit comprises the first output buffer BUF1, level shift buffer circuit SHIFT, the first inverter INV1, the second inverter INV2, the first predrive PMOS MP1, the first predrive NMOS tube MN1, exports P pipe feedback circuit;
As shown in Fig. 4 (a), the first output buffer BUF1 comprises the tenth inverter INV10, the 11 inverter INV11;
As shown in Figure 5, level shift buffer circuit SHIFT comprises the tenth PMOS MP10, the 11 PMOS MP11, the tenth NMOS tube MN10, the 11 NMOS tube MN11, the 8th inverter INV8, the 9th inverter INV9; 8th inverter INV8 comprises the 12 PMOS MP12, the 12 NMOS tube MN12; 9th inverter INV9 comprises the 13 PMOS MP13, the 13 NMOS tube MN13;
As shown in Figure 3, export P pipe feedback circuit and comprise the second predrive NMOS tube MN2, the 3rd predrive NMOS tube MN3, the 3rd inverter INV3, the 4th inverter INV4;
As shown in Figure 6, variable drive signal MID circuit for generating comprises the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9;
As shown in Figure 3, drop-down predrive circuit comprises the second output buffer BUF2, the 5th inverter INV5, hex inverter INV6, the 7th inverter INV7;
As shown in Fig. 4 (b), the second output buffer BUF2 comprises the 12 inverter INV12, the 13 inverter INV13;
As shown in Figure 3, output isolation circuit comprises the 3rd driving PMOS MP3, four-wheel drive NMOS tube MN4;
As shown in Figure 3, the input A of output control circuit T receives data-signal D, and enable signal input S receives enable signal OEN, and enable signal OEN controls output control circuit T, exports two paths of data signal from the first output Z1, the second output Z2.
As shown in Figure 4, first output Z1 connects the input of the tenth inverter INV10, the output of the tenth inverter INV10 connects the input of the 11 inverter INV11, the first via of the output of the 11 inverter INV11 connects the grid of the 12 PMOS MP12 and the grid of the 12 NMOS tube MN12, second tunnel of the output of the 11 inverter INV11 connects the input of the first inverter INV1, the output of the first inverter INV1 connects the input of the second inverter INV2, the output of the second inverter INV2 connects the grid of the first predrive NMOS tube MN1,
As shown in Figure 5, the source class of the 12 PMOS MP12 is connected the first power vd D1 with substrate, the drain electrode of the 12 PMOS MP12 is connected the grid of the 13 PMOS MP13 and the grid of the 13 NMOS tube MN13 with the drain electrode of the 12 NMOS tube MN12, the source class of the 12 NMOS tube MN12 and the source class input MID signal of the 13 NMOS tube MN13; The source class of the 13 PMOS MP13 is connected the first power vd D1 with substrate, the drain electrode of the 13 PMOS MP13 is connected the grid of the 11 NMOS tube MN11 with the drain electrode of the 13 NMOS tube MN13; The drain electrode first via of the 11 NMOS tube MN11 connects the grid of the tenth PMOS MP10, and drain electrode second tunnel of the 11 NMOS tube MN11 connects the drain electrode of the 11 PMOS MP11; The source class of the 11 NMOS tube MN11 and the source class input MID signal of the tenth NMOS tube MN10; The source class of the tenth PMOS MP10 is connected second source VDD2 with the source class of substrate and the 11 PMOS MP11 with substrate; The grid of the 11 PMOS MP11, the drain electrode of the tenth PMOS MP10 and the drain electrode of the tenth NMOS tube MN10 are connected the grid of the first predrive PMOS MP1 simultaneously;
As shown in Figure 3, the substrate of the first predrive PMOS MP1 is connected second source VDD2 with source class, the drain electrode of the first predrive PMOS MP1 is connected the grid of the 4th predrive PMOS MP4 with the first via of the drain electrode of the first predrive NMOS tube MN1, the drain electrode of the first predrive PMOS MP1 is connected the input of the 3rd inverter INV3 with the second tunnel of the drain electrode of the first predrive NMOS tube MN1, the output predrive pull-up signal LP of the drain electrode of the first predrive NMOS tube MN1; The output first via of the 3rd inverter INV3 connects the grid of the 3rd NMOS tube MN3, output second tunnel of the 3rd inverter INV3 connects the input of the 4th inverter INV4, the output of the 4th inverter INV4 connects the grid of the second NMOS tube MN2, the source class ground connection of the second NMOS tube MN2, the source class input MID signal of the 3rd NMOS tube MN3; The drain electrode of the second NMOS tube MN2 is connected the source class of the first predrive NMOS tube MN1 with the drain electrode of the 3rd NMOS tube MN3;
As shown in Figure 3, the source class of the second PMOS MP2 drives the substrate of PMOS MP3 to be connected second source VDD2 with substrate and the 3rd, the drain electrode of the second PMOS MP2 connects the source class that the 3rd drives PMOS MP3,3rd drives the grid of PMOS MP3 to input MID signal, and the 3rd drives the drain electrode of PMOS MP3 and the drain electrode of four-wheel drive NMOS tube MN4 can realize the output of the output driving circuit exporting high level conversion as this; The grid of four-wheel drive NMOS tube MN4 connects the first power vd D1, and the source class of four-wheel drive NMOS tube MN4 connects the drain electrode of the 7th driving N metal-oxide-semiconductor MN7, the source class ground connection of the 7th driving N metal-oxide-semiconductor MN7; The grid of the 7th driving N metal-oxide-semiconductor MN7 connects the output of the 7th inverter INV7, the input of the 7th inverter INV7 connects the output of hex inverter INV6, the input of hex inverter INV6 connects the output of the 5th inverter INV5, the input of the 5th inverter INV5 connects the output of the 13 inverter INV13, the input of the 13 inverter INV13 connects the output of the 12 inverter INV12, and the input of the 12 inverter INV12 connects the second output Z2 of output control circuit T;
As shown in Figure 3, the source class of the 4th PMOS MP4 is connected second source VDD2 with the substrate of substrate and the 3rd PMOS MP3, the grid of the 4th PMOS MP4 is connected the drain electrode of the 5th PMOS MP5 with the drain electrode of the 4th PMOS MP4, the grounded-grid of the 5th PMOS MP5, the drain electrode of the 5th PMOS MP5 connects the source class of the 6th PMOS MP6, the grid of the 6th PMOS MP6 and the grid of drain electrode connection the 8th NMOS tube MN8 and drain electrode, the grid of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6, the source class of the 8th NMOS tube MN8 connects drain electrode and the substrate of the 7th PMOS MP7, the grid of the 7th PMOS MP7 and source class ground connection, the source class of the 6th NMOS tube MN6 and the drain electrode of the 6th NMOS tube MN6 connect, the drain electrode of the source class of the 7th NMOS tube MN7, the grid of the 9th NMOS tube MN9, the 8th PMOS MP8 connects and exports MID signal, the grid of the 8th PMOS MP8 and source class ground connection, the substrate of the 8th PMOS MP8 connects the drain electrode of the 9th PMOS MP9, and the grounded-grid of the 9th PMOS MP9, the substrate of the 9th PMOS MP9 is connected the first power vd D1 with source class.
In example, VDD1 is 2.5V, VDD2 is optional 3.3V or 2.5V, and circuit has two kinds of operating states: high-impedance state and normal operating conditions.
(1) output circuit is in high resistant operating state:
When output control terminal OEN is high level voltage 2.5V, the output signal Z1 of output control circuit T and Z2 is output low level voltage 0V and high level voltage 2.5V respectively, Z1 is through BUF1 drive level displacement buffer circuit SHIFT, output low level voltage MID, drive PMOS MP1 conducting, pulling drive signal LP is pulled to optional high level 3.3V or 2.5V, and pulling drive pipe PMOS MP2 is turned off.Meanwhile, Z2 obtains LN output low level voltage 0V through the chain of inverters that BUF2 and INV5, INV6, INV7 form, and drop-down driving tube MN5 conducting turns off.Circuit exports and shows as high-impedance state.
(2) output circuit is in normal operating conditions:
When output control terminal OEN is low level voltage 0V, output control circuit T normal output signal, Z1 and Z2 responds input signal D.
(1) as signal D input low level voltage 0V, Z1 is through BUF1 drive level displacement buffer circuit SHIFT, and clamper output low level voltage 307, is worth for MID.Low pressure MID signal drives PMOS MP1 conducting, and pulling drive signal LP is pulled to high level 3.3V/2.5V, and PMOS MP2 turns off.Now, form chain of inverters output low level voltage 0V by inverter INV1 and INV2, NMOS tube MN1 closes.Further, the inverter INV3 that pulling drive signal LP drives, INV4 exports 302 high level voltage 2.5V, makes NMOS tube MN2 conducting, and the parasitic capacitance electric charge at node 303 place passes through MN2 repid discharge to low level voltage 0V.Low level voltage Z2 is through BUF2 and inverter INV5 simultaneously, and obtain drop-down drive singal LN after the chain of inverters of INV6, INV7 composition, now, LN is high level voltage 2.5V, drop-down driving N metal-oxide-semiconductor MN5 conducting, exports PAD and is pulled to low level voltage 0V.
(2) as signal D putting high level voltage 2.5V, Z1, Z2 respond output high level voltage 2.5V.Z2 obtains the drop-down drive singal LN of low level voltage 0V through the chain of inverters that BUF2 and INV5, INV6, INV7 form, and drop-down driving tube MN5 turns off.Meanwhile, Z1, through BUF1 rear drive level shift circuit SHIFT, obtains output high level voltage 3.3V/2.5V, and predrive PMOS MP1 is turned off.Now, chain of inverters INV1 and INV2 output high level voltage 2.5V, make NMOS tube MN1 conducting, now, NMOS tube MN2 does not also turn off in time, and the spurious charge on node 303 and node 304 and NMOS tube MN2 is discharged by NMOS tube MN2.Along with spurious charge reduces gradually, pulling drive signal LP starts to decline, until during high threshold voltage lower than inverter INV3, inverter INV3 overturns, and makes node 305 output high level voltage 2.5V, and then makes NMOS tube MN3 conducting.Meanwhile, INV4 output low level voltage makes NMOS tube MN2 turn off.Spurious charge on node 304 utilizes NMOS tube MN1 and NMOS tube MN3 to accelerate electric discharge further, until pulling drive signal LP is pulled low to level voltage MID, this voltage makes driving tube MP2 conducting.PAD output high level voltage 3.3V/2.5V.So far, PAD completes the lever boosting conversion of 2.5V to 3.3/2.5V.
Need illustrate situation have following some:
(1) explanation of level shift circuit SHIFT circuit.Level shift circuit SHIFT, as shown in Fig. 5 (a), exports the level shift circuit of buffering in the present invention as one.When A inputs 0V, through inverter INV8 and INV9, output level is 2.5V signal 501 and variable drive low level MID signal respectively.The circuit theory of INV8 and INV9 is as Fig. 5 (b) and Fig. 5 (c), and the inverter be made up of PMOS MP4 and NMOS tube MN5, high output level is 2.5V, and low output level is to MID.Now, NMOS tube MN11 turns off, NMOS tube MN10 conducting, PMOS MP11 conducting, and the latch that intersects makes to export OUT and is clamped to low level voltage MID.When A is input as high level voltage 2.5V, it is low level voltage MID that inverter INV8 outputs signal 501, MN10 turns off, INV9 output high level voltage 2.5V, MN11 conducting, make node 502 be pulled low to low level voltage MID, simultaneously PMOS MP10 conducting, OUT intersection latches output high level voltage 3.3V.Level shifting buffer SHIFT, utilizes MID signal, when without the need to high tension apparatus, obtains optional high level 3.3V or 2.5V and exports.
(2) variable drive signal MID signal.MID Design of Signal is a middle low level voltage value, and as shown in Figure 6, MID signal is connected on the grid end of PMOS driving tube MP2, as the pull-up P pipe drive singal LP exporting PAD.As Suo Shi Fig. 6 (a) usually by this voltage design to 0V, when making the difference DELTA 1=0V-2.5V between itself and power supply.That is to say, when making the VGS=-2.5V of efferent duct, meet the requirement exporting fast and drive.Realize boost function, supply voltage must be raised to 3.3V by 2.5V, that is to say, the voltage difference between grid source rises to Δ
2=0V-3.3V.According to the requirement of above-mentioned design, under 0.25um process conditions, for ensureing that transistor can not cause because of overvoltage puncturing, MP2 etc. must adopt high tension apparatus, and this will increase technological design difficulty, are unfavorable for the compatibility of CMOS technology.In the present invention, still adopt the transistor MP2 of common process, improve the voltage of MID, make the voltage difference VGS=Δ at two ends, MP2 pipe grid source
3=MID-3.3V approximates-2.5V, and to ensure when not adopting high tension apparatus, MP2 pipe still can normally work effectively.Usually, gate source voltage difference VGS=Δ
4the absolute value of=MID-2.5V is greater than the absolute value of the threshold value of PMOS | V
th, P|, then can not affect the normal work exporting driving tube.Thus, the voltage range can releasing MID is greater than 0.8V, is less than 2.5-|V
th, p|.A kind of realizing circuit of MID signal is given, as shown in Fig. 6 (b) in the present invention.Power electric crimping 3.3V/2.5V, PMOS MP4, MP6, MP7 adopt diode to connect and make resistance, and the ratio of W/L (grid width and grid length) is 1.PMOS MP5 is normal open pipe, and NMOS tube MN8 also adopts diode to connect, and during design, W/L is not easily too large.Concrete magnitude of voltage is about VGS, 8 overdrive voltages adding a PMOS MP7.This voltage provides biased for rear class NMOS tube MN7.PMOS MP9 powers for the substrate bias of PMOS MP8 separately, and PMOS MP8 is designed to the small resistor that diode connects.Node 601 and 602, meets MN6 and MN9 that NMOS tube makes mos capacitance respectively, plays the effect of filtering, suppresses the signal noise that main circuit recalcitrates by signal fluctuation.This design effectively ensure that the symmetry of node 601 and node 602 both sides branch road and the accuracy of signal.Optionally access 3.3V or 2.5V according to VDD2, the low level MID signal of exportable about 0.8V or 0.5V of this circuit, produces a desired effect.
(3) feedback control loop.In traditional pull-up predrive circuit, be not with feedback control loop, as shown in Figure 1, only discharge by single tube MN01, therefore, cannot fast and effeciently discharge to pulling drive signal LP.In the present invention, the feedback module of increase can accelerate the electric discharge of LP signal.Further illustrate in conjunction with example, owing to have employed variable drive voltage MID, when VDD2 connects 3.3V voltage, gate source voltage difference VGS=Δ on PMOS MP2
3=0.8-3.3V ≈-2.5V, pull-up output transistor MP2 grid input range increases, now, and still can fast driving successive load without the need to feedback module.But when VDD2 connects 2.5V voltage, the absolute value of gate source voltage difference on PMOS MP4 | VGS|=| Δ
3|=| 0.5-2.5V|<2.5V.Now, utilize feedback circuit repid discharge to low level voltage, while effectively driving successive load, accelerate the driving to successive load, delay rise time is reduced.Note, MN2 be designed to wide be less than long fall than managing, play the effect of resistance.
(4) inverter number explanation.As shown in the figure, the NMOS tube MN1 on Z1 branch road can regard one-level inverter as, therefore, have passed through altogether Pyatyi reverse drive from the output of ZI to the grid of driving tube MP2.When designing, the inverter number of two branch roads of buffer BUF1 should be consistent.The chain of inverters that Z2 branch road is made up of buffer BUF2 and inverter INV5, INV6, INV7 also have passed through Pyatyi reverse drive altogether.When designing, Z1 branch road could be kept consistent with the time delay of Z2 branch road, make the rising edge time delay of output drive signal substantially equal with trailing edge time delay.
The content be not described in detail in specification of the present invention belongs to the known technology of professional and technical personnel in the field.Although describe embodiments of the present invention by reference to the accompanying drawings, those of ordinary skill in the art can make various distortion or amendment within the scope of the appended claims.
Claims (6)
1. one kind can realize the output driving circuit exporting high level conversion, it is characterized in that: comprise the first power vd D1, second source VDD2, output control circuit T, pull-up P pipe predrive circuit, pull-up export and drive PMOS MP2, drop-down output driving tube MN5, output isolation circuit, drop-down N pipe predrive circuit, variable drive signal MID circuit for generating, drop-down predrive circuit;
Output control circuit T is a tri-state control circuit, comprises data signal input A, enable signal input S, the first output Z1, the second output Z2;
Pull-up P pipe predrive circuit comprises the first output buffer BUF1, level shift buffer circuit SHIFT, the first inverter INV1, the second inverter INV2, the first predrive PMOS MP1, the first predrive NMOS tube MN1, exports P pipe feedback circuit;
First output buffer BUF1 comprises the tenth inverter INV10, the 11 inverter INV11;
Level shift buffer circuit SHIFT comprises the tenth PMOS MP10, the 11 PMOS MP11, the tenth NMOS tube MN10, the 11 NMOS tube MN11, the 8th inverter INV8, the 9th inverter INV9;
Export P pipe feedback circuit and comprise the second predrive NMOS tube MN2, the 3rd predrive NMOS tube MN3, the 3rd inverter INV3, the 4th inverter INV4;
Variable drive signal MID circuit for generating comprises the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9;
Drop-down predrive circuit comprises the second output buffer BUF2, the 5th inverter INV5, hex inverter INV6, the 7th inverter INV7; Second output buffer BUF2 comprises the 12 inverter INV12, the 13 inverter INV13;
Output isolation circuit comprises the 3rd and drives PMOS MP3, four-wheel drive NMOS tube MN4;
The input A of output control circuit T receives data-signal D, and enable signal input S receives enable signal OEN, and enable signal OEN controls output control circuit T, exports two paths of data signal from the first output Z1, the second output Z2;
The input that first output Z1 connects the input of the tenth inverter INV10, the output of the tenth inverter INV10 connects the 11 inverter INV11, the first via of the output of the 11 inverter INV11 connects the grid of the 12 PMOS MP12 and the grid of the 12 NMOS tube MN12, second tunnel of the output of the 11 inverter INV11 connects the input of the first inverter INV1, the output of the first inverter INV1 connects the input of the second inverter INV2, and the output of the second inverter INV2 connects the grid of the first predrive NMOS tube MN1;
8th inverter INV8 comprises the 12 PMOS MP12, the 12 NMOS tube MN12;
9th inverter INV9 comprises the 13 PMOS MP13, the 13 NMOS tube MN13;
The source class of the 12 PMOS MP12 is connected the first power vd D1 with substrate, the drain electrode of the 12 PMOS MP12 is connected the grid of the 13 PMOS MP13 and the grid of the 13 NMOS tube MN13 with the drain electrode of the 12 NMOS tube MN12, the source class of the 12 NMOS tube MN12 and the source class input MID signal of the 13 NMOS tube MN13; The source class of the 13 PMOS MP13 is connected the first power vd D1 with substrate, the drain electrode of the 13 PMOS MP13 is connected the grid of the 11 NMOS tube MN11 with the drain electrode of the 13 NMOS tube MN13; The drain electrode first via of the 11 NMOS tube MN11 connects the grid of the tenth PMOS MP10, and drain electrode second tunnel of the 11 NMOS tube MN11 connects the drain electrode of the 11 PMOS MP11; The source class of the 11 NMOS tube MN11 and the source class input MID signal of the tenth NMOS tube MN10; The source class of the tenth PMOS MP10 is connected second source VDD2 with the source class of substrate and the 11 PMOS MP11 with substrate; The grid of the 11 PMOS MP11, the drain electrode of the tenth PMOS MP10 and the drain electrode of the tenth NMOS tube MN10 are connected the grid of the first predrive PMOS MP1 simultaneously;
The substrate of the first predrive PMOS MP1 is connected second source VDD2 with source class, the drain electrode of the first predrive PMOS MP1 is connected the grid of the 4th predrive PMOS MP4 with the first via of the drain electrode of the first predrive NMOS tube MN1, the drain electrode of the first predrive PMOS MP1 is connected the input of the 3rd inverter INV3 with the second tunnel of the drain electrode of the first predrive NMOS tube MN1, the output predrive pull-up signal LP of the drain electrode of the first predrive NMOS tube MN1; The output first via of the 3rd inverter INV3 connects the grid of the 3rd NMOS tube MN3, output second tunnel of the 3rd inverter INV3 connects the input of the 4th inverter INV4, the output of the 4th inverter INV4 connects the grid of the second NMOS tube MN2, the source class ground connection of the second NMOS tube MN2, the source class input MID signal of the 3rd NMOS tube MN3; The drain electrode of the second NMOS tube MN2 is connected the source class of the first predrive NMOS tube MN1 with the drain electrode of the 3rd NMOS tube MN3;
The source class of the second PMOS MP2 drives the substrate of PMOS MP3 to be connected second source VDD2 with substrate and the 3rd, the drain electrode of the second PMOS MP2 connects the source class that the 3rd drives PMOS MP3,3rd drives the grid of PMOS MP3 to input MID signal, and the 3rd drives the drain electrode of PMOS MP3 and the drain electrode of four-wheel drive NMOS tube MN4 can realize the output of the output driving circuit exporting high level conversion as this; The grid of four-wheel drive NMOS tube MN4 connects the first power vd D1, and the source class of four-wheel drive NMOS tube MN4 connects the drain electrode of the 7th driving N metal-oxide-semiconductor MN7, the source class ground connection of the 7th driving N metal-oxide-semiconductor MN7; The grid of the 7th driving N metal-oxide-semiconductor MN7 connects the output of the 7th inverter INV7, the input of the 7th inverter INV7 connects the output of hex inverter INV6, the input of hex inverter INV6 connects the output of the 5th inverter INV5, the input of the 5th inverter INV5 connects the output of the 13 inverter INV13, the input of the 13 inverter INV13 connects the output of the 12 inverter INV12, and the input of the 12 inverter INV12 connects the second output Z2 of output control circuit T;
The source class of the 4th PMOS MP4 is connected second source VDD2 with the substrate of substrate and the 3rd PMOS MP3, the grid of the 4th PMOS MP4 is connected the drain electrode of the 5th PMOS MP5 with the drain electrode of the 4th PMOS MP4, the grounded-grid of the 5th PMOS MP5, the drain electrode of the 5th PMOS MP5 connects the source class of the 6th PMOS MP6, the grid of the 6th PMOS MP6 and the grid of drain electrode connection the 8th NMOS tube MN8 and drain electrode, the grid of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6, the source class of the 8th NMOS tube MN8 connects drain electrode and the substrate of the 7th PMOS MP7, the grid of the 7th PMOS MP7 and source class ground connection, the source class of the 6th NMOS tube MN6 and the drain electrode of the 6th NMOS tube MN6 connect, the drain electrode of the source class of the 7th NMOS tube MN7, the grid of the 9th NMOS tube MN9, the 8th PMOS MP8 connects and exports MID signal, the grid of the 8th PMOS MP8 and source class ground connection, the substrate of the 8th PMOS MP8 connects the drain electrode of the 9th PMOS MP9, and the grounded-grid of the 9th PMOS MP9, the substrate of the 9th PMOS MP9 is connected the first power vd D1 with source class.
2. a kind of output driving circuit realizing the conversion of output high level according to claim 1, is characterized in that: described PMOS MP1, PMOS MP4 are common process transistor.
3. a kind of output driving circuit realizing the conversion of output high level according to claim 1, is characterized in that: the level of described second source VDD2 is equal to or higher than the level of the first power vd D1.
4. a kind of output driving circuit realizing the conversion of output high level according to claim 1, is characterized in that: the scope of the level of described MID signal is greater than VDD2-VDD1, and is less than VDD1-|V
th, p2|, wherein V
th, p2for the threshold voltage of pulling drive PMOS MP2.
5. a kind of output driving circuit realizing the conversion of output high level according to claim 1, it is characterized in that: described 3rd inverter INV3 and the 4th inverter INV4, second NMOS tube MN2, the feedback circuit that 3rd NMOS tube MN3 is formed, positive feedback structure can be formed, drag down drive singal fast, accelerate to export driving.
6. a kind of output driving circuit realizing the conversion of output high level according to claim 1, it is characterized in that: described 3rd PMOS MP3 the 4th NMOS tube MN4, the noise jamming of insulating power supply ground introducing effectively, improves this voltage endurance that can realize the output driving circuit output interface exporting high level conversion and reliability.
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| CN116827333A (en) * | 2023-08-28 | 2023-09-29 | 苏州锴威特半导体股份有限公司 | Level shift circuit |
| CN116827333B (en) * | 2023-08-28 | 2023-11-03 | 苏州锴威特半导体股份有限公司 | Level shift circuit |
| CN117318697A (en) * | 2023-09-15 | 2023-12-29 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
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| CN104638887B (en) | 2017-02-22 |
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