CN104638887A - Output driving circuit capable of realizing output high level conversion - Google Patents

Abstract

The present invention proposes an output driving circuit capable of realizing output high level conversion, which is characterized in that it includes a first power supply VDD1, a second power supply VDD2, an output control circuit T, a pull-up P tube pre-driver circuit, and a pull-up output driver PMOS tube MP2, pull-down output drive tube MN5, output isolation circuit, pull-down N tube pre-drive circuit, variable drive signal MID generating circuit, pull-down pre-drive circuit. The pull-up P tube pre-driver circuit is pulled up by the level shift buffer circuit SHIFT and accelerated by the feedback circuit to provide a variable drive signal MID for the drive tube MP2, so that the entire circuit can output high level without high-voltage devices. voltage conversion. Compared with other circuits, the characteristics of this technology are: no additional high-voltage device output tube; different options for low-level input and high-level output; fast drive load; power supply noise isolation; small area; low power consumption Small.

Description

An output drive circuit that can realize output high level conversion

technical field

The invention relates to an output drive circuit capable of converting low-level voltage to high-level voltage without using high-voltage devices, and more specifically relates to the field of level converter and integrated circuit I/O design.

Background technique

With the diversification of the development of integrated circuits, integrated circuits operating at various levels of voltage have been derived. Proper signal levels ensure reliable system operation and prevent damage to sensitive circuits due to excessively high or low voltage conditions. Inputs below the desired level will reduce the signal noise margin, while inputs that are too large will cause excessive energy loss. In order to effectively transmit signals, integrated circuits usually use input/output (I/O) interfaces as a bridge between low voltage and high voltage, so that low voltage signals can be completely transmitted without interference from high voltage signals.

Usually, when designing an output drive circuit, the main considerations are the ability of the circuit to drive a large load, the three-state output, and the level compatibility of the logic device interface. A typical CMOS output drive circuit is shown in Figure 1, including a pre-drive circuit module, a drive circuit and an output protection circuit. The pre-drive circuit is composed of a three-state control circuit T, a pre-drive circuit of the pull-up drive signal LP and a pre-drive circuit of the pull-down drive signal LN; the input terminal A of the three-state control circuit T receives the internal output signal D, and the S terminal receives the output signal The control terminal OEN signal enables control; the output terminal Z1 is connected to the pull-up P tube pre-driver circuit, and the output terminal Z2 is connected to the pull-down N tube pre-driver circuit; the pull-up and pull-down pre-driver circuit is usually composed of a gradually enlarged inverter chain; simplified as The inverter composed of PMOS transistor MP01 and NMOS transistor MN01 shown in Figure 1, and the inverter composed of PMOS transistor MP03 and NMOS transistor MN03; the drain of PMOS transistor MP01 and the drain of NMOS transistor MN01 lead to a pull-up drive signal LP, the drain of the PMOS transistor MP03 and the drain of the NMOS transistor MN03 lead to the pull-down drive signal LN; the pull-up drive signal LP and the pull-down drive signal LN respectively drive the pull-up output PMOS transistor MP02 and the pull-down output NMOS transistor MN05, and their drains The output terminal PAD is drawn between the poles; the output protection circuit is connected to the output terminal PAD.

The working principle of the circuit is as follows: the enable signal OEN is valid, and when the data signal D inputs a low level, both Z1 and Z2 output a low level. At this time, the PMOS transistors MP01 and MP03 are turned on, so that the pull-up driving signal LP and the pull-down driving signal LN are both at high level, the NMOS transistor MN05 is turned on, and the PAD outputs a low-level voltage. When input D is high level VDD1, both Z1 and Z2 output high level VDD1. At this time, the NMOS transistor MN01 and the NMOS transistor MN03 are turned on, so that the pull-up drive signal LP and the pull-down drive signal LN signal are both low level, the pull-up drive signal LP output drives the PMOS transistor MP02, and the PAD outputs a high level Voltage VDD1.

The output drive circuit is powered by the power supply voltage VDD1 and can only output a single high-level signal. This cannot meet the application requirements that require a large output swing and transition from low level to high level.

In the existing CMOS drive technology, the method of level shift (Level shifter) is usually used to boost the output drive circuit, as shown in Figure 2. In addition to the modules necessary for the output drive circuit, the circuit also includes a level shift module 201, a power supply VDD2 and high-voltage PMOS devices MP21, MP23, and MP22. The level of the power supply VDD2 is higher than the level of the power supply VDD1. The high voltage device is used to effectively prevent the breakdown of the device when the power supply voltage is switched from a lower level VDD1 to VDD2. The level shift module 201 replaces the pre-driver circuit for the pull-up drive signal LP composed of the PMOS transistor MP01 and the NMOS transistor MN01 in FIG. 1 . The circuit has a boost driving function of receiving a relatively low level VDD1 input signal D and outputting a high level VDD2. Specifically, when D inputs low level, both Z1 and Z2 output low level. The low-level voltage of the signal 202 passes through the inverter INV21 to obtain the high-level voltage VDD1 of 203, so that the NMOS transistor MN23 is turned on, the gate voltage of the PMOS transistor MP21 is pulled to a low-level voltage, MP21 is turned on, and the driving signal LP is pulled up. Pull up to VDD2, PMOS transistor MP22 is turned off. At the same time, when D inputs high level VDD1, both Z1 and Z2 output VDD1. The NMOS transistor MP21 is turned on so that the pull-up driving signal LP is grounded, the high-voltage PMOS transistor MP02 is turned on, and the output of the PAD has a relatively high level VDD2.

As mentioned above, in the same CMOS process, this level-shift output drive circuit has several disadvantages: 1. PMOS transistors that pull up the output high level, such as MP21, MP22, and MP23, need to use high-voltage devices. In the same process design, the use of high-voltage devices will increase the difficulty of circuit design and process implementation. While increasing the layout area, it will also bring excessive power consumption; 2. Since the threshold of high-voltage devices is higher than that of ordinary devices, If the relatively small level VDD1 is still transmitted, the electrical device may be cut off and cannot be output normally. Therefore, this circuit only has the function of boosting voltage from VDD1 to VDD2, but does not have the same high-level voltage transmission function, and cannot flexibly switch the output level according to the needs of the back-end circuit. 3. Compared with the case where the output terminal is connected to a large load, the circuit does not have a fast pull-up mechanism.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art, and propose an output driving circuit capable of realizing output high-level conversion. Utilizing the variable driving signal MID, the output driving circuit can realize the voltage boosting function without using high-voltage devices and only using ordinary devices. At the same time, it overcomes the disadvantage of unidirectional boosting in the traditional circuit, so that the output terminal can not only effectively boost the voltage, but also realize the function of equal level shifting, which improves the flexibility of the output level of the output port. The feedback circuit is used to solve the problem of insufficient pull-up of the output drive signal when the output terminal is connected to a large load. Increase the output isolation MN4 and MP3, effectively isolate the noise interference introduced by the power ground, and improve the withstand voltage characteristics and reliability of the output interface.

The technical solution solved by the present invention is: an output driving circuit capable of realizing output high level conversion, including a first power supply VDD1, a second power supply VDD2, an output control circuit T, a pull-up P tube pre-driver circuit, and a pull-up output driver PMOS tube MP2, pull-down output drive tube MN5, output isolation circuit, pull-down N tube pre-drive circuit, variable drive signal MID generation circuit, pull-down pre-drive circuit;

The output control circuit T is a three-state control circuit, including a data signal input terminal A, an enable signal input terminal S, a first output terminal Z1, and a second output terminal Z2;

The pull-up P tube pre-driver circuit includes a first output buffer BUF1, a level shift buffer circuit SHIFT, a first inverter INV1, a second inverter INV2, a first pre-drive PMOS transistor MP1, a first pre-drive NMOS transistor MN1, output P tube feedback circuit;

The first output buffer BUF1 includes a tenth inverter INV10 and an eleventh inverter INV11;

The level shift buffer circuit SHIFT includes a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, an eighth inverter INV8, and a ninth inverter INV9;

The output P-tube feedback circuit includes a second pre-drive NMOS transistor MN2, a third pre-drive NMOS transistor MN3, a third inverter INV3, and a fourth inverter INV4;

The variable driving signal MID generating circuit includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a sixth NMOS transistor MN6, The seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9;

The pull-down pre-drive circuit includes a second output buffer BUF2, a fifth inverter INV5, a sixth inverter INV6, and a seventh inverter INV7; the second output buffer BUF2 includes a twelfth inverter INV12, a tenth inverter Three inverters INV13;

The output isolation circuit includes a third driving PMOS transistor MP3 and a fourth driving NMOS transistor MN4;

The input terminal A of the output control circuit T receives the data signal D, the enable signal input terminal S receives the enable signal OEN, the enable signal OEN controls the output control circuit T, and outputs two channels from the first output terminal Z1 and the second output terminal Z2 data signal;

The first output terminal Z1 is connected to the input terminal of the tenth inverter INV10, the output terminal of the tenth inverter INV10 is connected to the input terminal of the eleventh inverter INV11, and the first channel of the output terminal of the eleventh inverter INV11 The gate of the twelfth PMOS transistor MP12 and the gate of the twelfth NMOS transistor MN12 are connected, the second path of the output terminal of the eleventh inverter INV11 is connected to the input terminal of the first inverter INV1, and the first inverter The output terminal of INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the gate of the first pre-driving NMOS transistor MN1;

The eighth inverter INV8 includes a twelfth PMOS transistor MP12 and a twelfth NMOS transistor MN12;

The ninth inverter INV9 includes a thirteenth PMOS transistor MP13 and a thirteenth NMOS transistor MN13;

The source and substrate of the twelfth PMOS transistor MP12 are connected to the first power supply VDD1, the drain of the twelfth PMOS transistor MP12 and the drain of the twelfth NMOS transistor MN12 are connected to the gate of the thirteenth PMOS transistor MP13 and the tenth The gate of the third NMOS transistor MN13, the source of the twelfth NMOS transistor MN12 and the source of the thirteenth NMOS transistor MN13 input the MID signal; the source and substrate of the thirteenth PMOS transistor MP13 are connected to the first power supply VDD1, and the source of the thirteenth NMOS transistor MN13 is connected to the first power supply VDD1. The drain of the thirteenth PMOS transistor MP13 and the drain of the thirteenth NMOS transistor MN13 are connected to the gate of the eleventh NMOS transistor MN11; the drain of the eleventh NMOS transistor MN11 is first connected to the gate of the tenth PMOS transistor MP10 , the drain of the eleventh NMOS transistor MN11 is connected to the drain of the eleventh PMOS transistor MP11 in the second way; the source of the eleventh NMOS transistor MN11 and the source of the tenth NMOS transistor MN10 input the MID signal; the tenth PMOS transistor The source and substrate of MP10 and the source and substrate of the eleventh PMOS transistor MP11 are connected to the second power supply VDD2; the gate of the eleventh PMOS transistor MP11, the drain of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 The drain is simultaneously connected to the gate of the first pre-drive PMOS transistor MP1;

The substrate and source of the first pre-drive PMOS transistor MP1 are connected to the second power supply VDD2, and the first path between the drain of the first pre-drive PMOS transistor MP1 and the drain of the first pre-drive NMOS transistor MN1 is connected to the fourth pre-drive PMOS The gate of the transistor MP4, the drain of the first pre-drive PMOS transistor MP1 and the drain of the first pre-drive NMOS transistor MN1 are connected to the input terminal of the third inverter INV3, and the first pre-drive NMOS transistor MN1 The output of the drain pre-drives the pull-up signal LP; the first output terminal of the third inverter INV3 is connected to the gate of the third NMOS transistor MN3, and the second output terminal of the third inverter INV3 is connected to the fourth inverter The input end of the inverter INV4, the output end of the fourth inverter INV4 is connected to the gate of the second NMOS transistor MN2, the source level of the second NMOS transistor MN2 is grounded, and the source level of the third NMOS transistor MN3 inputs the MID signal; the second NMOS transistor MN2 The drain of the transistor MN2 and the drain of the third NMOS transistor MN3 are connected to the source of the first pre-driving NMOS transistor MN1;

The source and substrate of the second PMOS transistor MP2 and the substrate of the third driving PMOS transistor MP3 are connected to the second power supply VDD2, the drain of the second PMOS transistor MP2 is connected to the source of the third driving PMOS transistor MP3, and the third driving PMOS transistor MP3 The gate of the transistor MP3 inputs the MID signal, and the drain of the third driving PMOS transistor MP3 and the drain of the fourth driving NMOS transistor MN4 are used as the output of the output driving circuit that can realize output high level conversion; the fourth driving NMOS transistor MN4 The gate of the fourth driving NMOS transistor MN4 is connected to the drain of the seventh driving NMOS transistor MN7, the source of the seventh driving NMOS transistor MN7 is grounded; the gate of the seventh driving NMOS transistor MN7 is connected to The output terminal of the seventh inverter INV7, the input terminal of the seventh inverter INV7 is connected to the output terminal of the sixth inverter INV6, the input terminal of the sixth inverter INV6 is connected to the output terminal of the fifth inverter INV5, The input end of the fifth inverter INV5 is connected to the output end of the thirteenth inverter INV13, the input end of the thirteenth inverter INV13 is connected to the output end of the twelfth inverter INV12, and the twelfth inverter INV12 The input terminal is connected to the second output terminal Z2 of the output control circuit T;

The source and substrate of the fourth PMOS transistor MP4 and the substrate of the third PMOS transistor MP3 are connected to the second power supply VDD2, the gate of the fourth PMOS transistor MP4 and the drain of the fourth PMOS transistor MP4 are connected to the fifth PMOS transistor MP5 The drain, the gate of the fifth PMOS transistor MP5 is grounded, the drain of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6, and the gate and drain of the sixth PMOS transistor MP6 are connected to the gate of the eighth NMOS transistor MN8 electrode and drain, the gate of the seventh NMOS transistor MN7, the gate of the sixth NMOS transistor MN6, the source of the eighth NMOS transistor MN8 is connected to the drain and the substrate of the seventh PMOS transistor MP7, the seventh PMOS transistor MP7 The gate and the source are grounded; the source of the sixth NMOS transistor MN6 is connected to the drain of the sixth NMOS transistor MN6; the source of the seventh NMOS transistor MN7, the gate of the ninth NMOS transistor MN9, and the eighth PMOS transistor MP8 The drain of the eighth PMOS transistor MP8 is connected to output the MID signal; the gate and source of the eighth PMOS transistor MP8 are connected to the ground; the substrate of the eighth PMOS transistor MP8 is connected to the drain of the ninth PMOS transistor MP9, and the gate of the ninth PMOS transistor MP9 is grounded. The substrate and source of the ninth PMOS transistor MP9 are connected to the first power supply VDD1. The circuits not illustrated are powered by the power supply VDD1.

Compared with the prior art, the beneficial effects of the present invention are:

(1) The present invention proposes an output driving circuit that can realize output high-level switching. By using the variable driving signal MID, all required high-voltage devices are replaced with ordinary working devices. Compared with the high-voltage device technology in the background art, the process compatibility is improved, the implementation difficulty is small, the problem of large layout area of the high-voltage device is eliminated, and the circuit power consumption cost is reduced.

(2) The present invention proposes an output drive circuit that can realize output high-level conversion. The variable drive signal MID is used to make the output end not only effectively boost, but also to realize the function of equal level shift, which improves the output Port output level flexibility.

(3) The present invention proposes an output drive circuit that can realize output high-level conversion, uses the pre-drive P-tube feedback module, quickly pulls down the drive signal, and accelerates the output drive.

(4) The present invention proposes an output drive circuit that can realize output high-level conversion, increases the output isolation MN4 and MP3, effectively isolates the noise interference introduced by the power supply, and improves the withstand voltage characteristics and reliability of the output interface.

Description of drawings

Fig. 1 is a schematic block diagram of a typical CMOS output drive circuit of the present invention;

Fig. 2 is the functional block diagram of the output drive circuit with level shift of the present invention;

Fig. 3 is the circuit diagram that the present invention is used to realize the conversion of low input level to high output level without high voltage device;

(a) of Fig. 4 is the circuit principle diagram for realizing the first output buffer BUF1 of the present invention, (b) is used for realizing the circuit principle diagram of the second output buffer BUF2;

(a) of Fig. 5 is the circuit schematic diagram that the present invention is used to realize the pull-up P tube pre-output level shift buffer circuit SHIFT, (b) the inverter INV8 schematic diagram of the auxiliary level shift circuit, (c) the auxiliary circuit Schematic diagram of the inverter INV9 of the translation bit circuit.

FIG. 6 is a schematic diagram of a bias circuit for generating a variable driving signal MID according to the present invention.

Detailed ways

The present invention will be explained below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 3, the present invention proposes an output drive circuit that can realize output high-level conversion, including a first power supply VDD1, a second power supply VDD2, an output control circuit T, a pull-up P tube pre-driver circuit, a pull-up Output drive PMOS tube MP2, pull-down output drive tube MN5, output isolation circuit, pull-down N tube pre-drive circuit, variable drive signal MID generation circuit, pull-down pre-drive circuit.

As shown in Figure 3, the output control circuit T is a three-state control circuit, including a data signal input terminal A, an enable signal input terminal S, a first output terminal Z1, and a second output terminal Z2;

As shown in Figure 3, the pull-up P transistor pre-drive circuit includes a first output buffer BUF1, a level shift buffer circuit SHIFT, a first inverter INV1, a second inverter INV2, a first pre-drive PMOS transistor MP1, The first pre-driver NMOS tube MN1, the output P tube feedback circuit;

As shown in FIG. 4(a), the first output buffer BUF1 includes a tenth inverter INV10 and an eleventh inverter INV11;

As shown in FIG. 5, the level shift buffer circuit SHIFT includes a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, an eighth inverter INV8, a ninth inverter Inverter INV9; the eighth inverter INV8 includes a twelfth PMOS transistor MP12 and a twelfth NMOS transistor MN12; the ninth inverter INV9 includes a thirteenth PMOS transistor MP13 and a thirteenth NMOS transistor MN13;

As shown in FIG. 3 , the output P-tube feedback circuit includes a second pre-drive NMOS transistor MN2, a third pre-drive NMOS transistor MN3, a third inverter INV3, and a fourth inverter INV4;

As shown in Figure 6, the variable drive signal MID generation circuit includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, The sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9;

As shown in FIG. 3, the pull-down pre-driver circuit includes a second output buffer BUF2, a fifth inverter INV5, a sixth inverter INV6, and a seventh inverter INV7;

As shown in FIG. 4(b), the second output buffer BUF2 includes a twelfth inverter INV12 and a thirteenth inverter INV13;

As shown in FIG. 3, the output isolation circuit includes a third driving PMOS transistor MP3 and a fourth driving NMOS transistor MN4;

As shown in Figure 3, the input terminal A of the output control circuit T receives the data signal D, the enable signal input terminal S receives the enable signal OEN, and the enable signal OEN controls the output control circuit T, from the first output terminal Z1, the second The output terminal Z2 outputs two data signals.

As shown in Figure 4, the first output terminal Z1 is connected to the input terminal of the tenth inverter INV10, the output terminal of the tenth inverter INV10 is connected to the input terminal of the eleventh inverter INV11, and the eleventh inverter INV11 The first path of the output end of the inverter is connected to the gate of the twelfth PMOS transistor MP12 and the gate of the twelfth NMOS transistor MN12, and the second path of the output end of the eleventh inverter INV11 is connected to the input end of the first inverter INV1 , the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the gate of the first pre-driving NMOS transistor MN1;

As shown in Figure 5, the source and substrate of the twelfth PMOS transistor MP12 are connected to the first power supply VDD1, the drain of the twelfth PMOS transistor MP12 and the drain of the twelfth NMOS transistor MN12 are connected to the thirteenth PMOS transistor MP13 and the gate of the thirteenth NMOS transistor MN13, the source of the twelfth NMOS transistor MN12 and the source of the thirteenth NMOS transistor MN13 input the MID signal; the source of the thirteenth PMOS transistor MP13 is connected to the substrate The first power supply VDD1, the drain of the thirteenth PMOS transistor MP13 and the drain of the thirteenth NMOS transistor MN13 are connected to the gate of the eleventh NMOS transistor MN11; the drain of the eleventh NMOS transistor MN11 is first connected to the gate of the tenth The gate of the PMOS transistor MP10 and the drain of the eleventh NMOS transistor MN11 are connected to the drain of the eleventh PMOS transistor MP11 in the second way; the source of the eleventh NMOS transistor MN11 and the source of the tenth NMOS transistor MN10 are input to the MID Signal; the source and substrate of the tenth PMOS transistor MP10 and the source and substrate of the eleventh PMOS transistor MP11 are connected to the second power supply VDD2; the gate of the eleventh PMOS transistor MP11 and the drain of the tenth PMOS transistor MP10 and the drain of the tenth NMOS transistor MN10 are simultaneously connected to the gate of the first pre-drive PMOS transistor MP1;

As shown in FIG. 3 , the substrate and source of the first pre-driving PMOS transistor MP1 are connected to the second power supply VDD2, and the first path between the drain of the first pre-driving PMOS transistor MP1 and the drain of the first pre-driving NMOS transistor MN1 Connect the gate of the fourth pre-driving PMOS transistor MP4, the second path connecting the drain of the first pre-driving PMOS transistor MP1 and the drain of the first pre-driving NMOS transistor MN1 to the input terminal of the third inverter INV3, the first The output of pre-driving the drain of the NMOS transistor MN1 pre-drives the pull-up signal LP; the first output terminal of the third inverter INV3 is connected to the gate of the third NMOS transistor MN3, and the second output terminal of the third inverter INV3 The road is connected to the input end of the fourth inverter INV4, the output end of the fourth inverter INV4 is connected to the gate of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is grounded, and the source of the third NMOS transistor MN3 is input MID signal; the drain of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3 are connected to the source of the first pre-drive NMOS transistor MN1;

As shown in Figure 3, the source and substrate of the second PMOS transistor MP2 and the substrate of the third driving PMOS transistor MP3 are connected to the second power supply VDD2, and the drain of the second PMOS transistor MP2 is connected to the source of the third driving PMOS transistor MP3 stage, the gate of the third driving PMOS transistor MP3 inputs the MID signal, the drain of the third driving PMOS transistor MP3 and the drain of the fourth driving NMOS transistor MN4 are used as the output of the output driving circuit that can realize output high level conversion; The gate of the fourth driving NMOS transistor MN4 is connected to the first power supply VDD1, the source of the fourth driving NMOS transistor MN4 is connected to the drain of the seventh driving NMOS transistor MN7, and the source of the seventh driving NMOS transistor MN7 is grounded; the seventh driving NMOS transistor MN7 The gate of the tube MN7 is connected to the output terminal of the seventh inverter INV7, the input terminal of the seventh inverter INV7 is connected to the output terminal of the sixth inverter INV6, and the input terminal of the sixth inverter INV6 is connected to the fifth inverter The output end of the inverter INV5, the input end of the fifth inverter INV5 is connected to the output end of the thirteenth inverter INV13, the input end of the thirteenth inverter INV13 is connected to the output end of the twelfth inverter INV12, and the input end of the thirteenth inverter INV13 is connected. The input terminal of the twelve inverter INV12 is connected to the second output terminal Z2 of the output control circuit T;

As shown in FIG. 3, the source and substrate of the fourth PMOS transistor MP4 and the substrate of the third PMOS transistor MP3 are connected to the second power supply VDD2, and the gate of the fourth PMOS transistor MP4 is connected to the drain of the fourth PMOS transistor MP4. The drain of the fifth PMOS transistor MP5, the gate of the fifth PMOS transistor MP5 are grounded, the drain of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6, and the gate and drain of the sixth PMOS transistor MP6 are connected to the first The gate and drain of the eighth NMOS transistor MN8, the gate of the seventh NMOS transistor MN7, the gate of the sixth NMOS transistor MN6, the source of the eighth NMOS transistor MN8 is connected to the drain and the substrate of the seventh PMOS transistor MP7, The gate and source of the seventh PMOS transistor MP7 are grounded; the source of the sixth NMOS transistor MN6 is connected to the drain of the sixth NMOS transistor MN6; the source of the seventh NMOS transistor MN7 and the gate of the ninth NMOS transistor MN9 1. The drain of the eighth PMOS transistor MP8 is connected to output the MID signal; the gate and source of the eighth PMOS transistor MP8 are grounded; the substrate of the eighth PMOS transistor MP8 is connected to the drain of the ninth PMOS transistor MP9, and the ninth PMOS transistor MP8 The gate of MP9 is grounded, and the substrate and source of the ninth PMOS transistor MP9 are connected to the first power supply VDD1.

In the example, VDD1 is 2.5V, VDD2 is optional 3.3V or 2.5V, and the circuit has two working states: high-impedance state and normal working state.

(1) The output circuit is in a high-impedance working state:

When the output control terminal OEN is a high-level voltage of 2.5V, the output signals Z1 and Z2 of the output control circuit T output a low-level voltage of 0V and a high-level voltage of 2.5V respectively, and Z1 drives the level shift buffer circuit SHIFT through BUF1 to output The low-level voltage MID drives the PMOS transistor MP1 to turn on, and the pull-up drive signal LP is pulled to an optional high level of 3.3V or 2.5V, so that the pull-up drive transistor PMOS transistor MP2 is turned off. At the same time, Z2 obtains the LN output low-level voltage 0V through the inverter chain composed of BUF2 and INV5, INV6, and INV7, and the pull-down drive tube MN5 is turned on and off. The output of the circuit behaves as a high-impedance state.

(2) The output circuit is in normal working condition:

When the output control terminal OEN is a low-level voltage of 0V, the output control circuit T normally outputs signals, and Z1 and Z2 respond to the input signal D.

(1) When the signal D inputs a low-level voltage of 0V, Z1 drives the level-shift buffer circuit SHIFT through BUF1, and clamps and outputs a low-level voltage 307, which is MID. The low-voltage MID signal drives the PMOS transistor MP1 to turn on, the pull-up drive signal LP is pulled to a high level of 3.3V/2.5V, and the PMOS transistor MP2 is turned off. At this time, the inverter chain composed of inverters INV1 and INV2 outputs a low-level voltage of 0V, and the NMOS transistor MN1 is turned off. Moreover, the inverters INV3 and INV4 driven by the pull-up drive signal LP output 302 a high-level voltage of 2.5V, making the NMOS transistor MN2 turn on, and the parasitic capacitor charge at the node 303 is quickly discharged to a low-level voltage of 0V through MN2. At the same time, the low-level voltage Z2 passes through the inverter chain composed of BUF2 and inverters INV5, INV6, and INV7 to obtain the pull-down drive signal LN. At this time, LN is a high-level voltage of 2.5V, and the pull-down drive NMOS transistor MN5 is turned on. The output PAD is pulled to a low level voltage of 0V.

(2) When the signal D inputs a high-level voltage of 2.5V, Z1 and Z2 output a high-level voltage of 2.5V in response. Z2 obtains a pull-down drive signal LN with a low-level voltage of 0V through the inverter chain composed of BUF2 and INV5, INV6, and INV7, and the pull-down drive tube MN5 is turned off. At the same time, Z1 drives the level shift circuit SHIFT after passing through BUF1 to obtain an output high-level voltage of 3.3V/2.5V, so that the pre-drive PMOS transistor MP1 is turned off. At this time, the inverter chains INV1 and INV2 output a high-level voltage of 2.5V, so that the NMOS transistor MN1 is turned on. At this time, the NMOS transistor MN2 has not been turned off in time, and the parasitic charges on the nodes 303 and 304 and the NMOS transistor MN2 Discharge through the NMOS tube MN2. As the parasitic charge gradually decreases, the pull-up drive signal LP begins to drop until it is lower than the high threshold voltage of the inverter INV3, the inverter INV3 flips, so that the node 305 outputs a high-level voltage of 2.5V, and then the NMOS transistor MN3 conduction. At the same time, INV4 outputs a low-level voltage to turn off the NMOS transistor MN2. The parasitic charge on the node 304 is further accelerated to be discharged by the NMOS transistor MN1 and the NMOS transistor MN3 until the pull-up driving signal LP is pulled down to the level voltage MID, which makes the driving transistor MP2 turn on. The PAD outputs a high-level voltage of 3.3V/2.5V. So far, the PAD has completed the level boost conversion from 2.5V to 3.3/2.5V.

The following points need to be explained:

(1) Description of the level shift circuit SHIFT circuit. The level shift circuit SHIFT is shown in Fig. 5(a), which is used as an output buffer level shift circuit in the present invention. When A inputs 0V, the inverters INV8 and INV9 respectively output a signal 501 with a level of 2.5V and a variable driving low level MID signal. The circuit principles of INV8 and INV9 are shown in Figure 5(b) and Figure 5(c). The inverter composed of PMOS transistor MP4 and NMOS transistor MN5 has a high output level of 2.5V and a low output level of MID. At this time, the NMOS transistor MN11 is turned off, the NMOS transistor MN10 is turned on, and the PMOS transistor MP11 is turned on, and the cross latch makes the output OUT clamped to the low level voltage MID. When A input is a high-level voltage of 2.5V, the output signal 501 of the inverter INV8 is a low-level voltage MID, MN10 is turned off, INV9 outputs a high-level voltage of 2.5V, and MN11 is turned on, so that the node 502 is pulled down to low Level voltage MID, at the same time the PMOS transistor MP10 is turned on, and the OUT cross latch outputs a high level voltage of 3.3V. The level shift buffer SHIFT uses the MID signal to obtain an optional high-level 3.3V or 2.5V output without the need for high-voltage devices.

(2) Variable drive signal MID signal. The MID signal is designed as a low-medium level voltage value, as shown in Figure 6, the MID signal is connected to the gate terminal of the PMOS driving transistor MP2 as the pull-up P transistor driving signal LP for the output PAD. As shown in FIG. 6( a ), the voltage is usually designed to be 0V, when the difference between it and the power supply is Δ1=0V-2.5V. That is to say, when the VGS of the output transistor=-2.5V, the requirement of fast output driving is satisfied. To realize the boost function, the power supply voltage must be raised from 2.5V to 3.3V, that is to say, the voltage difference between the gate and the source rises to Δ ₂ =0V-3.3V. According to the above design requirements, under the 0.25um process condition, in order to ensure that the transistor will not break down due to overvoltage, MP2 must use high-voltage devices, which will increase the difficulty of process design and is not conducive to the compatibility of CMOS process. In the present invention, still adopt the transistor MP2 of common process, improve the voltage of MID, make the voltage difference VGS=Δ ₃ =MID-3.3V of MP2 tube gate source two ends be equal to-2.5V approximately, to guarantee not adopting the situation of high-voltage device Under this condition, the MP2 tube can still work normally and effectively. Usually, the absolute value of the gate-source voltage difference VGS=Δ ₄ =MID-2.5V is greater than the absolute value |V _th,P | of the threshold of the PMOS transistor, which will not affect the normal operation of the output drive transistor. From this, it can be deduced that the voltage range of the MID is greater than 0.8V and less than 2.5-|V _th,p |. The present invention provides a realization circuit of MID signal, as shown in Fig. 6(b). The power supply voltage is connected to 3.3V/2.5V, and the PMOS tubes MP4, MP6, and MP7 are connected by diodes as resistors, and the ratio of W/L (gate width to gate length) is 1. The PMOS tube MP5 is a normally-through tube, and the NMOS tube MN8 is also connected by a diode, so the W/L is not too large during design. The specific voltage value is about VGS, 8 plus the overdrive voltage of a PMOS transistor MP7. This voltage provides a bias for the subsequent NMOS transistor MN7. The PMOS transistor MP9 alone supplies power for the substrate bias of the PMOS transistor MP8, and the PMOS transistor MP8 is designed as a small resistor connected by a diode. Nodes 601 and 602 are respectively connected to NMOS transistors as MN6 and MN9 of MOS capacitors, which have the effect of filtering and suppress the signal noise of the main circuit kicked back by signal fluctuations. This design effectively guarantees the symmetry of the branches on both sides of the node 601 and the node 602 and the accuracy of the signal. According to the selective access of VDD2 to 3.3V or 2.5V, the circuit can output a low-level MID signal of about 0.8V or 0.5V to achieve the desired effect.

(3) Feedback loop. In the traditional pull-up pre-driver circuit, there is no feedback loop, as shown in Figure 1, only the single transistor MN01 is used for discharge, so the pull-up drive signal LP cannot be discharged quickly and effectively. In the present invention, the added feedback module can accelerate the discharge of the LP signal. To further illustrate with an example, since the variable driving voltage MID is adopted, when VDD2 is connected to 3.3V voltage, the gate-source voltage difference VGS=Δ ₃ =0.8-3.3V≈-2.5V on the PMOS transistor MP2, the pull-up output transistor MP2 gate The pole input range increases, and at this time, it can quickly drive the post-stage load without a feedback module. But when VDD2 is connected to 2.5V voltage, the absolute value of the gate-source voltage difference on PMOS transistor MP4 |VGS|=|Δ ₃ |=|0.5-2.5V|<2.5V. At this time, the feedback circuit is used to quickly discharge to a low-level voltage to effectively drive the subsequent load, and at the same time accelerate the driving of the subsequent load, so that the rising delay time is reduced. Note that MN2 is designed as an inverting tube with a width smaller than its length, which acts as a resistor.

(4) Description of the number of inverters. As shown in the figure, the NMOS transistor MN1 on the Z1 branch can be regarded as a first-stage inverter. Therefore, a total of five stages of reverse driving have been performed from the output terminal of ZI to the gate of the drive transistor MP2. During design, the number of inverters in the two branches of the buffer BUF1 should be consistent. The inverter chain composed of the buffer BUF2 and the inverters INV5, INV6, and INV7 on the Z2 branch also undergoes five stages of reverse driving. In the design, the delay of the Z1 branch and the Z2 branch can be kept consistent, so that the rising edge delay and falling edge delay of the output driving signal are basically equal.

The content that is not described in detail in the description of the present invention belongs to the well-known technology of those skilled in the art. Although the embodiments of the present invention have been described with reference to the accompanying drawings, various variations or modifications may be made by those skilled in the art within the scope of the appended claims.

Claims (6)

1. An output drive circuit that can realize output high-level conversion, characterized in that: it includes a first power supply VDD1, a second power supply VDD2, an output control circuit T, a pull-up P tube pre-driver circuit, and a pull-up output drive PMOS tube MP2, pull-down output drive tube MN5, output isolation circuit, pull-down N tube pre-drive circuit, variable drive signal MID generation circuit, pull-down pre-drive circuit; The output control circuit T is a three-state control circuit, including a data signal input terminal A, an enable signal input terminal S, a first output terminal Z1, and a second output terminal Z2; The pull-up P tube pre-driver circuit includes a first output buffer BUF1, a level shift buffer circuit SHIFT, a first inverter INV1, a second inverter INV2, a first pre-drive PMOS transistor MP1, a first pre-drive NMOS transistor MN1, output P tube feedback circuit; The first output buffer BUF1 includes a tenth inverter INV10 and an eleventh inverter INV11; The level shift buffer circuit SHIFT includes a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, an eighth inverter INV8, and a ninth inverter INV9; The output P-tube feedback circuit includes a second pre-drive NMOS transistor MN2, a third pre-drive NMOS transistor MN3, a third inverter INV3, and a fourth inverter INV4; The variable driving signal MID generating circuit includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a sixth NMOS transistor MN6, The seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9; The pull-down pre-drive circuit includes a second output buffer BUF2, a fifth inverter INV5, a sixth inverter INV6, and a seventh inverter INV7; the second output buffer BUF2 includes a twelfth inverter INV12, a tenth inverter Three inverters INV13; The output isolation circuit includes a third driving PMOS transistor MP3 and a fourth driving NMOS transistor MN4; The input terminal A of the output control circuit T receives the data signal D, the enable signal input terminal S receives the enable signal OEN, the enable signal OEN controls the output control circuit T, and outputs two channels from the first output terminal Z1 and the second output terminal Z2 data signal; The first output terminal Z1 is connected to the input terminal of the tenth inverter INV10, the output terminal of the tenth inverter INV10 is connected to the input terminal of the eleventh inverter INV11, and the first channel of the output terminal of the eleventh inverter INV11 The gate of the twelfth PMOS transistor MP12 and the gate of the twelfth NMOS transistor MN12 are connected, the second path of the output terminal of the eleventh inverter INV11 is connected to the input terminal of the first inverter INV1, and the first inverter The output terminal of INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the gate of the first pre-driving NMOS transistor MN1; The eighth inverter INV8 includes a twelfth PMOS transistor MP12 and a twelfth NMOS transistor MN12; The ninth inverter INV9 includes a thirteenth PMOS transistor MP13 and a thirteenth NMOS transistor MN13; The source and substrate of the twelfth PMOS transistor MP12 are connected to the first power supply VDD1, the drain of the twelfth PMOS transistor MP12 and the drain of the twelfth NMOS transistor MN12 are connected to the gate of the thirteenth PMOS transistor MP13 and the tenth The gate of the third NMOS transistor MN13, the source of the twelfth NMOS transistor MN12 and the source of the thirteenth NMOS transistor MN13 input the MID signal; the source and substrate of the thirteenth PMOS transistor MP13 are connected to the first power supply VDD1, and the source of the thirteenth NMOS transistor MN13 is connected to the first power supply VDD1. The drain of the thirteenth PMOS transistor MP13 and the drain of the thirteenth NMOS transistor MN13 are connected to the gate of the eleventh NMOS transistor MN11; the drain of the eleventh NMOS transistor MN11 is first connected to the gate of the tenth PMOS transistor MP10 , the drain of the eleventh NMOS transistor MN11 is connected to the drain of the eleventh PMOS transistor MP11 in the second way; the source of the eleventh NMOS transistor MN11 and the source of the tenth NMOS transistor MN10 input the MID signal; the tenth PMOS transistor The source and substrate of MP10 and the source and substrate of the eleventh PMOS transistor MP11 are connected to the second power supply VDD2; the gate of the eleventh PMOS transistor MP11, the drain of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 The drain is simultaneously connected to the gate of the first pre-drive PMOS transistor MP1; The substrate and source of the first pre-drive PMOS transistor MP1 are connected to the second power supply VDD2, and the first path between the drain of the first pre-drive PMOS transistor MP1 and the drain of the first pre-drive NMOS transistor MN1 is connected to the fourth pre-drive PMOS The gate of the transistor MP4, the drain of the first pre-drive PMOS transistor MP1 and the drain of the first pre-drive NMOS transistor MN1 are connected to the input terminal of the third inverter INV3, and the first pre-drive NMOS transistor MN1 The output of the drain pre-drives the pull-up signal LP; the first output terminal of the third inverter INV3 is connected to the gate of the third NMOS transistor MN3, and the second output terminal of the third inverter INV3 is connected to the fourth inverter The input end of the inverter INV4, the output end of the fourth inverter INV4 is connected to the gate of the second NMOS transistor MN2, the source level of the second NMOS transistor MN2 is grounded, and the source level of the third NMOS transistor MN3 inputs the MID signal; the second NMOS transistor MN2 The drain of the transistor MN2 and the drain of the third NMOS transistor MN3 are connected to the source of the first pre-driving NMOS transistor MN1; The source and substrate of the second PMOS transistor MP2 and the substrate of the third driving PMOS transistor MP3 are connected to the second power supply VDD2, the drain of the second PMOS transistor MP2 is connected to the source of the third driving PMOS transistor MP3, and the third driving PMOS transistor MP3 The gate of the transistor MP3 inputs the MID signal, and the drain of the third driving PMOS transistor MP3 and the drain of the fourth driving NMOS transistor MN4 are used as the output of the output driving circuit that can realize output high level conversion; the fourth driving NMOS transistor MN4 The gate of the fourth driving NMOS transistor MN4 is connected to the drain of the seventh driving NMOS transistor MN7, the source of the seventh driving NMOS transistor MN7 is grounded; the gate of the seventh driving NMOS transistor MN7 is connected to The output terminal of the seventh inverter INV7, the input terminal of the seventh inverter INV7 is connected to the output terminal of the sixth inverter INV6, the input terminal of the sixth inverter INV6 is connected to the output terminal of the fifth inverter INV5, The input end of the fifth inverter INV5 is connected to the output end of the thirteenth inverter INV13, the input end of the thirteenth inverter INV13 is connected to the output end of the twelfth inverter INV12, and the twelfth inverter INV12 The input terminal is connected to the second output terminal Z2 of the output control circuit T; The source and substrate of the fourth PMOS transistor MP4 and the substrate of the third PMOS transistor MP3 are connected to the second power supply VDD2, the gate of the fourth PMOS transistor MP4 and the drain of the fourth PMOS transistor MP4 are connected to the fifth PMOS transistor MP5 The drain, the gate of the fifth PMOS transistor MP5 is grounded, the drain of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6, and the gate and drain of the sixth PMOS transistor MP6 are connected to the gate of the eighth NMOS transistor MN8 electrode and drain, the gate of the seventh NMOS transistor MN7, the gate of the sixth NMOS transistor MN6, the source of the eighth NMOS transistor MN8 is connected to the drain and the substrate of the seventh PMOS transistor MP7, the seventh PMOS transistor MP7 The gate and the source are grounded; the source of the sixth NMOS transistor MN6 is connected to the drain of the sixth NMOS transistor MN6; the source of the seventh NMOS transistor MN7, the gate of the ninth NMOS transistor MN9, and the eighth PMOS transistor MP8 The drain of the eighth PMOS transistor MP8 is connected to output the MID signal; the gate and source of the eighth PMOS transistor MP8 are connected to the ground; the substrate of the eighth PMOS transistor MP8 is connected to the drain of the ninth PMOS transistor MP9, and the gate of the ninth PMOS transistor MP9 is grounded. The substrate and source of the ninth PMOS transistor MP9 are connected to the first power supply VDD1. 2 . The output driving circuit capable of outputting high-level conversion according to claim 1 , wherein the PMOS transistor MP1 and the PMOS transistor MP4 are common process transistors. 3 . 3 . The output driving circuit capable of outputting high-level switching according to claim 1 , wherein the level of the second power supply VDD2 is equal to or higher than the level of the first power supply VDD1 . 4. A kind of output driving circuit capable of outputting high-level conversion according to claim 1, characterized in that: the range of the level of the MID signal is greater than VDD2-VDD1, and less than VDD1-|V _{th, p2} |, where V _{th, p2} is the threshold voltage of the pull-up drive PMOS transistor MP2. 5. An output drive circuit capable of outputting high-level conversion according to claim 1, characterized in that: the third inverter INV3 and the fourth inverter INV4, the second NMOS transistor MN2, the second inverter The feedback circuit composed of three NMOS transistors MN3 can form a positive feedback structure, quickly pull down the drive signal, and accelerate the output drive. 6. The output driving circuit capable of outputting high-level conversion according to claim 1, characterized in that: the third PMOS transistor MP3 and the fourth NMOS transistor MN4 effectively isolate the noise interference introduced by the power ground, The withstand voltage characteristics and reliability of the output interface of the output driving circuit capable of outputting high-level conversion are improved.