CN104638887B - Output driving circuit capable of realizing output high level conversion - Google Patents
Output driving circuit capable of realizing output high level conversion Download PDFInfo
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- CN104638887B CN104638887B CN201510050634.2A CN201510050634A CN104638887B CN 104638887 B CN104638887 B CN 104638887B CN 201510050634 A CN201510050634 A CN 201510050634A CN 104638887 B CN104638887 B CN 104638887B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
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Abstract
The invention provides an output driving circuit capable of realizing output high level conversion. The output driving circuit is characterized by comprising a first power supply VDD1, a second power supply VDD2, an output control circuit T, an upwards pulling P tube pre-driving circuit, an upwards pulling output driving PMOS (P-channel metal oxide semiconductor) tube MP2, a downwards pulling output driving tube MN5, an output isolation circuit, a downwards pulling N tube pre-driving circuit, a variable driving signal MID and a downwards pulling pre-driving circuit. The upwards pulling pre-driving circuit provides the variable driving signal MID for the driving tube MP2 through the pulling of a level displacement buffer circuit SHIFT by using the feedback circuit for acceleration, so that the whole circuit realizes the output high level voltage conversion under the high-voltage-device-free condition. Compared with other circuits, the technology has the characteristics that an additional high-voltage device output tube is not needed, different selections of low level input and high level output can be realized, the load is fast driven, the power supply noise can be isolated, the area is smaller, and the power consumption is lower.
Description
Technical field
The present invention relates to one kind does not utilize high tension apparatus, also can achieve that low level voltage turns the output driving of high level voltage
Circuit, more particularly, to level translator and integrated circuit I/O design field.
Background technology
With the variation of integrated circuit development, derive the integrated circuit working under various level voltages.Correctly
Signal level can ensure that system reliably works, and prevents sensitive circuit undermined because of too high or too low voltage conditions.
The input of not up to required level can reduce the surplus of signal noise, and excessive input, the loss of excessive power can be caused.For
Effectively transmit signal, integrated circuit is generally by the use of input/output (I/O) interface as the bridge of conversion between low pressure and high pressure
Beam so that while low-voltage signal completely transmits, from the interference of high-voltage signal.
Generally, when designing output driving circuit, the main ability considering drives heavy load, ternary output and patrol
Collect the compatible problem of device interface level.Typical CMOS output driving circuit as shown in figure 1, including predrive circuit module,
Drive circuit and output protection circuit.Wherein predrive circuit is by the predrive electricity of tri-state control circuit T, pulling drive signal LP
The predrive circuit composition of road and drop-down drive signal LN；Tri-state control circuit T its input A receives internal output signal D, S
End is enabled by output control terminal OEN signal and controls；Outfan Z1 connects pull-up P pipe predrive circuit, and outfan Z2 connects drop-down N
Pipe predrive circuit；Upper drop-down predrive circuit is generally made up of the chain of inverters gradually amplified；It is reduced to as shown in Figure 1
PMOS MP01 and the phase inverter of NMOS tube MN01 composition, and the phase inverter of PMOS MP03 and NMOS tube MN03 composition；
Pulling drive signal LP, the drain electrode of PMOS MP03 and NMOS tube are drawn in the drain electrode of the drain electrode of PMOS MP01 and NMOS tube MN01
Drop-down drive signal LN is drawn in the drain electrode of MN03；Pulling drive signal LP and drop-down drive signal LN, drives pull-up output respectively
PMOS MP02 and drop-down output NMOS tube MN05, draw outfan PAD between their drain electrode；Output protection circuit is connected to
Outfan PAD.
The operation principle of this circuit is as follows：Enable signal OEN effectively, when data signal D input low level, Z1, Z2 are all defeated
Go out low level.Now, PMOS MP01 and MP03 turn on so that pulling drive signal LP and drop-down drive signal LN signal are
High level, NMOS tube MN05 turns on, and PAD exports low level voltage.When inputting D for high level VDD1, Z1, Z2 all export high electricity
Flat VDD1.Now, NMOS tube MN01 and the conducting of NMOS tube MN03 are so that pulling drive signal LP and drop-down drive signal LN signal
It is low level, pulling drive signal LP output driving pipe PMOS MP02 turns on, PAD output high level voltage VDD1.
Described output driving circuit, is powered by supply voltage VDD1, is only capable of exporting single high level signal.This cannot expire
Foot needs to export long arc, the application requirement changed from low level to high level.
In existing CMOS actuation techniques, the method for level shift (Level shifter) is generally adopted to realize output
The boosting of drive circuit, such as Fig. 2.This circuit, in addition to module necessary to output driving circuit, also includes a level shift
Module 201, power vd D2 and high voltage PMOS device MP21, MP23, MP22.Wherein the level of power vd D2 is higher than power vd D1
Level value.Effectively prevent supply voltage using high tension apparatus when being switched to VDD2 compared with low level VDD1, the puncturing of device.Electricity
Translational shifting module 201 instead of the predrive of the pulling drive signal LP being made up of in Fig. 1 PMOS MP01 and NMOS tube MN01
Circuit.This circuit has input signal D accepting relatively low level VDD1, and the boosting of output high level VDD2 drives work(
Energy.Specifically, when D input low level, Z1, Z2 all export low level.The low level voltage of signal 202 is through phase inverter
203 high level voltage VDD1 are obtained so that NMOS tube MN23 turns on, the grid voltage of PMOS MP21 moves low level electricity to after INV21
Pressure, MP21 turns on, and pulling drive signal LP draws high VDD2, and PMOS MP22 turns off.Meanwhile, as D input high level VDD1,
Z1, Z2 all export VDD1.The conducting of NMOS tube MP21 makes pulling drive signal LP be grounded, and high voltage PMOS pipe MP02 turns on, and PAD is defeated
Go out there is the VDD2 of higher level.
As described above, in CMOS technology of the same race, this level shift output driving circuit has several drawbacks in that：1st, draw high defeated
Go out the PMOS of high level, such as MP21, MP22, MP23 need to use high tension apparatus.In same technological design, using high pressure
Increase circuit design difficulty and technique are realized difficulty by device, while increasing chip area, the power consumption being more than also can be brought to hold
Pin；2nd, because the threshold value of high tension apparatus is higher than commonplace components, if still transmitting the flat VDD1 of small electric, electrical part may be made to end,
Cannot normally export.Therefore, this circuit only possesses the function of being boosted to VDD2 by VDD1, does not possess identical high level voltage transmission
Function it is impossible to need to realize the level flexible conversion of output according to back-end circuit.3rd, output terminates heavy load situation, this electricity relatively
Road does not have the mechanism of quick lift.
Content of the invention
The purpose of the present invention is for overcoming the deficiencies in the prior art, and a kind of achievable of proposition exports the defeated of high level conversion
Go out drive circuit.Using variable drive signal MID so that output driving circuit without high tension apparatus only with commonplace components
Realize boost function.Meanwhile, overcome the shortcoming of the unidirectional boosting of traditional circuit so that outfan not only can effectively boost, also
The function of achievable equal voltage levels transfer, improves the motility of output port output level.Using feedback circuit, solve defeated
Go out to terminate the problem that output drive signal during heavy load draws high deficiency.Increase output isolation MN4 and MP3, be effectively isolated power supply
The noise jamming that ground introduces, improves output interface voltage endurance and reliability.
The present invention solve technical scheme be：A kind of output driving circuit of achievable output high level conversion, including the
One power vd D1, second source VDD2, output control circuit T, pull-up P pipe predrive circuit, pull-up output driving PMOS
MP2, drop-down output driving pipe MN5, output isolation circuit, drop-down N pipe predrive circuit, variable drive signal MID occur circuit,
Drop-down predrive circuit；
Output control circuit T be a tri-state control circuit, include data signal input A, enable signal input part S,
First outfan Z1, the second outfan Z2；
Pull-up P pipe predrive circuit includes the first output buffer BUF1, level shift buffer circuit SHIFT, first anti-
Phase device INV1, the second phase inverter INV2, the first predrive PMOS MP1, the first predrive NMOS tube MN1, output P pipe feedback electricity
Road；
First output buffer BUF1 includes the tenth phase inverter INV10, the 11st phase inverter INV11；
Level shift buffer circuit SHIFT includes the tenth PMOS MP10, the 11st PMOS MP11, the tenth NMOS tube
MN10, the 11st NMOS tube MN11, the 8th phase inverter INV8, the 9th phase inverter INV9；
Output P pipe feedback circuit includes the second predrive NMOS tube MN2, the 3rd predrive NMOS tube MN3, the 3rd phase inverter
INV3, the 4th phase inverter INV4；
Variable drive signal MID occur circuit include the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6,
7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th
NMOS tube MN8, the 9th NMOS tube MN9；
Drop-down predrive circuit include the second output buffer BUF2, the 5th phase inverter INV5, hex inverter INV6,
Seven phase inverter INV7；Second output buffer BUF2 includes the 12nd phase inverter INV12, the 13rd phase inverter INV13；
Output isolation circuit includes the 3rd driving PMOS MP3, the 4th driving NMOS tube MN4；
The input A receiving data signal D of output control circuit T, enables signal input part S and receives enable signal OEN, make
Output control circuit T can be controlled by signal OEN, from the first outfan Z1, the second outfan Z2 output two paths of data signal；
First outfan Z1 connects the input of the tenth phase inverter INV10, the outfan of the tenth phase inverter INV10 connects the
The input of 11 phase inverter INV11, the first via of the outfan of the 11st phase inverter INV11 connects the 12nd PMOS MP12
Grid and the 12nd NMOS tube MN12 grid, the second tunnel of the outfan of the 11st phase inverter INV11 connects first anti-phase
The input of device INV1, the outfan of the first phase inverter INV1 connects the input of the second phase inverter INV2, the second phase inverter
The outfan of INV2 connects the grid of the first predrive NMOS tube MN1；
8th phase inverter INV8 includes the 12nd PMOS MP12, the 12nd NMOS tube MN12；
9th phase inverter INV9 includes the 13rd PMOS MP13, the 13rd NMOS tube MN13；
The source class of the 12nd PMOS MP12 and substrate connect the first power vd D1, the drain electrode of the 12nd PMOS MP12 and
The drain electrode connection grid of the 13rd PMOS MP13 of the 12nd NMOS tube MN12 and the grid of the 13rd NMOS tube MN13, the tenth
The source class input MID signal of the source class of two NMOS tube MN12 and the 13rd NMOS tube MN13；The source class of the 13rd PMOS MP13
Connect the first power vd D1 with substrate, the drain electrode of the 13rd PMOS MP13 and the drain electrode of the 13rd NMOS tube MN13 connect the tenth
The grid of one NMOS tube MN11；The grid of drain electrode first via connection the tenth PMOS MP10 of the 11st NMOS tube MN11, the tenth
Drain electrode second tunnel of one NMOS tube MN11 connects the drain electrode of the 11st PMOS MP11；The source class of the 11st NMOS tube MN11 and
The source class input MID signal of ten NMOS tube MN10；The source class of the tenth PMOS MP10 and substrate and the 11st PMOS MP11
Source class and substrate connect second source VDD2；The grid of the 11st PMOS MP11, the drain electrode of the tenth PMOS MP10 and
The drain electrode of ten NMOS tube MN10 is simultaneously connected with the grid of the first predrive PMOS MP1；
The substrate of the first predrive PMOS MP1 and source class connect second source VDD2, the first predrive PMOS MP1
The first via of the drain electrode of drain electrode and the first predrive NMOS tube MN1 connects the grid of the 4th predrive PMOS MP4, and first drives in advance
Second tunnel of the drain electrode of the drain electrode of dynamic PMOS MP1 and the first predrive NMOS tube MN1 connects the input of the 3rd phase inverter INV3
End, the output predrive pull-up signal LP of the drain electrode of the first predrive NMOS tube MN1；The outfan first of the 3rd phase inverter INV3
Road connects the grid of the 3rd NMOS tube MN3, and outfan second tunnel of the 3rd phase inverter INV3 connects the defeated of the 4th phase inverter INV4
Enter end, the outfan of the 4th phase inverter INV4 connects the grid of the second NMOS tube MN2, the source class of the second NMOS tube MN2 is grounded, the
The source class input MID signal of three NMOS tube MN3；The drain electrode of the drain electrode of the second NMOS tube MN2 and the 3rd NMOS tube MN3 connects first
The source class of predrive NMOS tube MN1；
The substrate of the source class of the second PMOS MP2 and substrate and the 3rd driving PMOS MP3 connects second source VDD2,
The drain electrode of the second PMOS MP2 connects the source class of the 3rd driving PMOS MP3, the grid input MID of the 3rd driving PMOS MP3
Signal, as this, the drain electrode of the drain electrode of the 3rd driving PMOS MP3 and the 4th driving NMOS tube MN4 can achieve that output high level turns
The output of the output driving circuit changing；The grid of the 4th driving NMOS tube MN4 connects the first power vd D1, the 4th driving NMOS tube
The source class of MN4 connects the drain electrode of the 7th driving NMOS tube MN7, the source class ground connection of the 7th driving NMOS tube MN7；7th driving NMOS
The grid of pipe MN7 connects the outfan of the 7th phase inverter INV7, and the input of the 7th phase inverter INV7 connects hex inverter
The outfan of INV6, the input of hex inverter INV6 connects the outfan of the 5th phase inverter INV5, the 5th phase inverter INV5
Input connect the outfan of the 13rd phase inverter INV13, it is anti-phase that the input of the 13rd phase inverter INV13 connects the 12nd
The outfan of device INV12, the input of the 12nd phase inverter INV12 connects the second outfan Z2 of output control circuit T；
The substrate connection second source VDD2 of the source class of the 4th PMOS MP4 and substrate and the 3rd PMOS MP3, the 4th
The drain electrode of the grid of PMOS MP4 and the 4th PMOS MP4 connects the drain electrode of the 5th PMOS MP5, the grid of the 5th PMOS MP5
Pole is grounded, and the drain electrode of the 5th PMOS MP5 connects the source class of the 6th PMOS MP6, and the grid of the 6th PMOS MP6 and drain electrode are even
Meet grid and drain electrode, the grid of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6 of the 8th NMOS tube MN8, the 8th NMOS
The source class of pipe MN8 connects drain electrode and the substrate of the 7th PMOS MP7, the grid of the 7th PMOS MP7 and source class ground connection；6th
The drain electrode of the source class of NMOS tube MN6 and the 6th NMOS tube MN6 connects；The source class of the 7th NMOS tube MN7, the 9th NMOS tube MN9
Grid, the drain electrode of the 8th PMOS MP8 connect and export MID signal；The grid of the 8th PMOS MP8 and source class ground connection；8th
The substrate of PMOS MP8 connects the drain electrode of the 9th PMOS MP9, the grounded-grid of the 9th PMOS MP9, the 9th PMOS MP9
Substrate and source class connect the first power vd D1.Not elsewhere specified circuit is powered by power vd D1.
The having the beneficial effects that compared with prior art of the present invention：
(1) present invention proposes a kind of output driving circuit of achievable output high level conversion.Using variable drive letter
Number MID, required high tension apparatus are all substituted for common device work.Compared with the high tension apparatus technology in background technology, work
Skill compatibility improves, and realizes that difficulty is little, eliminates the big problem of high tension apparatus chip area, reduce circuit power consumption expense.
(2) output driving circuit of a kind of achievable output high level conversion proposed by the present invention, using variable drive letter
Number MID, so that outfan not only can effectively boost, also can achieve the function of equal voltage levels transfer, improves output port defeated
Go out the motility of level.
(3) a kind of output driving circuit of achievable output high level conversion proposed by the present invention, anti-using predrive P pipe
Feedback module, quickly drags down drive signal, accelerates output driving.
(4) a kind of output driving circuit of achievable output high level conversion proposed by the present invention, increases output isolation MN4
And MP3, the noise jamming introducing with being effectively isolated power supply, improve output interface voltage endurance and reliability.
Brief description
Fig. 1 is present invention typical case's CMOS output driving circuit theory diagram；
Fig. 2 is the output driving circuit theory diagram with level shift for the present invention；
The low incoming level that Fig. 3 is used for realization no high tension apparatus for the present invention turns the circuit diagram of height output level；
(a) of Fig. 4 is used for realizing the circuit theory diagrams of the first output buffer BUF1 for the present invention, and (b) is used for realizing the
The circuit theory diagrams of two output buffer BUF2；
(a) of Fig. 5 is used for realizing the circuit theory of pull-up P pipe pre-output level shift buffer circuit SHIFT for the present invention
Figure, (b) assists the phase inverter INV8 schematic diagram of level shift circuit, and (c) assists the phase inverter INV9 principle of level shift circuit
Figure.
Fig. 6 is used for producing the biasing circuit schematic diagram of variable drive signal MID for the present invention.
Specific embodiment
With specific embodiment, the present invention is explained below in conjunction with the accompanying drawings.
As shown in figure 3, the present invention proposes a kind of output driving circuit of achievable output high level conversion, including first
Power vd D1, second source VDD2, output control circuit T, pull-up P pipe predrive circuit, pull-up output driving PMOS MP2,
There is circuit, drop-down in drop-down output driving pipe MN5, output isolation circuit, drop-down N pipe predrive circuit, variable drive signal MID
Predrive circuit.
As shown in figure 3, output control circuit T is a tri-state control circuit, including data signal input A, enable letter
Number input S, the first outfan Z1, the second outfan Z2；
As shown in figure 3, pull-up P pipe predrive circuit includes the first output buffer BUF1, level shift buffer circuit
SHIFT, the first phase inverter INV1, the second phase inverter INV2, the first predrive PMOS MP1, the first predrive NMOS tube MN1,
Output P pipe feedback circuit；
As shown in Fig. 4 (a), the first output buffer BUF1 includes the tenth phase inverter INV10, the 11st phase inverter INV11；
As shown in figure 5, level shift buffer circuit SHIFT include the tenth PMOS MP10, the 11st PMOS MP11,
Ten NMOS tube MN10, the 11st NMOS tube MN11, the 8th phase inverter INV8, the 9th phase inverter INV9；8th phase inverter INV8 bag
Include the 12nd PMOS MP12, the 12nd NMOS tube MN12；9th phase inverter INV9 include the 13rd PMOS MP13, the 13rd
NMOS tube MN13；
As shown in figure 3, output P pipe feedback circuit include the second predrive NMOS tube MN2, the 3rd predrive NMOS tube MN3,
3rd phase inverter INV3, the 4th phase inverter INV4；
As shown in fig. 6, variable drive signal MID occur circuit include the 4th PMOS MP4, the 5th PMOS MP5, the 6th
PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 6th NMOS tube MN6, the 7th NMOS tube
MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9；
As shown in figure 3, drop-down predrive circuit includes the second output buffer BUF2, the 5th phase inverter INV5, the 6th anti-
Phase device INV6, the 7th phase inverter INV7；
As shown in Fig. 4 (b), the second output buffer BUF2 includes the 12nd phase inverter INV12, the 13rd phase inverter
INV13；
As shown in figure 3, output isolation circuit includes the 3rd driving PMOS MP3, the 4th driving NMOS tube MN4；
As shown in figure 3, the input A receiving data signal D of output control circuit T, enable signal input part S and receive enable
Signal OEN, enables signal OEN and controls output control circuit T, from the first outfan Z1, the second outfan Z2 output two paths of data
Signal.
As shown in figure 4, the input of the first outfan Z1 connection the tenth phase inverter INV10, the tenth phase inverter INV10's is defeated
Go out the input that end connects the 11st phase inverter INV11, the first via of the outfan of the 11st phase inverter INV11 connects the 12nd
The grid of PMOS MP12 and the grid of the 12nd NMOS tube MN12, the second tunnel of the outfan of the 11st phase inverter INV11 is even
Connect the input of the first phase inverter INV1, the outfan of the first phase inverter INV1 connects the input of the second phase inverter INV2, the
The outfan of two phase inverter INV2 connects the grid of the first predrive NMOS tube MN1；
As shown in figure 5, the source class of the 12nd PMOS MP12 and substrate connect the first power vd D1, the 12nd PMOS
The drain electrode of the drain electrode of MP12 and the 12nd NMOS tube MN12 connects grid and the 13rd NMOS tube of the 13rd PMOS MP13
The grid of MN13, the source class input MID signal of the source class of the 12nd NMOS tube MN12 and the 13rd NMOS tube MN13；13rd
The source class of PMOS MP13 and substrate connect the first power vd D1, the drain electrode of the 13rd PMOS MP13 and the 13rd NMOS tube
The drain electrode of MN13 connects the grid of the 11st NMOS tube MN11；The drain electrode first via of the 11st NMOS tube MN11 connects the tenth PMOS
The grid of pipe MP10, drain electrode second tunnel of the 11st NMOS tube MN11 connects the drain electrode of the 11st PMOS MP11；11st
The source class input MID signal of the source class of NMOS tube MN11 and the tenth NMOS tube MN10；The source class of the tenth PMOS MP10 and substrate
And the 11st PMOS MP11 source class and substrate connect second source VDD2；The grid of the 11st PMOS MP11, the tenth
The drain electrode of the drain electrode of PMOS MP10 and the tenth NMOS tube MN10 is simultaneously connected with the grid of the first predrive PMOS MP1；
As shown in figure 3, the substrate of the first predrive PMOS MP1 and source class connect second source VDD2, the first predrive
The first via of the drain electrode of the drain electrode of PMOS MP1 and the first predrive NMOS tube MN1 connects the grid of the 4th predrive PMOS MP4
Pole, the second tunnel of the drain electrode of the first predrive PMOS MP1 and the drain electrode of the first predrive NMOS tube MN1 connects the 3rd phase inverter
The input of INV3, the output predrive pull-up signal LP of the drain electrode of the first predrive NMOS tube MN1；3rd phase inverter INV3's
The outfan first via connects the grid of the 3rd NMOS tube MN3, and the outfan second tunnel connection the 4th of the 3rd phase inverter INV3 is anti-phase
The input of device INV4, the outfan of the 4th phase inverter INV4 connects the grid of the second NMOS tube MN2, the second NMOS tube MN2
Source class is grounded, the source class input MID signal of the 3rd NMOS tube MN3；The drain electrode of the second NMOS tube MN2 and the 3rd NMOS tube MN3
Drain electrode connects the source class of the first predrive NMOS tube MN1；
As shown in figure 3, the substrate of the source class of the second PMOS MP2 and substrate and the 3rd driving PMOS MP3 connects the
Two power vd D2, the drain electrode of the second PMOS MP2 connects the source class of the 3rd driving PMOS MP3, the 3rd driving PMOS MP3
Grid inputs MID signal, and the drain electrode of the drain electrode of the 3rd driving PMOS MP3 and the 4th driving NMOS tube MN4 can achieve as this
The output of the output driving circuit of output high level conversion；The grid of the 4th driving NMOS tube MN4 connects the first power vd D1, the
The source class of four driving NMOS tube MN4 connects the drain electrode of the 7th driving NMOS tube MN7, the source class ground connection of the 7th driving NMOS tube MN7；
The grid of the 7th driving NMOS tube MN7 connects the outfan of the 7th phase inverter INV7, and the input of the 7th phase inverter INV7 connects
The outfan of hex inverter INV6, the outfan of input connection the 5th phase inverter INV5 of hex inverter INV6, the 5th
The input of phase inverter INV5 connects the outfan of the 13rd phase inverter INV13, and the input of the 13rd phase inverter INV13 connects
The outfan of the 12nd phase inverter INV12, the second of the input connection output control circuit T of the 12nd phase inverter INV12 is defeated
Go out to hold Z2；
As shown in figure 3, the substrate of the source class of the 4th PMOS MP4 and substrate and the 3rd PMOS MP3 connects the second electricity
The drain electrode of drain electrode connection the 5th PMOS MP5 of source VDD2, the grid of the 4th PMOS MP4 and the 4th PMOS MP4, the 5th
The grounded-grid of PMOS MP5, the drain electrode of the 5th PMOS MP5 connects the source class of the 6th PMOS MP6, the 6th PMOS MP6
Grid and drain electrode connect the grid of the 8th NMOS tube MN8 and drain electrode, the grid of the 7th NMOS tube MN7, the 6th NMOS tube MN6
Grid, the source class of the 8th NMOS tube MN8 connects drain electrode and substrate, the grid of the 7th PMOS MP7 and the source of the 7th PMOS MP7
Level ground connection；The drain electrode of the source class of the 6th NMOS tube MN6 and the 6th NMOS tube MN6 connects；The source class of the 7th NMOS tube MN7, the 9th
The grid of NMOS tube MN9, the drain electrode of the 8th PMOS MP8 connect and export MID signal；The grid of the 8th PMOS MP8 and source
Level ground connection；The drain electrode of substrate connection the 9th PMOS MP9 of the 8th PMOS MP8, the grounded-grid of the 9th PMOS MP9, the
The substrate of nine PMOS MP9 and source class connect the first power vd D1.
In example, VDD1 is 2.5V, and VDD2 is optional 3.3V or 2.5V, and circuit has two kinds of working conditions：High-impedance state and just
Often working condition.
(1) output circuit is in high resistant working condition：
When output control terminal OEN is high level voltage 2.5V, output signal Z1 of output control circuit T and Z2 export respectively
Low level voltage 0V and high level voltage 2.5V, Z1 shift buffer circuit SHIFT through BUF1 drive level, export low level voltage
MID, drives the conducting of PMOS MP1, pulling drive signal LP is pulled to optional high level 3.3V or 2.5V so that pulling drive
Pipe PMOS MP2 turns off.Meanwhile, through BUF2 and INV5, the chain of inverters of INV6, INV7 composition obtains LN output low level electricity to Z2
Pressure 0V, drop-down driving tube MN5 conducting turns off.Circuit output shows as high-impedance state.
(2) output circuit is in normal operating conditions：
When output control terminal OEN is low level voltage 0V, output control circuit T normal output signal, Z1 and Z2 response is defeated
Enter signal D.
(1) as signal D input low level voltage 0V, Z1 shifts buffer circuit SHIFT through BUF1 drive level, and clamper is defeated
Go out low level voltage 307, be worth for MID.Low pressure MID signal drives the conducting of PMOS MP1, and pulling drive signal LP is pulled to high electricity
Flat 3.3V/2.5V, PMOS MP2 turns off.Now, chain of inverters output low level voltage is formed by phase inverter INV1 and INV2
0V, NMOS tube MN1 is closed.And, the phase inverter INV3 that pulling drive signal LP drives, INV4 export 302 high level voltages
, so that the conducting of NMOS tube MN2, the parasitic capacitance electric charge at node 303 is by MN2 repid discharge to low level voltage 0V for 2.5V.
Low level voltage Z2, through BUF2 and phase inverter INV5, obtains drop-down drive signal after the chain of inverters of INV6, INV7 composition simultaneously
LN, now, LN is high level voltage 2.5V, drop-down driving NMOS tube MN5 conducting, and output PAD is pulled to low level voltage 0V.
(2) as signal D putting high level voltage 2.5V, Z1, Z2 respond output high level voltage 2.5V.Z2 through BUF2 and
The chain of inverters of INV5, INV6, INV7 composition obtains the drop-down drive signal LN of low level voltage 0V, and drop-down driving tube MN5 closes
Disconnected.Meanwhile, Z1 moves level shift circuit SHIFT through BUF1 rear-guard, obtains output high level voltage 3.3V/2.5V so that pre- drive
Dynamic PMOS MP1 turns off.Now, chain of inverters INV1 and INV2 output high level voltage 2.5V be so that the conducting of NMOS tube MN1,
Now, NMOS tube MN2 does not also turn off in time, and the spurious charge on node 303 and node 304 and NMOS tube MN2 passes through NMOS
Pipe MN2 discharges.Gradually decrease with spurious charge, pulling drive signal LP begins to decline, until the height less than phase inverter INV3
During threshold voltage, phase inverter INV3 upset is so that node 305 output high level voltage 2.5V, and then NMOS tube MN3 is led
Logical.Meanwhile, INV4 output low level voltage makes NMOS tube MN2 turn off.Spurious charge on node 304 utilizes NMOS tube MN1
Further speed up electric discharge with NMOS tube MN3, until pulling drive signal LP is pulled low to level voltage MID, this voltage makes to drive
Dynamic pipe MP2 conducting.PAD output high level voltage 3.3V/2.5V.So far, PAD completes the lever boosting of 2.5V to 3.3/2.5V
Conversion.
Need explanation situation have following some：
(1) explanation of level shift circuit SHIFT circuit.Shown in level shift circuit SHIFT such as Fig. 5 (a), in the present invention
The middle level shift circuit as an output buffering.As A input 0V, through phase inverter INV8 and INV9, export electricity respectively
Put down as 2.5V signal 501 and variable drive low level MID signal.The circuit theory of INV8 and INV9 such as Fig. 5 (b) and Fig. 5 (c),
The phase inverter being made up of PMOS MP4 and NMOS tube MN5, height output level is 2.5V, low output level to MID.Now, NMOS
Pipe MN11 turns off, and NMOS tube MN10 turns on, and PMOS MP11 turns on, and intersects latch and makes output OUT be clamped to low level electricity
Pressure MID.When A inputs as high level voltage 2.5V, phase inverter INV8 output signal 501 is low level voltage MID, and MN10 closes
Disconnected, INV9 output high level voltage 2.5V, MN11 turn on so that node 502 is pulled low to low level voltage MID, PMOS simultaneously
MP10 turns on, and OUT intersects latch output high level voltage 3.3V.Level shifting buffer SHIFT, using MID signal, need not
In the case of high tension apparatus, obtain optional high level 3.3V or 2.5V output.
(2) variable drive signal MID signal.MID Design of Signal is a middle low level voltage value, as shown in fig. 6, MID
Signal is connected on the grid end of PMOS driving tube MP2, as the pull-up P pipe drive signal LP of output PAD.Generally will as shown in Fig. 6 (a)
This voltage design to 0V, when making itself difference DELTA 1=0V-2.5V and power supply between.I other words so that the VGS=- of outlet tube
During 2.5V, meet the requirement of quick output driving.Boost function to be realized, supply voltage must be raised to 3.3V by 2.5V, is
Say, the voltage difference between grid source rises to Δ2=0V-3.3V.According to the requirement of above-mentioned design, under 0.25um process conditions, it is
Ensure that transistor will not cause punch through because of overvoltage, MP2 etc. must adopt high tension apparatus, and this will increase technological design difficulty, no
Compatibility beneficial to CMOS technology.In the present invention, still adopt the transistor MP2 of common process, the voltage improving MID is so that MP2
The voltage difference VGS=Δ at pipe grid source two ends3=MID-3.3V approximates -2.5V, to ensure in the situation not adopting high tension apparatus
Under, MP2 pipe remains to normally effectively work.Generally, gate source voltage difference VGS=Δ4The absolute value of=MID-2.5V is more than PMOS
The absolute value of the threshold value of pipe | VTh, P|, then do not interfere with the normal work of output driving pipe.Thus, it is possible to release the voltage of MID
Scope is greater than 0.8V, less than 2.5- | VTh, p|.Give a kind of MID signal in the present invention realizes circuit, as Fig. 6 (b) institute
Show.Supply voltage connects 3.3V/2.5V, PMOS MP4, and MP6, MP7 make resistance, W/L (grid width and grid length) using diode connection
Ratio be 1.PMOS MP5 be normal open pipe, NMOS tube MN8 be also adopted by diode connect, during design W/L be difficult too big.Specifically
Magnitude of voltage is about VGS, and 8 add the overdrive voltage of PMOS MP7.This voltage provides biasing for rear class NMOS tube MN7.
The substrate bias that PMOS MP9 is individually for PMOS MP8 are powered, and PMOS MP8 is designed as the small resistor of diode connection.Node
601 and 602, meet MN6 and MN9 that NMOS tube makees mos capacitance respectively, play the effect of filtering, suppression main circuit is subject to signal fluctuation
The signal noise recalcitrating.This design effectively ensure that the symmetry of node 601 and node 602 both sides branch road and the accurate of signal
Property.3.3V or 2.5V is optionally accessed according to VDD2, the low level MID signal of exportable about 0.8V or 0.5V of this circuit, reach
To Expected Results.
(3) feedback control loop.In traditional pull-up predrive circuit, without feedback control loop, as shown in figure 1, only leaning on single tube
MN01 discharges, therefore, it is impossible to fast and effeciently discharge to pulling drive signal LP.In the present invention, the feedback module of increase
The electric discharge of LP signal can be accelerated.Further illustrate in conjunction with example, due to employing variable drive voltage MID, when VDD2 meets 3.3V
During voltage, gate source voltage difference VGS=Δ in PMOS MP23=0.8-3.3V ≈ -2.5V, pull-up output transistor MP2 grid is defeated
Enter scope to increase, now, still can fast driving successive load without feedback module.But when VDD2 connects 2.5V voltage, PMOS
Absolute value | VGS | of MP4 upper gate source voltage difference=| Δ3|=| 0.5-2.5V |<2.5V.Now, quickly put using feedback circuit
Electricity, to low level voltage, while effectively driving successive load, accelerates the driving to successive load so that during rising delay
Between reduce.Note, MN2 is designed as the wide ratio that falls less than length and manages, and plays the effect of resistance.
(4) phase inverter number explanation.As illustrated, NMOS tube MN1 on Z1 branch road can regard one-level phase inverter as, therefore,
Have passed through altogether Pyatyi reverse drive from the outfan of ZI to the grid of driving tube MP2.In design, two of buffer BUF1
The phase inverter number of branch road should be consistent.On Z2 branch road by buffer BUF2 and phase inverter INV5, INV6, INV7 form anti-
Phase device chain also goes through altogether Pyatyi reverse drive.Design when, Z1 branch road could be kept consistent with the time delay of Z2 branch road so that
The rising edge time delay of output drive signal and trailing edge time delay are of substantially equal.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.Although knot
Close Description of Drawings embodiments of the present invention, but those of ordinary skill in the art can be within the scope of the appended claims
Make various modifications or modification.
Claims (6)
1. a kind of achievable output high level conversion output driving circuit it is characterised in that：Including the first power vd D1, second
Power vd D2, output control circuit T, pull-up P pipe predrive circuit, the second PMOS MP2, the 5th NMOS tube MN5, output isolation
There is circuit in circuit, drop-down N pipe predrive circuit, variable drive signal MID；
Output control circuit T be a tri-state control circuit, include data signal input A, enable signal input part S, first
Outfan Z1, the second outfan Z2；
Pull-up P pipe predrive circuit includes the first output buffer BUF1, level shift buffer circuit SHIFT, the first phase inverter
INV1, the second phase inverter INV2, the first predrive PMOS MP1, the first predrive NMOS tube MN1, output P pipe feedback circuit；
First output buffer BUF1 includes the tenth phase inverter INV10, the 11st phase inverter INV11；
Level shift buffer circuit SHIFT include the tenth PMOS MP10, the 11st PMOS MP11, the tenth NMOS tube MN10,
11st NMOS tube MN11, the 8th phase inverter INV8, the 9th phase inverter INV9；
Output P pipe feedback circuit includes the second NMOS tube MN2, the 3rd NMOS tube MN3, the 3rd phase inverter INV3, the 4th phase inverter
INV4；
Variable drive signal MID occur circuit include the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th
PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube
MN8, the 9th NMOS tube MN9；
Drop-down N pipe predrive circuit include the second output buffer BUF2, the 5th phase inverter INV5, hex inverter INV6,
Seven phase inverter INV7；Second output buffer BUF2 includes the 12nd phase inverter INV12, the 13rd phase inverter INV13；
Output isolation circuit includes the 3rd PMOS MP3, the 4th NMOS tube MN4；
The input A receiving data signal D of output control circuit T, enables signal input part S and receives enable signal OEN, enable letter
Number OEN controls output control circuit T from the first outfan Z1, the second outfan Z2 output two paths of data signal；
First outfan Z1 connects the input of the tenth phase inverter INV10, the outfan of the tenth phase inverter INV10 connects the 11st
The input of phase inverter INV11, the first via of the outfan of the 11st phase inverter INV11 connects the grid of the 12nd PMOS MP12
Pole and the grid of the 12nd NMOS tube MN12, the second tunnel of the outfan of the 11st phase inverter INV11 connects the first phase inverter
The input of INV1, the outfan of the first phase inverter INV1 connects the input of the second phase inverter INV2, the second phase inverter INV2
Outfan connect the first predrive NMOS tube MN1 grid；
8th phase inverter INV8 includes the 12nd PMOS MP12, the 12nd NMOS tube MN12；
9th phase inverter INV9 includes the 13rd PMOS MP13, the 13rd NMOS tube MN13；
The source class of the 12nd PMOS MP12 and substrate connect the first power vd D1, the drain electrode and the tenth of the 12nd PMOS MP12
The drain electrode connection grid of the 13rd PMOS MP13 of two NMOS tube MN12 and the grid of the 13rd NMOS tube MN13, the 12nd
The source class input MID signal of the source class of NMOS tube MN12 and the 13rd NMOS tube MN13；The source class of the 13rd PMOS MP13 and
Substrate connects the first power vd D1, and the drain electrode of the 13rd PMOS MP13 and the drain electrode of the 13rd NMOS tube MN13 connect the 11st
The grid of NMOS tube MN11；The grid of drain electrode first via connection the tenth PMOS MP10 of the 11st NMOS tube MN11, the 11st
Drain electrode second tunnel of NMOS tube MN11 connects the drain electrode of the 11st PMOS MP11；The source class and the tenth of the 11st NMOS tube MN11
The source class input MID signal of NMOS tube MN10；The source class of the tenth PMOS MP10 and substrate and the 11st PMOS MP11
Source class and substrate connect second source VDD2；The grid of the 11st PMOS MP11, the drain electrode and the tenth of the tenth PMOS MP10
The drain electrode of NMOS tube MN10 is simultaneously connected with the grid of the first predrive PMOS MP1；
The substrate of the first predrive PMOS MP1 and source class connect second source VDD2, the drain electrode of the first predrive PMOS MP1
Connect the grid of the second PMOS MP2, the first predrive PMOS with the first via of the drain electrode of the first predrive NMOS tube MN1
Second tunnel of the drain electrode of the drain electrode of MP1 and the first predrive NMOS tube MN1 connects the input of the 3rd phase inverter INV3, and first is pre-
Drive the drain electrode output predrive pull-up signal LP of NMOS tube MN1；The outfan first via of the 3rd phase inverter INV3 connects the 3rd
The grid of NMOS tube MN3, outfan second tunnel of the 3rd phase inverter INV3 connects the input of the 4th phase inverter INV4, and the 4th is anti-
The outfan of phase device INV4 connects the grid of the second NMOS tube MN2, the source class ground connection of the second NMOS tube MN2, the 3rd NMOS tube MN3
Source class input MID signal；The drain electrode of the drain electrode of the second NMOS tube MN2 and the 3rd NMOS tube MN3 connects the first predrive NMOS
The source class of pipe MN1；
The substrate of the source class of the second PMOS MP2 and substrate and the 3rd PMOS MP3 connects second source VDD2, the 2nd PMOS
The drain electrode of pipe MP2 connects the source class of the 3rd PMOS MP3, the grid input MID signal of the 3rd PMOS MP3, the 3rd PMOS
The drain electrode of the drain electrode of MP3 and the 4th NMOS tube MN4 can achieve the output of the output driving circuit exporting high level conversion as this；
The grid of the 4th NMOS tube MN4 connects the first power vd D1, and the source class of the 4th NMOS tube MN4 connects the leakage of the 5th NMOS tube MN5
Pole, the source class ground connection of the 5th NMOS tube MN5；The outfan of grid connection the 7th phase inverter INV7 of the 5th NMOS tube MN5, the 7th
The input of phase inverter INV7 connects the outfan of hex inverter INV6, and the input connection the 5th of hex inverter INV6 is anti-
The outfan of phase device INV5, the input of the 5th phase inverter INV5 connects the outfan of the 13rd phase inverter INV13, and the 13rd is anti-
The input of phase device INV13 connects the outfan of the 12nd phase inverter INV12, and the input of the 12nd phase inverter INV12 connects
The second outfan Z2 of output control circuit T；
The substrate of the source class of the 4th PMOS MP4 and substrate and the 3rd PMOS MP3 connects second source VDD2, the 4th PMOS
The drain electrode of the grid of pipe MP4 and the 4th PMOS MP4 connects the source electrode of the 5th PMOS MP5, and the grid of the 5th PMOS MP5 connects
Ground, the drain electrode of the 5th PMOS MP5 connects the source class of the 6th PMOS MP6, the grid of the 6th PMOS MP6 and drain electrode connection the
The grid of eight NMOS tube MN8 and drain electrode, the grid of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6, the 8th NMOS tube MN8
Source class connect the source electrode of the 7th PMOS MP7 and substrate, the grid of the 7th PMOS MP7 and drain ground connection；6th NMOS tube
The drain electrode of the source class of MN6 and the 6th NMOS tube MN6 connects；The source class of the 7th NMOS tube MN7, the grid of the 9th NMOS tube MN9,
The source electrode of eight PMOS MP8 connects and exports MID signal；The grid of the 8th PMOS MP8 and drain ground connection；8th PMOS
The substrate of MP8 connects the drain electrode of the 9th PMOS MP9, the grounded-grid of the 9th PMOS MP9, the substrate of the 9th PMOS MP9
Connect the first power vd D1 with source class.
2. according to claim 1 a kind of achievable output high level conversion output driving circuit it is characterised in that：Institute
State PMOS MP1, the 4th PMOS MP4 is common process transistor.
3. according to claim 1 a kind of achievable output high level conversion output driving circuit it is characterised in that：Institute
The level stating second source VDD2 is equal to or higher than the level of the first power vd D1.
4. according to claim 1 a kind of achievable output high level conversion output driving circuit it is characterised in that：Institute
The scope stating the level of MID signal is more than VDD2-VDD1, and is less than VDD1- | Vth,p2|, wherein VTh, p2For the second PMOS
The threshold voltage of MP2.
5. according to claim 1 a kind of achievable output high level conversion output driving circuit it is characterised in that：Institute
State the 3rd phase inverter INV3 and the 4th phase inverter INV4, the second NMOS tube MN2, the feedback circuit that the 3rd NMOS tube MN3 is constituted, energy
Enough form positive feedback structure, quickly drag down drive signal, accelerate output driving.
6. according to claim 1 a kind of achievable output high level conversion output driving circuit it is characterised in that：Institute
State the 3rd PMOS MP3, the 4th NMOS tube MN4, the noise jamming introducing with being effectively isolated power supply, improve this achievable defeated
Go out the voltage endurance of output driving circuit output interface and the reliability of high level conversion.
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| CN110729999B (en) * | 2016-03-22 | 2024-04-09 | 华为技术有限公司 | Mode control circuit and apparatus |
| CN107493100B (en) * | 2016-06-12 | 2023-03-31 | 深圳芯启航科技有限公司 | Level converter |
| CN106505988B (en) * | 2016-11-10 | 2019-06-04 | 中国电子科技集团公司第四十七研究所 | Configurable I based on FPGA/O voltage holding circuit |
| CN108206689B (en) * | 2016-12-19 | 2024-02-23 | 上海安其威微电子科技有限公司 | Level shift driving circuit |
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| CN110601690A (en) * | 2019-10-10 | 2019-12-20 | 无锡安趋电子有限公司 | Low-working-voltage rapid downlink level shift circuit |
| CN113395063B (en) * | 2020-03-13 | 2023-12-12 | 中芯国际集成电路制造(上海)有限公司 | Level shift circuit |
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| CN111884648B (en) * | 2020-06-18 | 2021-08-06 | 华南理工大学 | Output feedback logic circuit and chip based on unipolar transistor |
| CN113659813B (en) * | 2021-08-12 | 2023-11-17 | 广东省大湾区集成电路与系统应用研究院 | Driving circuit |
| CN113852182B (en) * | 2021-09-06 | 2023-05-30 | 成都锐成芯微科技股份有限公司 | Power supply selection circuit with floatable input |
| CN115664408B (en) * | 2022-11-10 | 2023-11-21 | 江苏谷泰微电子有限公司 | Level shifter of unknown voltage domain |
| CN115694140B (en) * | 2022-12-28 | 2023-04-04 | 西安水木芯邦半导体设计有限公司 | Driving circuit applied to step-down DC-DC converter |
| CN116979946B (en) * | 2023-07-28 | 2024-03-05 | 北京中科格励微科技有限公司 | Control circuit of adjustable pull-up resistor |
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| CN117318697B (en) * | 2023-09-15 | 2024-06-14 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
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| US5736869A (en) * | 1996-05-16 | 1998-04-07 | Lsi Logic Corporation | Output driver with level shifting and voltage protection |
| JP4816077B2 (en) * | 2005-12-28 | 2011-11-16 | 日本電気株式会社 | Level shift circuit and driver circuit using the same |
| US7804334B2 (en) * | 2008-07-29 | 2010-09-28 | Qualcomm Incorporated | High signal level compliant input/output circuits |
| KR101652824B1 (en) * | 2009-07-29 | 2016-08-31 | 삼성전자주식회사 | Output driver for wide range supply voltages |
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