CN113659813B - Driving circuit - Google Patents

Driving circuit Download PDF

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Publication number
CN113659813B
CN113659813B CN202110924513.1A CN202110924513A CN113659813B CN 113659813 B CN113659813 B CN 113659813B CN 202110924513 A CN202110924513 A CN 202110924513A CN 113659813 B CN113659813 B CN 113659813B
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China
Prior art keywords
mos tube
mos
inverter
driving
tube
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CN202110924513.1A
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CN113659813A (en
Inventor
丁齐兵
郑鲲鲲
王飞
郝炳贤
马玫娟
梁福焕
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Guangdong Greater Bay Area Institute of Integrated Circuit and System
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Guangdong Greater Bay Area Institute of Integrated Circuit and System
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Priority to CN202110924513.1A priority Critical patent/CN113659813B/en
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

The present application provides a driving circuit, comprising: a signal processing unit and a main circuit; the signal processing unit is used for generating driving signals with different driving capacities and time sequences based on the control signals of the driving circuit, and applying each driving signal to a corresponding MOS tube in the main circuit; when the control signal changes under the action of each driving signal, the main circuit generates corresponding transient compensation so that the output current of the main circuit reaches a preset value within preset time and no overshoot or low current phenomenon occurs; the pull-up tube and the pull-down tube of the main circuit are controlled to be not conducted simultaneously through time sequence.

Description

Driving circuit
Technical Field
The application belongs to the technical field of power electronics, and particularly relates to a driving circuit.
Background
Referring to fig. 1, there is shown a prior art provided drive circuit; the driving circuit comprises: the reference current Iref is directly connected to the drain end and the gate end of the MOS tube MP1, the gate end of the MOS tube MP2 and the gate end of the MOS tube MP 4; meanwhile, the MOS transistor MP2 is connected in series with the MOS transistor MN7 between the low voltage power supply VDD and the ground, and the MOS transistor MP5 is connected in series with the MOS transistor MP4 between the low voltage power supply VDD and the ground, and the gate ends of the two MOS transistors all receive signals (g 1 and g2 shown in figure 1) after control signals of the driving circuit pass through corresponding inverters (INV 1 and INV2 shown in figure 1). MOS tubes MP_HV2, MN_HV4 and MN6 are sequentially connected in series between a high-voltage power supply and the ground.
In the structure shown in fig. 1, when the control signal is changed between on and off, the output current of the driving circuit has an overshoot or a lower current phenomenon, and then the pull-up tube mp_hv2 and the pull-down tubes mn_hv4 and MN6 may be turned on at the same time, which causes a great power loss.
Disclosure of Invention
Therefore, an object of the present application is to provide a driving circuit for realizing that an output current of the driving circuit reaches a predetermined value quickly, avoiding overshoot or low current phenomenon, avoiding power loss, improving stable operation of the circuit and reducing power consumption.
The application discloses a driving circuit, which is characterized by comprising: a signal processing unit and a main circuit;
the signal processing unit is used for generating driving signals with different driving capacities and time sequences based on the control signals of the driving circuit, and applying each driving signal to a corresponding MOS tube in the main circuit;
when the control signals change under the action of the driving signals, the main circuit generates corresponding transient compensation so that the output current of the main circuit reaches a preset value within preset time, and overshoot or low current phenomenon does not occur.
Optionally, the signal processing unit generates 6 of the driving signals.
Optionally, each driving signal acts on the gate end of a different MOS transistor in the main circuit.
Optionally, the signal processing unit includes: eight inverters;
the first inverter, the second inverter, the third inverter and the fourth inverter are sequentially connected in series;
the output end of the fourth inverter is used as a second output end of the signal processing unit and outputs a second driving signal;
the input end of the fifth inverter is respectively connected with the output end of the first inverter and the input end of the second inverter, and the connection point is used as a fourth output end of the signal processing unit and outputs a fourth driving signal;
the output end of the fifth inverter is used as a first output end of the signal processing unit and outputs a first driving signal;
the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series;
the input end of the sixth inverter is respectively connected with the output end of the second inverter and the input end of the third inverter, and the connection point is used as a third output end of the signal processing unit and outputs a third driving signal;
a connection point between the seventh inverter and the eighth inverter as a fifth output terminal of the signal processing unit, outputting a fifth driving signal;
the output end of the eighth inverter is used as a sixth output end of the signal processing unit and outputs a sixth driving signal.
Alternatively, the driving capability and timing of eight of the inverters are different.
Optionally, the closing speed of the first driving signal and the second driving signal is faster than a preset closing speed, and the opening speed of the first driving signal and the second driving signal is slower than a preset opening speed;
the fifth driving signal has a preset delay;
the driving capability of the sixth driving signal is larger than the preset driving capability.
Optionally, in the main circuit:
an eighth MOS tube and a ninth MOS tube form a current mirror circuit;
the tenth MOS tube and the eleventh MOS tube form a current mirror circuit;
the twelfth MOS tube and the thirteenth MOS tube form a current mirror circuit;
the fifth MOS tube and the sixth MOS tube form a current mirror circuit;
the fourteenth MOS tube, the fifteenth MOS tube, the sixteenth MOS tube and the seventeenth MOS tube form a current mirror circuit.
Optionally, the main circuit includes: the first resistor, the second resistor, the first capacitor, the second capacitor and the first to twentieth MOS transistors; wherein:
the fifth MOS tube, the first MOS tube and the eighth MOS tube are sequentially connected in series between a high-voltage power supply and the ground;
the sixth MOS tube, the fourth MOS tube and the thirteenth MOS tube are sequentially connected in series between the high-voltage power supply and the ground;
the connection point between the sixth MOS transistor and the fourth MOS transistor is used as the output end of the main circuit;
the first resistor, the seventh MOS tube and the second MOS tube are sequentially connected in series between the high-voltage power supply and the ground;
the connection point between the first resistor and the seventh MOS tube; the gate terminal of the fifth MOS tube, the gate terminal of the sixth MOS tube and the drain terminal of the nineteenth MOS tube are respectively connected;
the gate end of the seventh MOS tube is connected with a connection point between the fifth MOS tube and the first MOS tube;
the second resistor, the third MOS tube and the eleventh MOS tube are sequentially connected in series between the high-voltage power supply and the ground;
the connection point between the second resistor and the third MOS tube is connected with the gate end of the nineteenth MOS tube; the source end of the nineteenth MOS tube is connected with the high-voltage power supply;
the fifteenth MOS tube, the twenty-second MOS tube and the ninth MOS tube are sequentially connected in series between a low-voltage power supply and the ground;
the sixteenth MOS tube and the tenth MOS tube are sequentially connected in series between the low-voltage power supply and the ground;
the seventeenth MOS tube, the eighteenth MOS tube and the twelfth MOS tube are sequentially connected in series between the low-voltage power supply and the ground;
the source end of the fourteenth MOS tube is connected with the low-voltage power supply;
the drain end of the fourteenth MOS tube is respectively connected with the gate ends of the fourteenth to seventeenth MOS tubes, one end of the first capacitor is connected with one end of the second capacitor, and the connection point is used for receiving reference current;
the other end of the first capacitor is connected with the low-voltage power supply;
the other end of the second capacitor is connected with a connection point between the fifteenth MOS tube and the twentieth MOS tube;
the connection point between the ninth MOS tube and the twentieth MOS tube is respectively connected with the gate end of the ninth MOS tube and the gate end of the eighth MOS tube;
the connection point between the sixteenth MOS tube and the tenth MOS tube is respectively connected with the gate end of the tenth MOS tube and the gate end of the eleventh MOS tube;
the connection point between the eighteenth MOS tube and the twelfth MOS tube is respectively connected with the gate end of the twelfth MOS tube and the gate end of the thirteenth MOS tube;
the gate end of the first MOS tube is used as a first control end of the main circuit;
the gate end of the second MOS tube is used as a second control end of the main circuit;
the grid end of the twentieth MOS tube is used as a third control end of the main circuit;
the gate end of the third MOS tube is used as a fourth control end of the main circuit;
the gate end of the eighteenth MOS tube is used as a fifth control end of the main circuit;
and the gate end of the fourth MOS tube is used as a sixth control end of the main circuit.
Optionally, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, and the twentieth MOS transistor are all low-voltage NMOS;
the fourteenth MOS tube, the fifteenth MOS tube, the sixteenth MOS tube, the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube are all low-voltage PMOS;
the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all high-voltage NMOS;
the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are all high-voltage PMOS.
Optionally, when the eighteenth MOS transistor is turned off, the seventeenth MOS transistor is turned off.
As can be seen from the above technical solution, the driving circuit provided by the present application includes: a signal processing unit and a main circuit; the signal processing unit is used for generating driving signals with different driving capacities and time sequences based on the control signals of the driving circuit, and applying each driving signal to a corresponding MOS tube in the main circuit; when the control signal changes under the action of each driving signal, the main circuit generates corresponding transient compensation so that the output current of the main circuit reaches a preset value within preset time and no overshoot or low current phenomenon occurs; the pull-up tube and the pull-down tube of the main circuit are controlled to be not conducted simultaneously through time sequence.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art drive circuit;
FIG. 2 is a schematic diagram of a driving circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another driving circuit according to an embodiment of the present application;
fig. 4 is a timing chart of an output current of a driving circuit according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiment of the application provides a driving circuit, which is used for solving the problems that in the prior art, when the driving circuit is changed between on and off, the output current of the driving circuit has the phenomenon of overshoot or lower current, and then the pull-up tube MP_HV2 and the pull-down tubes MN_HV4 and MN6 are simultaneously conducted, so that the power loss of the circuit is caused.
Referring to fig. 2, the driving circuit includes: a signal processing unit 10 and a main circuit 20.
The signal processing unit 10 is configured to generate driving signals with different driving capacities and timings based on an input signal CMD of the driving circuit, and apply each driving signal to a corresponding MOS transistor in the main circuit 20.
The signal processing unit 10 can generate a plurality of driving signals with different driving capabilities and timings through a plurality of inverters, which is not limited to the above method, and is not described herein, so long as it can generate a plurality of driving signal interfaces with different driving capabilities and timings, which are all within the protection scope of the present application.
Specifically, the input terminal of the signal processing unit 10 is configured to receive an input signal CMD, and each output terminal of the signal processing unit 10 is connected to a corresponding gate terminal of the main circuit 20.
When the input signal CMD changes under the action of each driving signal, the main circuit 20 generates corresponding transient compensation, so that the output current of the main circuit 20 reaches a predetermined value within a preset time, and no overshoot or low current phenomenon occurs.
When the input signal CMD characterizes that the MOS transistor in the main circuit 20 needs to switch the switch state, the driving signal processing unit 10 generates a plurality of driving signals according to the input signal CMD, and the plurality of driving signals act on the corresponding MOS transistor in the main circuit 20, so as to further realize transient compensation in the main circuit 20, thereby avoiding the phenomenon that the output current of the main circuit 20 has an overshoot or a lower current when the switch state needs to be switched, and the phenomenon that the pull-up transistor and the pull-down transistor in the main circuit 20 are simultaneously turned on, improving the stability of the output current and reducing the loss.
It should be noted that the number and the driving capability and the timing of the driving signals with different driving capabilities and timings generated by the signal processing unit 10 are related to the corresponding MOS transistors in the main circuit 20.
Specifically, the signal processing unit 10 generates 6 different driving capabilities and timing driving signals. Of course, other values are also possible, and are not described in detail herein, and are all within the scope of the present application.
Each driving signal acts on the gate ends of different MOS transistors in the main circuit 20 respectively; i.e. to different gate terminals of the main circuit 20.
In practical application, referring to fig. 3, the signal processing unit 10 includes: eight inverters; the method comprises the following steps of: the first, second, third, fourth, fifth, sixth, seventh, and eighth inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, and INV8.
The first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 are sequentially connected in series.
Specifically, the input end of the first inverter INV1 is used as the input end of the signal processing unit 10 to receive the input signal CMD; the output end of the first inverter INV1 is connected with the input end of the second inverter INV 2; the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, and the output end of the third inverter INV3 is connected with the input end of the fourth inverter INV 4.
An output terminal of the fourth inverter INV4 outputs the second driving signal g2 as a second output terminal of the signal processing unit 10.
The input end of the fifth inverter INV5 is connected to the output end of the first inverter INV1 and the input end of the second inverter INV2, respectively, and the connection point is used as the fourth output end of the signal processing unit 10 to output the fourth driving signal g4.
An output terminal of the fifth inverter INV5 outputs the first driving signal g1 as a first output terminal of the signal processing unit 10.
The sixth inverter INV6, the seventh inverter INV7, and the eighth inverter INV8 are sequentially connected in series.
Specifically, the output end of the sixth inverter INV6 is connected to the input end of the seventh inverter INV7, and the output end of the seventh inverter INV7 is connected to the input end of the eighth inverter INV8.
The input end of the sixth inverter INV6 is connected to the output end of the second inverter INV2 and the input end of the third inverter INV3, respectively, and the connection point is used as the third output end of the signal processing unit 10 to output the third driving signal g3.
A connection point between the seventh inverter INV7 and the eighth inverter INV8 is outputted as a fifth output terminal of the signal processing unit 10, and a fifth driving signal g5.
An output terminal of the eighth inverter INV8 outputs a sixth driving signal g6 as a sixth output terminal of the signal processing unit 10.
It should be noted that the driving capability and timing of the eight inverters are different; the driving capability and timing sequence of each inverter are not described in detail herein, and are all within the protection scope of the present application.
In practical application, the first driving signal g1 and the second driving signal g2 have fast closing speed and slow opening speed; the fifth driving signal g5 has a preset delay; the driving capability of the sixth driving signal g6 is larger than the preset driving capability.
In any of the above embodiments, referring to fig. 3, the main circuit 20 includes: the first resistor R1, the second resistor R2, the first capacitor C1, the second capacitor C2 and the first to twentieth MOS transistors; wherein:
the fifth MOS tube MP_HV1, the first MOS tube MN_HV1 and the eighth MOS tube MN1 are sequentially connected in series between the high voltage power supply VBAT and the ground.
Specifically, the source end of the fifth MOS tube MP_HV1 is connected with a high-voltage power supply VBAT; the drain end of the fifth MOS tube MP_HV1 is connected with the drain end of the first MOS tube MN_HV 1; the source end of the first MOS tube MN_HV1 is connected with the drain end of the eighth MOS tube MN1, and the source end of the eighth MOS tube MN1 is grounded.
The sixth MOS transistor mp_hv2, the fourth MOS transistor mn_hv4 and the thirteenth MOS transistor MN6 are sequentially connected in series between the voltage source VBAT and ground.
Specifically, the source end of the sixth MOS tube MP_HV2 is connected with a high-voltage power supply VBAT; the drain end of the sixth MOS tube MP_HV2 is connected with the drain end of the fourth MOS tube MN_HV 4; the source end of the fourth MOS tube MN_HV4 is connected with the drain end of the thirteenth MOS tube MN6, and the source end of the thirteenth MOS tube MN6 is grounded.
The connection point between the sixth MOS transistor mp_hv2 and the fourth MOS transistor mn_hv4 is used as the output terminal OUT of the main circuit 20.
The first resistor R1, the seventh MOS tube MP_HV3 and the second MOS tube MN_HV2 are sequentially connected in series between the high-voltage power supply VBAT and the ground.
Specifically, one end of the first resistor R1 is connected with a high-voltage power supply VBAT; the other end of the first resistor R1 is connected with the source end of the seventh MOS tube MP_HV 3; the drain end of the seventh MOS tube MP_HV3 is connected with the drain end of the second MOS tube MN_HV2, and the source end of the second MOS tube MN_HV2 is grounded.
A connection point between the first resistor R1 and the seventh MOS tube MP_HV 3; and the gate terminal of the fifth MOS tube MP_HV1, the gate terminal of the sixth MOS tube MP_HV2 and the drain terminal of the nineteenth MOS tube MP6 are respectively connected.
The gate end of the seventh MOS tube MP_HV3 is connected with the connection point between the fifth MOS tube MP_HV1 and the first MOS tube MN_HV 1.
The second resistor R2, the third MOS transistor mn_hv3 and the eleventh MOS transistor MN4 are sequentially connected in series between the high-voltage power supply VBAT and ground.
Specifically, one end of the second resistor R2 is connected with the high-voltage power supply VBAT; the other end of the second resistor R2 is connected with the drain end of the third MOS tube MN_HV 3; the source end of the third MOS tube MN_HV3 is connected with the drain end of the eleventh MOS tube MN4, and the source end of the eleventh MOS tube MN4 is grounded.
The connection point between the second resistor R2 and the third MOS tube MN_HV3 is connected with the gate end of the nineteenth MOS tube MP 6; the source end of the nineteenth MOS tube MP6 is connected with the high-voltage power supply VBAT.
The fifteenth MOS transistor MP2, the twentieth MOS transistor MN7, and the ninth MOS transistor MN2 are sequentially connected in series between the low voltage power supply VDD and ground.
Specifically, the source end of the fifteenth MOS transistor MP2 is connected to the low voltage power supply VDD; the drain end of the fifteenth MOS tube MP2 is connected with the drain end of the twentieth MOS tube MN 7; the source end of the twentieth MOS tube MN7 is connected with the drain end of the ninth MOS tube MN 2; the source terminal of the ninth MOS transistor MN2 is grounded.
The sixteenth MOS transistor MP3 and the tenth MOS transistor MN3 are sequentially connected in series between the low voltage power supply VDD and the ground.
Specifically, the source end of the sixteenth MOS transistor MP3 is connected to the low voltage power supply VDD, the drain end of the sixteenth MOS transistor MP3 is connected to the drain end of the tenth MOS transistor MN3, and the source end of the tenth MOS transistor MN3 is grounded.
Seventeenth MOS pipe MP4, eighteenth MOS pipe MP5 and twelfth MOS pipe MN5 are connected in series in proper order and are arranged between low voltage power supply VDD and ground.
Specifically, the source end of the seventeenth MOS tube MP4 is connected to the low voltage power supply VDD; the drain end of the seventeenth MOS tube MP4 is connected with the source end of the eighteenth MOS tube MP 5; the drain end of the eighteenth MOS tube MP5 is connected with the drain end of the twelfth MOS tube MN 5; the source terminal of the twelfth MOS transistor MN5 is grounded.
The source end of the fourteenth MOS tube MP1 is connected with the low-voltage power supply VDD.
The drain end of the fourteenth MOS tube MP1 is respectively connected with the gate ends of the fourteenth MOS tube MP1 to the seventeenth MOS tube MP4, one end of the first capacitor C1 is connected with one end of the second capacitor C2, and the connection point is used for receiving the reference current Iref.
The other end of the first capacitor C1 is connected to the low voltage power supply VDD.
The other end of the second capacitor C2 is connected with a connection point between the fifteenth MOS tube MP2 and the twentieth MOS tube MN 7.
The connection point between the ninth MOS tube MN2 and the twentieth MOS tube MN7 is respectively connected with the gate end of the ninth MOS tube MN2 and the gate end of the eighth MOS tube MN 1.
The connection point between the sixteenth MOS tube MP3 and the tenth MOS tube MN3 is respectively connected with the gate end of the tenth MOS tube MN3 and the gate end of the eleventh MOS tube MN 4.
The connection point between the eighteenth MOS tube MP5 and the twelfth MOS tube MN5 is respectively connected with the gate end of the twelfth MOS tube MN5 and the gate end of the thirteenth MOS tube MN 6.
The gate terminal of the first MOS transistor mn_hv1 is used as the first control terminal of the main circuit 20, and receives the first driving signal g1 of the signal processing unit 10.
The gate terminal of the second MOS transistor mn_hv2 is used as the second control terminal of the main circuit 20, and receives the second driving signal g2 of the signal processing unit 10.
The gate terminal of the twentieth MOS transistor MN7 serves as a third control terminal of the main circuit 20, and receives the third driving signal g3 of the signal processing unit 10.
The gate terminal of the third MOS transistor mn_hv3 serves as a fourth control terminal of the main circuit 20 and receives the fourth driving signal g4 of the signal processing unit 10.
The gate terminal of the eighteenth MOS transistor MP5 is used as the fifth control terminal of the main circuit 20, and receives the fifth driving signal g5 of the signal processing unit 10.
The gate terminal of the fourth MOS transistor mn_hv4 is used as the sixth control terminal of the main circuit 20 and receives the sixth driving signal g6 of the signal processing unit 10.
It should be noted that, six MOS tubes, i.e., the first MOS tube mn_hv1, the second MOS tube mn_hv2, the twentieth MOS tube MN7, the third MOS tube mn_hv3, the eighteenth MOS tube MP5, and the fourth MOS tube mn_hv4, are used as MOS tubes for controlling the on/off of the main circuit 20.
The sixth MOS transistor mp_hv2 is used as an output pull-up transistor in the main circuit 20; the fourth MOS transistor mn_hv4 and the thirteenth MOS transistor MN6 are output pull-down transistors in the main circuit 20.
The eighth MOS tube MN1 and the ninth MOS tube MN2 form a current mirror circuit; the tenth MOS tube MN3 and the eleventh MOS tube MN4 form a current mirror circuit; the twelfth MOS tube MN5 and the thirteenth MOS tube MN6 form a current mirror circuit; the fifth MOS tube MP_HV1 and the sixth MOS tube MP_HV2 form a current mirror circuit; the fourteenth MOS transistor MP1 and the fifteenth MOS transistor MP2, and the sixteenth MOS transistor MP3 and the seventeenth MOS transistor MP4 constitute a current mirror circuit.
In practical applications, the eighth MOS transistor MN1, the ninth MOS transistor MN2, the tenth MOS transistor MN3, the eleventh MOS transistor MN4, the twelfth MOS transistor MN5, the thirteenth MOS transistor MN6, and the twentieth MOS transistor MN7 are all low-voltage NMOS.
The fourteenth MOS tube MP1, the fifteenth MOS tube MP2, the sixteenth MOS tube MP3, the seventeenth MOS tube MP4, the eighteenth MOS tube MP5 and the nineteenth MOS tube MP6 are all low-voltage PMOS.
The first MOS tube MN_HV1, the second MOS tube MN_HV2, the third MOS tube MN_HV3 and the fourth MOS tube MN_HV4 are all high-voltage NMOS.
The fifth MOS tube MP_HV1, the sixth MOS tube MP_HV2 and the seventh MOS tube MP_HV3 are all high-voltage PMOS.
It should be noted that, the seventeenth MOS transistor MP4 has a larger current during the use, so when it is not needed to use, the seventeenth MOS transistor MP4 is turned off by turning off the eighteenth MOS transistor MP5, so as to save power consumption.
Specifically, when the input signal CMD changes from low level to high level, the first MOS transistor mn_hv1, the second MOS transistor mn_hv2, and the twentieth MOS transistor MN7 are turned on; the third MOS transistor MN_HV3, the eighteenth MOS transistor MP5 and the fourth MOS transistor MN_HV4 are closed. At this time, the fourth MOS transistor MN_HV4 is turned off, and the sixth MOS transistor MP_HV2 is turned on; so that the main circuit 20 can provide a stable output driving current.
When the input signal CMD changes from high level to low level, the first MOS transistor mn_hv1, the second MOS transistor mn_hv2, and the twentieth MOS transistor MN7 are turned off; the third MOS transistor MN_HV3, the eighteenth MOS transistor MP5 and the fourth MOS transistor MN_HV4 are turned on. At this time, the fourth MOS transistor MN_HV4 is turned on, and the sixth MOS transistor MP_HV2 is turned off; so that the main circuit 20 can provide a stable output driving current.
It should be noted that, when the first capacitor C1 and the second capacitor C2 can make each MOS transistor turn off and turn on, the gate-source voltage VGS of the fourteenth MOS transistor MP1 is kept unchanged, so that the output current of the main circuit 20 is effectively ensured not to overshoot or be lower when the switch is turned off and turned on. When the twentieth MOS transistor and the eighteenth MOS transistor MP5 are turned off and on, the gate-source voltage VGS of the fourteenth MOS transistor MP1 is affected, but the two effects are reversed. In addition, the fifteenth MOS transistor MP2 and the seventeenth MOS transistor MP4 have different currents, and the effects thereof are different, so that the second capacitor C2 is introduced, and the effect generated by the twentieth MOS transistor MN7 is increased to cancel the effect generated by the eighteenth MOS transistor MP 5.
Referring to fig. 4, it should be noted that the first driving signal g1 and the second driving signal g2 have a fast closing speed and a slow opening speed; the fifth driving signal g5 has a preset delay; the driving capability of the sixth driving signal g6 is larger than the preset driving capability. The first resistor R1 and the third MOS transistor mn_hv3 can accelerate the turn-on of the sixth MOS transistor mp_hv2, and the second resistor R2 and the nineteenth MOS transistor MP6 can accelerate the turn-off of the sixth MOS transistor mp_hv2, thereby ensuring that the output pull-up transistor and the output pull-down transistor are not simultaneously turned on, and simultaneously, the output of the main circuit 20 does not have overshoot or lower current.
Features described in the embodiments in this specification may be replaced or combined, and identical and similar parts of the embodiments may be referred to each other, where each embodiment focuses on differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The systems and system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. A driving circuit, characterized by comprising: a signal processing unit and a main circuit;
the signal processing unit is used for generating driving signals with different driving capacities and time sequences based on the control signals of the driving circuit, and applying each driving signal to a corresponding MOS tube in the main circuit; the signal processing unit generates 6 driving signals; the closing speed of the first driving signal and the second driving signal is higher than the preset closing speed, and the opening speed of the first driving signal and the second driving signal is lower than the preset opening speed; the fifth driving signal has a preset delay; the driving capability of the sixth driving signal is larger than the preset driving capability;
when the control signals change under the action of the driving signals, the main circuit generates corresponding transient compensation so that the output current of the main circuit reaches a preset value within preset time, overshoot or low current phenomenon does not occur, and the output pull-up tube and the output pull-down tube of the main circuit are controlled to be not conducted simultaneously through time sequence;
the main circuit comprises:
an eighth MOS tube and a ninth MOS tube form a current mirror circuit;
the tenth MOS tube and the eleventh MOS tube form a current mirror circuit;
the twelfth MOS tube and the thirteenth MOS tube form a current mirror circuit;
the fifth MOS tube and the sixth MOS tube form a current mirror circuit;
a fourteenth MOS tube, a fifteenth MOS tube and a sixteenth MOS tube thereof form a current mirror circuit;
the main circuit includes: the first resistor, the second resistor, the first capacitor, the second capacitor and the first to twentieth MOS transistors; wherein:
the fifth MOS tube, the first MOS tube and the eighth MOS tube are sequentially connected in series between a high-voltage power supply and the ground;
the sixth MOS tube, the fourth MOS tube and the thirteenth MOS tube are sequentially connected in series between the high-voltage power supply and the ground;
the connection point between the sixth MOS transistor and the fourth MOS transistor is used as the output end of the main circuit;
the first resistor, the seventh MOS tube and the second MOS tube are sequentially connected in series between the high-voltage power supply and the ground;
the connection point between the first resistor and the seventh MOS tube; the gate terminal of the fifth MOS tube, the gate terminal of the sixth MOS tube and the drain terminal of the nineteenth MOS tube are respectively connected;
the gate end of the seventh MOS tube is connected with a connection point between the fifth MOS tube and the first MOS tube;
the second resistor, the third MOS tube and the eleventh MOS tube are sequentially connected in series between the high-voltage power supply and the ground;
the connection point between the second resistor and the third MOS tube is connected with the gate end of the nineteenth MOS tube; the source end of the nineteenth MOS tube is connected with the high-voltage power supply;
the fifteenth MOS tube, the twenty-second MOS tube and the ninth MOS tube are sequentially connected in series between a low-voltage power supply and the ground;
the sixteenth MOS tube and the tenth MOS tube are sequentially connected in series between the low-voltage power supply and the ground;
the seventeenth MOS tube, the eighteenth MOS tube and the twelfth MOS tube are sequentially connected in series between the low-voltage power supply and the ground;
the source end of the fourteenth MOS tube is connected with the low-voltage power supply;
the drain end of the fourteenth MOS tube is respectively connected with the gate ends of the fourteenth to seventeenth MOS tubes, one end of the first capacitor is connected with one end of the second capacitor, and the connection point is used for receiving reference current;
the other end of the first capacitor is connected with the low-voltage power supply;
the other end of the second capacitor is connected with a connection point between the fifteenth MOS tube and the twentieth MOS tube;
the connection point between the ninth MOS tube and the twentieth MOS tube is respectively connected with the gate end of the ninth MOS tube and the gate end of the eighth MOS tube;
the connection point between the sixteenth MOS tube and the tenth MOS tube is respectively connected with the gate end of the tenth MOS tube and the gate end of the eleventh MOS tube;
the connection point between the eighteenth MOS tube and the twelfth MOS tube is respectively connected with the gate end of the twelfth MOS tube and the gate end of the thirteenth MOS tube;
the gate end of the first MOS tube is used as a first control end of the main circuit;
the gate end of the second MOS tube is used as a second control end of the main circuit;
the grid end of the twentieth MOS tube is used as a third control end of the main circuit;
the gate end of the third MOS tube is used as a fourth control end of the main circuit;
the gate end of the eighteenth MOS tube is used as a fifth control end of the main circuit;
and the gate end of the fourth MOS tube is used as a sixth control end of the main circuit.
2. The driving circuit according to claim 1, wherein each of the driving signals acts on a gate terminal of a different MOS transistor in the main circuit.
3. The drive circuit according to claim 1, wherein the signal processing unit includes: eight inverters;
the first inverter, the second inverter, the third inverter and the fourth inverter are sequentially connected in series;
the output end of the fourth inverter is used as a second output end of the signal processing unit and outputs a second driving signal;
the input end of the fifth inverter is respectively connected with the output end of the first inverter and the input end of the second inverter, and the connection point is used as a fourth output end of the signal processing unit and outputs a fourth driving signal;
the output end of the fifth inverter is used as a first output end of the signal processing unit and outputs a first driving signal;
the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series;
the input end of the sixth inverter is respectively connected with the output end of the second inverter and the input end of the third inverter, and the connection point is used as a third output end of the signal processing unit and outputs a third driving signal;
a connection point between the seventh inverter and the eighth inverter as a fifth output terminal of the signal processing unit, outputting a fifth driving signal;
the output end of the eighth inverter is used as a sixth output end of the signal processing unit and outputs a sixth driving signal.
4. A driving circuit according to claim 3, wherein the driving capability and timing of the eight inverters are different.
5. The drive circuit of claim 1, wherein the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, and the twentieth MOS transistor are low-voltage NMOS;
the fourteenth MOS tube, the fifteenth MOS tube, the sixteenth MOS tube, the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube are all low-voltage PMOS;
the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all high-voltage NMOS;
the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are all high-voltage PMOS.
6. The drive circuit of claim 5, wherein the seventeenth MOS transistor is turned off when the eighteenth MOS transistor is turned off.
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CN110504822A (en) * 2019-08-26 2019-11-26 电子科技大学 Upper power tube drive part by part control circuit suitable for half-bridge gate drive circuit

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CN104638887A (en) * 2015-01-30 2015-05-20 北京时代民芯科技有限公司 Output driving circuit capable of realizing output high level conversion
CN107359787A (en) * 2017-09-08 2017-11-17 电子科技大学 A kind of gate driving circuit of adaptive dead zone time
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