CN116800067A - Load switch driving circuit based on NMOS (N-channel metal oxide semiconductor) tube - Google Patents

Load switch driving circuit based on NMOS (N-channel metal oxide semiconductor) tube Download PDF

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Publication number
CN116800067A
CN116800067A CN202310701716.3A CN202310701716A CN116800067A CN 116800067 A CN116800067 A CN 116800067A CN 202310701716 A CN202310701716 A CN 202310701716A CN 116800067 A CN116800067 A CN 116800067A
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China
Prior art keywords
mos tube
mos
tube
electrode
transistor
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CN202310701716.3A
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Chinese (zh)
Inventor
李子良
张睿君
张在涌
尹虎君
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Xinjixin Beijing Technology Co ltd
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Xinjixin Beijing Technology Co ltd
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Priority to CN202310701716.3A priority Critical patent/CN116800067A/en
Publication of CN116800067A publication Critical patent/CN116800067A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Abstract

The application discloses a load switch driving circuit based on an NMOS tube, wherein a drain electrode of the NMOS tube M0 is connected with a power port, a source electrode of the NMOS tube M0 is connected with an output port, and the load switch driving circuit comprises: the power supply comprises a bias current source, a first current mirror, a charge pump, a second current mirror, a third current mirror, an eighteenth MOS tube and a control unit, wherein the eighteenth MOS tube is connected with a grid electrode of an NMOS tube M0, the first current mirror and the third current mirror, the control unit is used for controlling the eighteenth MOS tube, when a grid control voltage NGATE is smaller than a control voltage VH, the eighteenth MOS tube is controlled to be conducted so as to charge a grid capacitance of the NMOS tube M0, and when the grid control voltage NGATE is larger than or equal to the control voltage VH, the eighteenth MOS tube is controlled to be cut off. The load switch driving circuit has simple structure and strong stability, can greatly reduce Tdelay time, does not influence rising rate of NGATE, and can be widely applied to various power supply systems.

Description

Load switch driving circuit based on NMOS (N-channel metal oxide semiconductor) tube
Technical Field
The application belongs to the technical field of analog circuits, and particularly relates to a load switch driving circuit based on an NMOS (N-channel metal oxide semiconductor) tube.
Background
A load switch is a device with good switching characteristics between the power supply and the load, which is very small in RDS (ON) when it is ON and very small in leakage IDSS when it is off, and which is also a very wide input voltage range. There are many other protection functions such as overheat protection, overcurrent protection, load short-circuit protection, etc.; in addition, the Slew Rate (Slew Rate) of the output voltage can be controlled.
There are two main components of the load switch: the application relates to an NMOS and PMOS, which is mainly applied to a drive protection circuit in a load switch of the NMOS. Since the RDS (ON) of the load switch of the NMOS transistor is small, the gate voltage of the NMOS transistor is higher than the source voltage. The currently used processes are low voltage processes, so a load switch driving circuit for protection is indispensable.
Referring to fig. 1, a schematic circuit diagram of a load switch is shown, which mainly includes an input VIN, an output VOUT, a bias voltage VBIAS, and a control switch ON. When VIN and VBIAS are both ON, ON is turned ON, and according to spec requirements, NGATE (gate control signal of the power tube) rises slowly, and the rising rate of NGATE is completely determined by charging the gate capacitance of the power tube with current. The time from ON to 10% rise in VOUT (Tdelay) is long.
Therefore, in order to solve the above-mentioned problems, it is necessary to provide a load switch driving circuit based on an NMOS transistor.
Disclosure of Invention
In view of the above, the present application is directed to a load switch driving circuit based on an NMOS transistor to optimize Tdelay time of the NMOS transistor.
In order to achieve the above object, an embodiment of the present application provides the following technical solution:
an NMOS transistor-based load switch driving circuit, wherein a drain electrode of the NMOS transistor M0 is connected to a power supply port, and a source electrode is connected to an output port, the load switch driving circuit comprising:
the first end of the bias current source is connected with the analog voltage AVDD and is used for providing a first bias current;
a first current mirror connected to the second terminal of the bias current source for replicating the first bias current;
the charge pump is connected with the power port and is used for acquiring a control voltage VH according to an input voltage VIN;
the second current mirror is connected with the first current mirror, the charge pump and the grid electrode of the NMOS tube M0 and is used for generating a grid electrode control voltage NGATE of the NMOS tube M0 according to the control voltage VH;
a third current mirror connected to the analog voltage AVDD for generating a second bias current;
the control unit is used for controlling the eighteenth MOS tube, when the grid control voltage NGATE is smaller than the control voltage VH, the eighteenth MOS tube is controlled to be conducted so as to charge the grid capacitance of the NMOS tube M0, and when the grid control voltage NGATE is larger than or equal to the control voltage VH, the eighteenth MOS tube is controlled to be cut off.
In an embodiment, the first current mirror includes a first MOS transistor and a second MOS transistor, the second current mirror includes a fourth MOS transistor and a fifth MOS transistor, the first MOS transistor and the second MOS transistor are NMOS transistors, and the fourth MOS transistor and the fifth MOS transistor are PMOS transistors, wherein:
the drain electrode of the first MOS tube is connected with the second end of the bias current source, the drain electrode is in short circuit with the grid electrode, the grid electrode of the second MOS tube is connected with the grid electrode of the first MOS tube, and the source electrodes of the first MOS tube and the second MOS tube are both connected with the ground potential;
the source electrode of the fourth MOS tube and the source electrode of the fifth MOS tube are connected with the output end of the charge pump, the drain electrode of the fourth MOS tube is in short circuit with the grid electrode, the grid electrode of the fourth MOS tube is connected with the grid electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube, and the drain electrode of the fifth MOS tube is connected with the grid electrode of the NMOS tube M0.
In an embodiment, the load switch driving circuit further includes a plurality of first switching tubes, and the first switching tubes include:
the seventh MOS tube is an NMOS tube, the drain electrode of the seventh MOS tube is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube, the source electrode of the seventh MOS tube is connected with the ground potential, and the grid electrode of the seventh MOS tube is connected with the second enable signal ENB;
and the ninth MOS transistor is an NMOS transistor, the drain electrode of the ninth MOS transistor is connected with the grid electrode of the NMOS transistor M0, the source electrode of the ninth MOS transistor is connected with the ground potential, and the grid electrode of the ninth MOS transistor is connected with the second enable signal ENB.
In one embodiment, the load switch driving circuit further includes a plurality of protection tubes, the protection tubes including:
the source electrode of the third MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, and the grid electrode of the third MOS tube is connected with the analog voltage AVDD;
the source electrode of the sixth MOS tube is connected with the drain electrode of the fifth MOS tube, the drain electrode of the sixth MOS tube is connected with the grid electrode of the NMOS tube M0, and the grid electrode of the sixth MOS tube is connected with the input voltage VIN;
and the eighth MOS tube is an NMOS tube, the source electrode of the eighth MOS tube is connected with the ground potential, the drain electrode of the eighth MOS tube is connected with the grid electrode of the NMOS tube M0, and the grid electrode of the eighth MOS tube is connected with the analog voltage AVDD.
In an embodiment, the load switch driving circuit further includes a seventeenth MOS transistor, the seventeenth MOS transistor and the eighteenth MOS transistor are both NMOS transistors, and the eighteenth MOS transistor and the first MOS transistor, the seventeenth MOS transistor and the first MOS transistor respectively form a current mirror;
the grid electrode of the seventeenth MOS tube and the grid electrode of the eighteenth MOS tube are respectively connected with the grid electrode of the first MOS tube, the source electrode of the seventeenth MOS tube and the source electrode of the eighteenth MOS tube are respectively connected with the ground potential, and the drain electrode of the seventeenth MOS tube and the drain electrode of the eighteenth MOS tube are connected with the third current mirror through a plurality of second switch tubes.
In an embodiment, the third current mirror includes a thirteenth MOS transistor and a fourteenth MOS transistor, where the thirteenth MOS transistor and the fourteenth MOS transistor are PMOS transistors, and the third current mirror includes:
the source electrode of the thirteenth MOS tube and the source electrode of the fourteenth MOS tube are respectively connected with the analog voltage AVDD, the drain electrode of the fourteenth MOS tube is in short circuit with the grid electrode, the grid electrode of the thirteenth MOS tube is connected with the grid electrode of the fourteenth MOS tube, the drain electrode of the fourteenth MOS tube is indirectly connected with the drain electrode of the seventeenth MOS tube, and the drain electrode of the thirteenth MOS tube is connected with the control unit.
In an embodiment, the second switching tube includes a fifteenth MOS tube, a sixteenth MOS tube and a nineteenth MOS tube, the fifteenth MOS tube is a PMOS tube, the sixteenth MOS tube and the nineteenth MOS tube are NMOS tubes, wherein:
the source electrode of the fifteenth MOS tube is connected with the analog voltage AVDD, the drain electrode of the fifteenth MOS tube is connected with the drain electrode of the fourteenth MOS tube, and the grid electrode of the fifteenth MOS tube is connected with the grid electrode of the nineteenth MOS tube;
the source electrode of the sixteenth MOS tube is connected with the drain electrode of the seventeenth MOS tube, the drain electrode is connected with the drain electrode of the fourteenth MOS tube, and the grid electrode is connected with the grid electrode of the fifteenth MOS tube;
the source electrode of the nineteenth MOS tube is connected with the drain electrode of the eighteenth MOS tube, and the drain electrode is connected with the drain electrode of the second MOS tube.
In one embodiment, the load switch driving circuit further includes:
the signal at the input end of the delay module Dly is a first enable signal EN, and the first enable signal EN and the second enable signal ENB are opposite signals;
and the twelfth MOS tube is a PMOS tube, the grid electrode of the twelfth MOS tube is connected with the output end of the delay module Dly, the source electrode of the twelfth MOS tube is connected with the source electrode of the thirteenth MOS tube, and the drain electrode of the twelfth MOS tube is connected with the drain electrode of the thirteenth MOS tube.
In an embodiment, the control unit includes an eleventh MOS transistor and a schmitt trigger, where the eleventh MOS transistor is an NMOS transistor, and the control unit includes:
the source electrode of the eleventh MOS tube is connected with the drain electrode of the thirteenth MOS tube, the drain electrode is connected with the ground potential, and the grid electrode is connected with the grid electrode of the NMOS tube M0;
the input end of the Schmitt trigger is connected with the source electrode of the eleventh MOS tube, and the output end of the Schmitt trigger is connected with the grid electrode of the nineteenth MOS tube.
In an embodiment, the control unit further includes a tenth MOS transistor, the tenth MOS transistor is an NMOS transistor, the source is connected to the gate of the eleventh MOS transistor, the drain is connected to the gate of the NMOS transistor M0, and the gate is connected to the analog voltage AVDD.
The application has the following beneficial effects:
the load switch driving circuit has simple structure and strong stability, can greatly reduce Tdelay time, does not influence rising rate of NGATE, and can be widely applied to various power supply systems.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic circuit diagram of a prior art load switch;
FIG. 2 is a schematic diagram of a load switch driving circuit according to a comparative example of the present application;
FIG. 3 is a timing diagram of a load switch driving circuit according to a comparative example of the present application;
FIG. 4 is a schematic diagram of a load switch driving circuit in embodiment 1 of the present application;
fig. 5 is a timing simulation diagram of a load switch driving circuit in embodiment 1 of the present application.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
The application discloses a load switch driving circuit based on an NMOS tube, wherein the drain electrode of the NMOS tube M0 is connected with a power port, the source electrode is connected with an output port, and the load switch driving circuit comprises:
the first end of the bias current source is connected with the analog voltage AVDD and is used for providing a first bias current;
a first current mirror connected to the second terminal of the bias current source for replicating the first bias current;
the charge pump is connected with the power port and is used for acquiring a control voltage VH according to an input voltage VIN;
the second current mirror is connected with the first current mirror, the charge pump and the grid electrode of the NMOS tube M0 and is used for generating a grid electrode control voltage NGATE of the NMOS tube M0 according to the control voltage VH;
a third current mirror connected to the analog voltage AVDD for generating a second bias current;
the control unit is used for controlling the eighteenth MOS tube, when the grid control voltage NGATE is smaller than the control voltage VH, the eighteenth MOS tube is controlled to be conducted so as to charge the grid capacitance of the NMOS tube M0, and when the grid control voltage NGATE is larger than or equal to the control voltage VH, the eighteenth MOS tube is controlled to be cut off.
The present application will be described in detail with reference to specific examples.
Comparative example:
referring to fig. 2, a schematic diagram of a load switch driving circuit based on an NMOS transistor in the prior art is shown, where a drain electrode of the NMOS transistor M0 is connected to a power supply port, and a source electrode is connected to an output port.
The load switch driving circuit includes:
a bias current source IBAIAS, a first end of which is connected with the analog voltage AVDD and is used for providing a first bias current;
a first current mirror connected to the second terminal of the bias current source IBAIAS for replicating the first bias current;
the charge pump is connected with the power port and used for acquiring a control voltage VH according to an input voltage VIN;
the second current mirror is connected to the first current mirror, the charge pump, and the gate of the NMOS transistor M0, and is configured to generate a gate control voltage NGATE of the NMOS transistor M0 according to the control voltage VH.
The first current mirror in this comparative example is an NMOS current mirror, including a first MOS transistor M1 and a second MOS transistor M2, the second current mirror is a PMOS current mirror, including a fourth MOS transistor M4 and a fifth MOS transistor M5, the first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors, the fourth MOS transistor M4 and the fifth MOS transistor M5 are PMOS transistors, wherein:
the drain electrode of the first MOS tube M1 is connected with the second end of the bias current source IBAIAS, the drain electrode is in short circuit with the grid electrode, the grid electrode of the second MOS tube M2 is connected with the grid electrode of the first MOS tube M1, and the source electrode of the first MOS tube M1 and the source electrode of the second MOS tube M2 are both connected with the ground potential;
the source electrode of the fourth MOS tube M4 and the source electrode of the fifth MOS tube M5 are connected with the output end of the charge pump, the drain electrode of the fourth MOS tube M4 is in short circuit with the grid electrode, the grid electrode of the fourth MOS tube M4 is connected with the grid electrode of the fifth MOS tube M5, the drain electrode of the fourth MOS tube M4 is connected with the drain electrode of the second MOS tube M2, and the drain electrode of the fifth MOS tube M5 is connected with the grid electrode of the NMOS tube M0.
In addition, the load switch driving circuit in this comparative example further includes a plurality of first switching tubes including:
the seventh MOS tube M7, the seventh MOS tube M7 is an NMOS tube, the drain electrode is connected with the grid electrode of the first MOS tube M1 and the grid electrode of the second MOS tube M2, the source electrode is connected with the ground potential, and the grid electrode is connected with the second enabling signal ENB;
and the ninth MOS transistor M9 is an NMOS transistor, the drain electrode of the ninth MOS transistor M9 is connected with the grid electrode of the NMOS transistor M0, the source electrode of the ninth MOS transistor M9 is connected with the ground potential, and the grid electrode of the ninth MOS transistor M9 is connected with the second enabling signal ENB.
Further, the load switch driving circuit in this comparative example further includes a plurality of protection pipes including:
the source electrode of the third MOS tube M3 is connected with the drain electrode of the second MOS tube M2, the drain electrode of the third MOS tube M3 is connected with the drain electrode of the fourth MOS tube M4, and the grid electrode of the third MOS tube M3 is connected with the analog voltage AVDD;
the sixth MOS tube M6, the sixth MOS tube M6 is a PMOS tube, the source electrode is connected with the drain electrode of the fifth MOS tube M5, the drain electrode is connected with the grid electrode of the NMOS tube M0, and the grid electrode is connected with the input voltage VIN;
the eighth MOS tube M8, the eighth MOS tube M8 is an NMOS tube, the source electrode is connected with the ground potential, the drain electrode is connected with the grid electrode of the NMOS tube M0, and the grid electrode is connected with the analog voltage AVDD.
In the MOS tube, M0 is a power tube, and M1-M2 and M4-M5 are current mirrors. M7 and M9 are switching tubes, and play a role in turn-off. M3, M6, M8 are protective tubes, which play a role in protection.
For example, in this embodiment, the voltage withstanding voltages of VGS, VDS, VGD of M0 to M9 are 5V, the voltage of vin is 5V, the voltage of avdd is 5V, and the voltage of vh is 10V, so that NGATE is guaranteed to reach 10V, and vgs=5v of the power tube M0. The RDS (ON) is only as small as possible when it reaches the mΩ level.
When ON, the second enable signal ENB changes from 5V to 0V, and the initial voltage of NGATE is 0V. As the current charges the gate capacitance of M0, the rate of charging of NGATE is determined and thus Tdelay time is long.
Referring to fig. 3, which shows a timing simulation diagram of the load switch driving circuit in this comparative example, it can be found that Tdelay time from ON to 10% rise of VOUT is 210 μs.
Example 1:
referring to fig. 4, a schematic diagram of a load switch driving circuit based on an NMOS transistor according to an embodiment of the present application is shown, where a drain electrode of the NMOS transistor M0 is connected to a power port, and a source electrode is connected to an output port.
The load switch driving circuit includes:
a bias current source IBAIAS, a first end of which is connected with the analog voltage AVDD and is used for providing a first bias current;
a first current mirror connected to the second terminal of the bias current source IBAIAS for replicating the first bias current;
the charge pump is connected with the power port and used for acquiring a control voltage VH according to an input voltage VIN;
the second current mirror is connected with the first current mirror, the charge pump and the grid electrode of the NMOS tube M0 and is used for generating a grid electrode control voltage NGATE of the NMOS tube M0 according to the control voltage VH;
a third current mirror connected to the analog voltage AVDD for generating a second bias current;
the eighteenth MOS tube M18 and the control unit, the eighteenth MOS tube M18 is connected with the grid electrode of the NMOS tube M0, the first current mirror and the third current mirror, the control unit is used for controlling the eighteenth MOS tube M18, when the grid control voltage NGATE is smaller than the control voltage VH, the eighteenth MOS tube M18 is controlled to be conducted so as to charge the grid capacitance of the NMOS tube M0, and when the grid control voltage NGATE is larger than or equal to the control voltage VH, the eighteenth MOS tube M18 is controlled to be cut off.
The bias current source IBAIAS, the charge pump, and the MOS transistors M0 to M9 in this embodiment are identical to those in the comparative example, and will not be described here again.
The load switch driving circuit in this embodiment includes a seventeenth MOS transistor M17 and an eighteenth MOS transistor M18, where the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18 are NMOS transistors, and the eighteenth MOS transistor M18 and the first MOS transistor M1, the seventeenth MOS transistor M17 and the first MOS transistor M1 respectively form a current mirror;
the grid electrode of the seventeenth MOS tube M17 and the grid electrode of the eighteenth MOS tube M18 are respectively connected with the grid electrode of the first MOS tube M1, the source electrode of the seventeenth MOS tube M17 and the source electrode of the eighteenth MOS tube M18 are respectively connected with the ground potential, and the drain electrode of the seventeenth MOS tube M17 and the drain electrode of the eighteenth MOS tube M18 are connected with the third current mirror through a plurality of second switch tubes.
Specifically, the third current mirror in this embodiment includes a thirteenth MOS transistor M13 and a fourteenth MOS transistor M14, where the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are PMOS transistors, and the third current mirror includes:
the source electrode of the thirteenth MOS tube M13 and the source electrode of the fourteenth MOS tube M14 are respectively connected with the analog voltage AVDD, the drain electrode of the fourteenth MOS tube M14 is in short circuit with the grid electrode, the grid electrode of the thirteenth MOS tube M13 is connected with the grid electrode of the fourteenth MOS tube M14, the drain electrode of the fourteenth MOS tube M14 is indirectly connected with the drain electrode of the seventeenth MOS tube M17, and the drain electrode of the thirteenth MOS tube M13 is connected with the control unit.
The second switching tube in this embodiment includes a fifteenth MOS tube M15, a sixteenth MOS tube M16, and a nineteenth MOS tube M19, where the fifteenth MOS tube M15 is a PMOS tube, and the sixteenth MOS tube M16 and the nineteenth MOS tube M19 are NMOS tubes, where:
the source electrode of the fifteenth MOS tube M15 is connected with the analog voltage AVDD, the drain electrode is connected with the drain electrode of the fourteenth MOS tube M14, and the grid electrode is connected with the grid electrode of the nineteenth MOS tube M19;
the source electrode of the sixteenth MOS tube M16 is connected with the drain electrode of the seventeenth MOS tube M17, the drain electrode is connected with the drain electrode of the fourteenth MOS tube M14, and the grid electrode is connected with the grid electrode of the fifteenth MOS tube M15;
the source electrode of the nineteenth MOS tube M19 is connected with the drain electrode of the eighteenth MOS tube M18, and the drain electrode is connected with the drain electrode of the second MOS tube M2.
The load switch driving circuit in this embodiment further includes:
the delay module Dly has the input end with the first enable signal EN, the first enable signal EN and the second enable signal ENB are opposite signals, and the first enable signal EN can be converted into the second enable signal ENB through the inverter, so that the system is more stable by the Dly module;
twelfth MOS pipe M12, twelfth MOS pipe M12 is the PMOS pipe, and the grid links to each other with the output of delay module Dly, and the source links to each other with the source of thirteenth MOS pipe M13, and the drain-source resistance links to each other with the drain-source resistance of thirteenth MOS pipe M13.
The control unit in this embodiment includes an eleventh MOS transistor M11 and a schmitt trigger, where the eleventh MOS transistor M11 is an NMOS transistor, and the following:
the source electrode of the eleventh MOS tube M11 is connected with the drain electrode of the thirteenth MOS tube M13, the drain electrode is connected with the ground potential, and the grid electrode is connected with the grid electrode of the NMOS tube M0;
the input end of the Schmitt trigger is connected with the source electrode of the eleventh MOS tube M11, and the output end of the Schmitt trigger is connected with the grid electrode of the nineteenth MOS tube M19.
In addition, the control unit in this embodiment further includes a tenth MOS transistor M10, where the tenth MOS transistor M10 is an NMOS transistor, the source is connected to the gate of the eleventh MOS transistor M11, the drain is connected to the gate of the NMOS transistor M0, and the gate is connected to the analog voltage AVDD.
In this embodiment, M1, M2, M18, and M17 are NMOS current mirrors, the size of M2 is determined by the system, the size of M18 is larger, and the size of M17 is smaller. M4-M5 are PMOS current mirrors, and M13-M14 are PMOS current mirrors. M10, M12, M15, M16 and M19 are switching tubes, and M16 enables the accuracy of the current mirror to be higher, and the current of M17 can be turned off.
In this embodiment, the voltage withstanding voltages of VGS, VDS, VGD of M0 to M19 are 5V, and first, the currents from M1 to M2, and M4 to M5 are output to the NGATE terminal to charge the gate capacitance of the power transistor M0, and the currents are all 100nA when they are designed unchanged.
To increase Tdelay time, the output of M5 is first high current and then kept low to charge M0. Initially, the voltage of NGATE is 0, the voltage of vh is the output voltage of the charge pump, and vin+5v. The normal operating sequence is therefore:
AVDD is powered up first, and then control voltage VH, generated by AVDD and VIN via the charge pump, begins to build. When EN goes from low to high, the initial voltage of NGATE is 0, and in order to ensure the stability of the system time sequence, the VA6 signal is delayed for 2 μs and then goes from low to high, so that in the initial situation, two paths of current mirror images of M2 and M18 are provided to charge NGATE. When the NGATE initial condition begins to rise, the NGATE and VA4 rise at the same rate, the voltage of VA4 is passed through a common source amplifier where M13 and M14 provide the bias current. When NGATE is below VTH, then VA4 is also below VTH, VA5 is high, through the schmitt trigger, so VA6 is also high. VA6 is low when NGATE is greater than VTH. So, in the initial condition, the charging current is M2 plus the current flowing out of M18, and then the NGATE is charged with a large current. When the NGATE voltage is greater than VTH, the current of M18 is turned off, so that the slew rate of NGATE is not affected.
Therefore, the application can greatly reduce Tdelay time, and after NGATE is larger than VTH, VA5 and VA7 signals are turned off, thereby preventing the influence of float gate on VA 6.
Referring to fig. 5, which shows a timing simulation diagram of the load switch driving circuit in this embodiment, it can be found that the Tdelay time from ON to 10% rise in VOUT is reduced from 210 μs to 39 μs in the comparative example.
As can be seen from the technical scheme, the application has the following advantages:
the load switch driving circuit has simple structure and strong stability, can greatly reduce Tdelay time, does not influence rising rate of NGATE, and can be widely applied to various power supply systems.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.

Claims (10)

1. The utility model provides a load switch drive circuit based on NMOS pipe, NMOS pipe M0's drain electrode links to each other with power port, and the source electrode links to each other with output port, its characterized in that, load switch drive circuit includes:
the first end of the bias current source is connected with the analog voltage AVDD and is used for providing a first bias current;
a first current mirror connected to the second terminal of the bias current source for replicating the first bias current;
the charge pump is connected with the power port and is used for acquiring a control voltage VH according to an input voltage VIN;
the second current mirror is connected with the first current mirror, the charge pump and the grid electrode of the NMOS tube M0 and is used for generating a grid electrode control voltage NGATE of the NMOS tube M0 according to the control voltage VH;
a third current mirror connected to the analog voltage AVDD for generating a second bias current;
the control unit is used for controlling the eighteenth MOS tube, when the grid control voltage NGATE is smaller than the control voltage VH, the eighteenth MOS tube is controlled to be conducted so as to charge the grid capacitance of the NMOS tube M0, and when the grid control voltage NGATE is larger than or equal to the control voltage VH, the eighteenth MOS tube is controlled to be cut off.
2. The NMOS transistor-based load switch drive circuit of claim 1, wherein the first current mirror comprises a first MOS transistor and a second MOS transistor, the second current mirror comprises a fourth MOS transistor and a fifth MOS transistor, the first MOS transistor and the second MOS transistor are NMOS transistors, the fourth MOS transistor and the fifth MOS transistor are PMOS transistors, wherein:
the drain electrode of the first MOS tube is connected with the second end of the bias current source, the drain electrode is in short circuit with the grid electrode, the grid electrode of the second MOS tube is connected with the grid electrode of the first MOS tube, and the source electrodes of the first MOS tube and the second MOS tube are both connected with the ground potential;
the source electrode of the fourth MOS tube and the source electrode of the fifth MOS tube are connected with the output end of the charge pump, the drain electrode of the fourth MOS tube is in short circuit with the grid electrode, the grid electrode of the fourth MOS tube is connected with the grid electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube, and the drain electrode of the fifth MOS tube is connected with the grid electrode of the NMOS tube M0.
3. The NMOS transistor-based load switch drive circuit of claim 2, further comprising a number of first switching transistors, the first switching transistors comprising:
the seventh MOS tube is an NMOS tube, the drain electrode of the seventh MOS tube is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube, the source electrode of the seventh MOS tube is connected with the ground potential, and the grid electrode of the seventh MOS tube is connected with the second enable signal ENB;
and the ninth MOS transistor is an NMOS transistor, the drain electrode of the ninth MOS transistor is connected with the grid electrode of the NMOS transistor M0, the source electrode of the ninth MOS transistor is connected with the ground potential, and the grid electrode of the ninth MOS transistor is connected with the second enable signal ENB.
4. The NMOS transistor-based load switch drive circuit of claim 3, further comprising a number of protection transistors, the protection transistors comprising:
the source electrode of the third MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, and the grid electrode of the third MOS tube is connected with the analog voltage AVDD;
the source electrode of the sixth MOS tube is connected with the drain electrode of the fifth MOS tube, the drain electrode of the sixth MOS tube is connected with the grid electrode of the NMOS tube M0, and the grid electrode of the sixth MOS tube is connected with the input voltage VIN;
and the eighth MOS tube is an NMOS tube, the source electrode of the eighth MOS tube is connected with the ground potential, the drain electrode of the eighth MOS tube is connected with the grid electrode of the NMOS tube M0, and the grid electrode of the eighth MOS tube is connected with the analog voltage AVDD.
5. The NMOS transistor-based load switch drive circuit of claim 3, further comprising a seventeenth MOS transistor, wherein the seventeenth MOS transistor and the eighteenth MOS transistor are both NMOS transistors, and wherein the eighteenth MOS transistor and the first MOS transistor, and wherein the seventeenth MOS transistor and the first MOS transistor form a current mirror, respectively;
the grid electrode of the seventeenth MOS tube and the grid electrode of the eighteenth MOS tube are respectively connected with the grid electrode of the first MOS tube, the source electrode of the seventeenth MOS tube and the source electrode of the eighteenth MOS tube are respectively connected with the ground potential, and the drain electrode of the seventeenth MOS tube and the drain electrode of the eighteenth MOS tube are connected with the third current mirror through a plurality of second switch tubes.
6. The NMOS transistor-based load switch drive circuit of claim 5, wherein said third current mirror comprises a thirteenth MOS transistor and a fourteenth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor being PMOS transistors, wherein:
the source electrode of the thirteenth MOS tube and the source electrode of the fourteenth MOS tube are respectively connected with the analog voltage AVDD, the drain electrode of the fourteenth MOS tube is in short circuit with the grid electrode, the grid electrode of the thirteenth MOS tube is connected with the grid electrode of the fourteenth MOS tube, the drain electrode of the fourteenth MOS tube is indirectly connected with the drain electrode of the seventeenth MOS tube, and the drain electrode of the thirteenth MOS tube is connected with the control unit.
7. The NMOS transistor-based load switch drive circuit of claim 6, wherein the second switching transistor comprises a fifteenth MOS transistor, a sixteenth MOS transistor, and a nineteenth MOS transistor, the fifteenth MOS transistor being a PMOS transistor, the sixteenth MOS transistor and the nineteenth MOS transistor being NMOS transistors, wherein:
the source electrode of the fifteenth MOS tube is connected with the analog voltage AVDD, the drain electrode of the fifteenth MOS tube is connected with the drain electrode of the fourteenth MOS tube, and the grid electrode of the fifteenth MOS tube is connected with the grid electrode of the nineteenth MOS tube;
the source electrode of the sixteenth MOS tube is connected with the drain electrode of the seventeenth MOS tube, the drain electrode is connected with the drain electrode of the fourteenth MOS tube, and the grid electrode is connected with the grid electrode of the fifteenth MOS tube;
the source electrode of the nineteenth MOS tube is connected with the drain electrode of the eighteenth MOS tube, and the drain electrode is connected with the drain electrode of the second MOS tube.
8. The NMOS transistor-based load switch drive circuit of claim 6, further comprising:
the signal at the input end of the delay module Dly is a first enable signal EN, and the first enable signal EN and the second enable signal ENB are opposite signals;
and the twelfth MOS tube is a PMOS tube, the grid electrode of the twelfth MOS tube is connected with the output end of the delay module Dly, the source electrode of the twelfth MOS tube is connected with the source electrode of the thirteenth MOS tube, and the drain electrode of the twelfth MOS tube is connected with the drain electrode of the thirteenth MOS tube.
9. The NMOS transistor-based load switch drive circuit of claim 7, wherein the control unit includes an eleventh MOS transistor and a schmitt trigger, the eleventh MOS transistor being an NMOS transistor, wherein:
the source electrode of the eleventh MOS tube is connected with the drain electrode of the thirteenth MOS tube, the drain electrode is connected with the ground potential, and the grid electrode is connected with the grid electrode of the NMOS tube M0;
the input end of the Schmitt trigger is connected with the source electrode of the eleventh MOS tube, and the output end of the Schmitt trigger is connected with the grid electrode of the nineteenth MOS tube.
10. The NMOS transistor-based load switch driving circuit of claim 9, wherein the control unit further comprises a tenth MOS transistor, the tenth MOS transistor is an NMOS transistor, the source is connected to the gate of the eleventh MOS transistor, the drain is connected to the gate of the NMOS transistor M0, and the gate is connected to the analog voltage AVDD.
CN202310701716.3A 2023-06-13 2023-06-13 Load switch driving circuit based on NMOS (N-channel metal oxide semiconductor) tube Pending CN116800067A (en)

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CN202310701716.3A CN116800067A (en) 2023-06-13 2023-06-13 Load switch driving circuit based on NMOS (N-channel metal oxide semiconductor) tube

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Application Number Priority Date Filing Date Title
CN202310701716.3A CN116800067A (en) 2023-06-13 2023-06-13 Load switch driving circuit based on NMOS (N-channel metal oxide semiconductor) tube

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CN116800067A true CN116800067A (en) 2023-09-22

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