CN116075012B - Drive circuit for reducing voltage disturbance - Google Patents

Drive circuit for reducing voltage disturbance Download PDF

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Publication number
CN116075012B
CN116075012B CN202310301235.3A CN202310301235A CN116075012B CN 116075012 B CN116075012 B CN 116075012B CN 202310301235 A CN202310301235 A CN 202310301235A CN 116075012 B CN116075012 B CN 116075012B
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switching tube
voltage
pin
node
driving circuit
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CN116075012A (en
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请求不公布姓名
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Suzhou Baker Microelectronics Co Ltd
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Suzhou Baker Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0064—Earth or grounding circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electronic Switches (AREA)

Abstract

The application provides a driving circuit for reducing voltage disturbance, which comprises a first-stage driving circuit and a second-stage driving circuit; the first stage driving circuit is used for converting a first control signal related to the signal grounding pin SGND into a third control signal TD related to the power grounding pin PGND; the second stage driving circuit is used for converting a third control signal TD related to the power ground pin PGND into a second control signal TG related to a first pin voltage of the first pin BOOST and a second pin voltage of the second pin SWITCH. The driving circuit drives the power switch tube in the LED driving chip through the second control signal TG related to the first pin voltage and the second pin voltage, so that voltage disturbance generated at the power grounding pin PGND can not be conducted into the LED driving chip, and the safety and the stability of LED driving are ensured.

Description

Drive circuit for reducing voltage disturbance
Technical Field
The application relates to the technical field of LED driving, in particular to a driving circuit for reducing voltage disturbance.
Background
The LED driving power supply is generally composed of a control circuit and a power circuit, wherein the power circuit can adopt a circuit topological structure such as BUCK voltage, BOOST voltage or BUCK-BOOST voltage, and the control circuit is generally composed of an LED driving chip and peripheral circuits thereof.
However, the LED driving chip in the prior art generally only includes one ground pin, that is, the control circuit and the power circuit in the prior art are both connected to the same ground pin in the LED driving chip, at this time, since the power circuit generally flows in and out a large current, when the current changes, the voltage at the ground pin changes, so that a voltage disturbance is caused to the ground pin.
In the scheme, the voltage disturbance can be conducted into the LED driving chip through the grounding pin, so that the internal driving circuit of the LED driving chip is disordered, and the safety and stability of the LED driving power supply are reduced.
Disclosure of Invention
The application provides a drive circuit for reducing voltage disturbance, which ensures the safety and stability of LED driving.
In one aspect, a voltage disturbance reduction driving circuit is provided, the voltage disturbance reduction driving circuit including a first stage driving circuit and a second stage driving circuit;
in the first stage driving circuit, a first voltage end is connected to a first node through a first switching tube M1; the first node is connected to a signal ground pin SGND through a fifteenth switching tube M15; the first voltage end is connected to a second node through a second switching tube M2; the second node is connected to the signal ground pin SGND through a third switching tube M3; the control end of the first switching tube M1 is connected to a second node; the control end of the second switching tube M2 is connected to the first node; the control end of the fifteenth switching tube M15 is connected with a first control signal, and the control end of the third switching tube M3 is connected with an inverted signal of the first control signal;
The first voltage end is also connected to a third node through a fourth switching tube M4; the third node is connected to a power ground pin PGND through a sixth switching tube M6; the first voltage end is also connected to a fourth node through a fifth switching tube M5; the fourth node is connected to the power ground pin PGND through a seventh switching tube M7; the third node is connected to the control end of the seventh switching tube M7; the fourth node is connected to the control end of the sixth switching tube M6; the level of the control end of the fourth switching tube M4 and the level of the control end of the second switching tube M2 are reversed; the level of the control end of the fifth switching tube M5 and the level of the control end of the first switching tube M1 are reversed;
the input end of the second-stage driving circuit is connected with the fourth node; the grounding end of the second-stage driving circuit is connected to the power grounding pin PGND; when the fourth node is at a high level, the second-stage driving circuit outputs a high-level signal of a first voltage value; when the fourth node is at a low level, the second stage driving circuit outputs a low level signal of a second voltage value.
In one possible implementation manner, the first stage driving circuit further includes a first inverter A1, a second inverter A2, a third inverter A3, and a fourth inverter A4;
The first control signal is connected with the control end of the third switching tube M3 through a first inverter A1;
the first control signal is connected to the control end of the fifteenth switching tube M15 through a first inverter A1 and a second inverter A2 in sequence;
the first node is connected to the control end of the fourth switching tube M4 through the third inverter A3;
the second node is connected to the control terminal of the fifth switching tube M5 through the fourth inverter A4.
In one possible implementation manner, the positive power supply terminals of the first inverter A1, the second inverter A2, the third inverter A3, and the fourth inverter A4 are respectively connected to the first voltage terminal, and the negative power supply terminals are respectively connected to the signal ground pin SGND.
In one possible implementation manner, the first switching tube M1, the second switching tube M2, the fourth switching tube M4 and the fifth switching tube M5 are PMOS tubes respectively; the third switching tube M3, the sixth switching tube M6, the seventh switching tube M7, and the fifteenth switching tube M15 are NMOS tubes respectively;
or, the first switching tube M1, the second switching tube M2, the fourth switching tube M4 and the fifth switching tube M5 are PNP transistors respectively; the third switching tube M3, the sixth switching tube M6, the seventh switching tube M7, and the fifteenth switching tube M15 are NPN transistors, respectively.
In one possible implementation manner, the high voltage end of the second stage driving circuit is connected to the first pin voltage; the low voltage end of the second-stage driving circuit is connected with a second pin voltage;
the first voltage value is related to the first pin voltage; the second voltage value is related to the second pin voltage.
In a possible implementation manner, in the second stage driving circuit, the high voltage end is connected to a fifth node through a sixteenth switching tube M16 and a ninth switching tube M9 in sequence; the fifth node is connected to the low voltage terminal through an eleventh switching tube M11;
the high-voltage end is also connected to a sixth node through an eighth switching tube M8 and a tenth switching tube M10 in sequence; the sixth node is connected to the low voltage terminal through a twelfth switching tube M12;
the control end of the sixteenth switching tube M16 and the control end of the eleventh switching tube M11 are connected to the sixth node; the control end of the eighth switching tube M8 and the control end of the twelfth switching tube M12 are connected to the fifth node; the inversion level of the fifth node is the output signal of the second-stage driving circuit;
the high-voltage end is also connected to the power grounding pin PGND through a sixteenth switching tube M16 and a thirteenth switching tube M13 in sequence; the high-voltage end is also connected to the power grounding pin PGND through an eighth switching tube M8 and a fourteenth switching tube M14 in sequence;
The control end of the thirteenth switching tube M13 is connected to the level of the fourth node; the control end of the fourteenth switching tube M14 is connected to the inversion level of the fourth node.
In a possible implementation manner, the second stage driving circuit further includes a fifth inverter A5 and a sixth inverter A6;
the fourth node is connected to the control end of the fourteenth switching tube M14 through the fifth inverter A5;
the fifth node outputs a high level signal of a first voltage value or a low level signal of a second voltage value through the sixth inverter A6.
In a possible implementation manner, the positive power supply terminal of the fifth inverter A5 is connected to the first voltage terminal, and the negative power supply terminal is connected to the power ground pin PGND.
In a possible implementation manner, the positive power supply terminal of the sixth inverter A6 is connected to the first pin voltage, and the negative power supply terminal is connected to the second pin voltage.
In one possible implementation manner, in the second stage driving circuit, the eighth switching tube M8 to the tenth switching tube M10, and the sixteenth switching tube M16 are high voltage PMOS tubes;
the eleventh switching tube M11 and the twelfth switching tube M12 are isolated NMOS tubes;
The thirteenth switching tube M13 and the fourteenth switching tube M14 are high-voltage NMOS tubes.
In one possible implementation manner, the eleventh switching tube M11 and the twelfth switching tube M12 are low-voltage NMOS tubes including isolation islands, and the isolation islands of the eleventh switching tube M11 and the twelfth switching tube M12 are connected to the first pin voltage.
In one possible embodiment, the back gates of the eighth to fourteenth switching transistors M8 to M14 and M16 are connected to the respective sources.
In yet another aspect, an LED driver chip is provided that includes a signal ground pin SGND, a power ground pin PGND, and a driver circuit for reducing voltage disturbances as described above.
In yet another aspect, an LED driving power supply is provided, the LED driving power supply including a control circuit; the control circuit comprises the LED driving chip.
The technical scheme that this application provided can include following beneficial effect:
the driving circuit for reducing the voltage disturbance can convert the first control signal inside the LED driving chip into a high-level signal with a first voltage value or a low-level signal with a second voltage value (namely, the first control signal is converted into a second control signal related to a first pin voltage of a first pin BOOST and a second pin voltage of a second pin SWITCH), and the driving of the power SWITCH tube in the LED driving chip is realized through the high-level signal with the first voltage value or the low-level signal with the second voltage value, so that the voltage disturbance generated at the power grounding pin PGND is not conducted into the LED driving chip, and the safety and the stability of LED driving are ensured;
According to the power switch tube driving circuit, the back grids of the switch tubes in the second-stage driving circuit are designed to be connected with the respective source electrodes, so that the situation that the grid-source voltage difference VGS is reduced and the starting voltage VTH is increased is avoided, and therefore, the source voltages of the switch tubes in the second-stage driving circuit can be normally reduced to the starting voltage VTH (about 1.2V), and therefore, the driving circuit for reducing the voltage disturbance can rapidly output driving signals to drive the power switch tubes in the LED driving chip; in addition, when the voltage difference between the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH is reduced to a certain range (about 2.4V), the power SWITCH tube in the LED driving chip can still be driven, so that the reliability of the driving circuit for reducing the voltage disturbance is ensured;
according to the method, the eleventh switching tube M11 and the twelfth switching tube M12 are reasonably arranged as low-voltage switching tubes in the second-stage driving circuit, so that the area of the driving circuit for reducing the voltage disturbance is reduced, and the effect of improving the response speed of the driving circuit for reducing the voltage disturbance is achieved; meanwhile, the isolation islands of the eleventh switching tube M11 and the twelfth switching tube M12 are connected with the first pin voltage with higher voltage, so that the occurrence of electric leakage of the eleventh switching tube M11 and the twelfth switching tube M12 is effectively avoided, and the reliability and the working efficiency of the driving circuit for reducing the voltage disturbance are further improved;
The driving circuit for reducing the voltage disturbance is designed in an LED driving chip in a control circuit of an LED driving power supply, and the LED driving chip comprises a signal grounding pin SGND and a power grounding pin PGND; the LED driving power supply comprises a power circuit except a control circuit, wherein the input end and the output end of the power circuit are grounded and connected to a power grounding pin PGND, the related grounding of the control circuit is grounded and connected to a signal grounding pin SGND, the influence of voltage disturbance on the LED driving power supply can be reduced by the arrangement of the LED driving power supply, the safety and the stability of the LED driving power supply are further improved, in addition, the size of the LED driving power supply can be reduced by the arrangement of the LED driving power supply, and the reliability, the working efficiency and the response speed of the LED driving power supply are improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram showing the structure of an LED driving power source according to an exemplary embodiment.
Fig. 2 shows a schematic internal structure of the LED driving chip U1 of fig. 1.
Fig. 3 is a schematic diagram showing a structure of a driving circuit for reducing voltage disturbance according to an exemplary embodiment.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Fig. 1 is a schematic diagram of an LED driving power supply according to an exemplary embodiment, and as shown in fig. 1, the LED driving power supply includes a power circuit and a control circuit.
Specifically, the power circuit comprises a power inductor L1, a power diode D1, a filter capacitor C2 and an LED load; the control circuit comprises an LED driving chip U1, a charging diode D2, a charging capacitor C1 and other peripheral circuits.
As shown in fig. 1, the LED driving chip U1 includes a signal ground pin SGND and a power ground pin PGND, and both the ground of the input end and the ground of the output end of the power circuit are connected to the power ground pin PGND, and the ground related to the control circuit is connected to the signal ground pin SGND.
In the power circuit, a second pin voltage corresponding to a second pin SWITCH of the LED driving chip U1 is connected to a DA pin of the LED driving chip U1 through a power diode D1; the voltage of the second pin corresponding to the second pin SWITCH is also connected to the power grounding pin PGND through the power inductor L1 and the filter capacitor C2 in sequence; the output end OUT of the LED driving chip is connected to the power grounding pin PGND through an LED load;
in the control circuit, a first pin voltage corresponding to a first pin BOOST of the LED driving chip U1 is connected to the power circuit through a charging diode D2 and a charging capacitor C1.
Fig. 2 is a schematic diagram of the internal structure of the LED driving chip U1 shown in fig. 1. The LED driving chip U1 comprises a pulse generating circuit, an LDO circuit and a driving circuit;
the pulse generating circuit is used for generating a first control signal T, and the reference ground of the first control signal T is a signal grounding pin SGND;
as shown in fig. 2, the output end of the pulse generating circuit and the output end of the LDO circuit are respectively connected with the input end of the driving circuit, and the output end of the driving circuit is connected with the control end of a power switch tube Q1 (the power switch tube Q1 is a built-in switch tube of the LED driving chip U1); the power switch tube Q1 can adopt an NPN triode or an NMOS tube; when the power switch tube Q1 is an NPN triode, the control end of the power switch tube Q1 is a base electrode, and when the power switch tube Q1 is an NMOS tube, the control end of the power switch tube Q1 is a grid electrode.
The driving circuit is configured to convert the first control signal T into a high level signal of a first voltage value or a low level signal of a second voltage value (the high level signal of the first voltage value is a second control signal TG when the high level signal of the first voltage value is related to a first pin voltage of the first pin BOOST; the low level signal of the second voltage value is a second control signal TG when the low level signal of the second voltage value is related to a second pin voltage of the second pin SWITCH), and input the high level signal of the first voltage value or the low level signal of the second voltage value into the control end of the power SWITCH Q1 to control on/off of the power SWITCH Q1.
In one possible implementation, the input terminal of the driving circuit is further connected to a first pin voltage of the first pin BOOST and a second pin voltage of the second pin SWITCH.
Further, as can be seen from fig. 1 and fig. 2, in this embodiment, a BUCK circuit topology is adopted, if the power switch Q1 needs to be driven, the voltage of the control terminal of the power switch Q1 needs to be greater than the voltage of the output terminal of the power switch Q1, when the power switch Q1 is an NPN triode, the output terminal of the power switch Q1 is an emitter, and when the power switch Q1 is an NMOS, the output terminal of the power switch Q1 is a source; at this time, the output end of the power SWITCH tube Q1 is the second pin voltage of the second pin SWITCH of the LED driving chip U1, and the first pin voltage of the first pin BOOST of the LED driving chip is always greater than the second pin voltage of the second pin SWITCH by a threshold value through the charging diode D2 and the charging capacitor C1, so if the second control signal TG related to the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH is input to the control end of the power SWITCH tube Q1, that is, the power SWITCH tube Q1 is driven, so as to achieve the purpose of controlling the LED driving power supply.
Further, as shown in fig. 2, the pulse generating circuit may generate a first control signal T, and the reference ground of the first control signal T is a signal ground pin SGND; then, the first control signal T is input into the driving circuit through the input end of the driving circuit, the driving circuit converts the first control signal T into a second control signal TG related to a first pin voltage of the first pin BOOST and a second pin voltage of the second pin SWITCH through the internal structure, and then the second control signal TG is input into the control end of the power switching tube Q1 through the output end of the driving circuit to drive the power switching tube Q1; at this time, since the reference ground of the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH is the power ground pin PGND, the driving circuit first converts the first control signal T into a third control signal TD related to the power ground pin PGND, and then converts the third control signal TD into a second control signal TG related to the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH.
Based on the above requirements, the present application designs a driving circuit for reducing voltage disturbance, please refer to fig. 3, which illustrates a schematic structure diagram of a driving circuit for reducing voltage disturbance according to an embodiment of the present application, and the driving circuit for reducing voltage disturbance may be applied to the LED driving chip U1 shown in fig. 2. As shown in fig. 3, the driving circuit for reducing voltage disturbance includes a first stage driving circuit and a second stage driving circuit;
The first stage driving circuit corresponds to the left block diagram structure of fig. 3, and the second stage driving circuit corresponds to the right block diagram structure of fig. 3, and is configured to convert the first control signal T related to the signal ground pin SGND into the third control signal TD related to the power ground pin PGND; the second stage driving circuit is configured to convert a third control signal TD related to the power ground pin PGND into a second control signal TG related to a first pin voltage of the first pin BOOST and a second pin voltage of the second pin SWITCH;
in the first stage driving circuit, a first voltage terminal (the first voltage terminal is connected to a first voltage INTVCC in fig. 3, and the first voltage INTVCC is generated by the LDO circuit) is connected to a first node through a first switching tube M1; the first node is connected to the signal ground pin SGND through a fifteenth switching tube M15; the first voltage end is connected to a second node through a second switching tube M2; the second node is connected to the signal ground pin SGND through a third switching tube M3; the control end of the first switching tube M1 is connected to a second node; the control end of the second switching tube M2 is connected to the first node; the control end of the fifteenth switching tube M15 is connected to a first control signal T (as shown in fig. 3, the first control signal T is connected to the control end of the fifteenth switching tube M15 through a first inverter A1 and a second inverter A2, that is, the control end of the fifteenth switching tube M15 is connected to the first control signal T), and the control end of the third switching tube M3 is connected to the inverted signal of the first control signal T (as shown in fig. 3, the first control signal T is connected to the control end of the third switching tube M3 through the first inverter A1, that is, the control end of the third switching tube M3 is connected to the inverted signal of the first control signal T);
The first voltage end is also connected to a third node through a fourth switching tube M4; the third node is connected to the power ground pin PGND through a sixth switching tube M6; the first voltage end is also connected to a fourth node through a fifth switching tube M5; the fourth node is connected to the power ground pin PGND through a seventh switching tube M7; the third node is connected to the control end of the seventh switching tube M7; the fourth node is connected to the control end of the sixth switching tube M6; the level of the control end of the fourth switching tube M4 and the level of the control end of the second switching tube M2 are reversed; the fifth switching tube M5 is in level inversion with the control terminal of the first switching tube M1 (as shown in fig. 3, the first node corresponding to the control terminal of the second switching tube M2 is connected to the control terminal of the fourth switching tube M4 through the third inverter A3, that is, the fourth switching tube M4 is in level inversion with the control terminal of the second switching tube M2; the second node corresponding to the control terminal of the first switching tube M1 is connected to the control terminal of the fifth switching tube M5 through the fourth inverter A4, that is, the fifth switching tube M5 is in level inversion with the control terminal of the first switching tube M1);
the input end of the second-stage driving circuit is connected to the fourth node; the grounding end of the second-stage driving circuit is connected to the power grounding pin PGND; when the fourth node is at a high level, the second stage driving circuit outputs a high level signal of a first voltage value (the high level signal of the first voltage value is a second control signal TG when the high level signal is related to a first pin voltage of the first pin BOOST); when the fourth node is at a low level, the second stage driving circuit outputs a low level signal of a second voltage value (the low level signal of the second voltage value is a second control signal TG when the second pin voltage of the second pin SWITCH is related).
In one possible embodiment, the first stage driving circuit further includes a first inverter A1, a second inverter A2, a third inverter A3, and a fourth inverter A4;
in one possible implementation, the positive power terminals of the first inverter A1, the second inverter A2, the third inverter A3 and the fourth inverter A4 are respectively connected to the first voltage terminal, and the negative power terminals are respectively connected to the signal ground pin SGND.
In one possible implementation manner, the first switching tube M1, the second switching tube M2, the fourth switching tube M4 and the fifth switching tube M5 are PMOS tubes respectively; the third switching tube M3, the sixth switching tube M6, the seventh switching tube M7 and the fifteenth switching tube M15 are NMOS tubes respectively;
or, the first switching tube M1, the second switching tube M2, the fourth switching tube M4 and the fifth switching tube M5 are PNP transistors respectively; the third switching tube M3, the sixth switching tube M6, the seventh switching tube M7 and the fifteenth switching tube M15 are NPN transistors, respectively.
That is, when the first to seventh switching transistors M1 to M7 and the fifteenth switching transistor M15 are NPN transistors or PNP transistors, the control ends of the first to seventh switching transistors M1 to M7 and the fifteenth switching transistor M15 are respective bases;
When the first to seventh switching tubes M1 to M7 and the fifteenth switching tube M15 are NMOS or PMOS, the control ends of the first to seventh switching tubes M1 to M7 and the fifteenth switching tube M15 are respective gates;
in one possible implementation, the high voltage terminal of the second stage driver circuit is connected to the first pin voltage (that is, the high voltage terminal of the second stage driver circuit is connected to the first pin voltage of the first pin BOOST); the low voltage end of the second stage driving circuit is connected to the second pin voltage (that is, the low voltage end of the second stage driving circuit is connected to the second pin voltage of the second pin SWITCH);
the first voltage value is related to the first pin voltage; the second voltage value is related to the second pin voltage. At this time, the high level signal of the first voltage value is the second control signal TG when the first pin voltage of the first pin BOOST is related; the low level signal of the second voltage value is a second control signal TG when the low level signal is related to the second pin voltage of the second pin SWITCH; that is, the second control signal TG is related to the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH.
In a possible embodiment, in the second stage driving circuit, the high voltage terminal is connected to a fifth node through a sixteenth switching transistor M16 and a ninth switching transistor M9 in sequence; the fifth node is connected to the low voltage terminal through an eleventh switching tube M11;
the high-voltage end is also connected to a sixth node through an eighth switching tube M8 and a tenth switching tube M10 in sequence; the sixth node is connected to the low voltage terminal through a twelfth switching transistor M12;
the control end of the sixteenth switching tube M16 and the control end of the eleventh switching tube M11 are connected to the sixth node; the control end of the eighth switching tube M8 and the control end of the twelfth switching tube M12 are connected to the fifth node; the inversion level of the fifth node is the output signal of the second-stage driving circuit;
the high voltage end is also connected to the power grounding pin PGND through a sixteenth switching tube M16 and a thirteenth switching tube M13 in sequence; the high voltage end is also connected to the power grounding pin PGND through an eighth switching tube M8 and a fourteenth switching tube M14 in sequence;
the control end of the thirteenth switching tube M13 is connected to the level of the fourth node; the control end of the fourteenth switching tube M14 is connected to the inverting level of the fourth node.
In one possible embodiment, the second stage driving circuit further includes a fifth inverter A5 and a sixth inverter A6;
the fourth node is connected to the control end of the fourteenth switching tube M14 through the fifth inverter A5;
the fifth node outputs a high level signal of a first voltage value or a low level signal of a second voltage value through the sixth inverter A6.
In one possible implementation, the positive power terminal of the fifth inverter A5 is connected to the first voltage terminal, and the negative power terminal is connected to the power ground pin PGND.
In one possible implementation, the positive power terminal of the sixth inverter A6 is connected to the first pin voltage, and the negative power terminal is connected to the second pin voltage.
In one possible implementation manner, in the second stage driving circuit, the eighth switching tube M8 to the tenth switching tube M10, and the sixteenth switching tube M16 are high voltage PMOS tubes;
the eleventh switching tube M11 and the twelfth switching tube M12 are isolated NMOS tubes;
the thirteenth switching transistor M13 and the fourteenth switching transistor M14 are high-voltage NMOS transistors.
Therefore, the control ends of the eighth switching tube M8 to the fourteenth switching tube M14 and the sixteenth switching tube M16 are the gates respectively.
In one possible implementation, the eleventh switching transistor M11 and the twelfth switching transistor M12 are low-voltage NMOS transistors including isolation islands, and the isolation islands of the eleventh switching transistor M11 and the twelfth switching transistor M12 are connected to the first pin voltage.
In one possible embodiment, the back gates of the eighth through fourteenth switching transistors M8 through M14 and the sixteenth switching transistor M16 are connected to respective sources.
The operating principle of the driving circuit for reducing voltage disturbance based on fig. 3 can be as follows:
the first control signal T generated by the pulse generating circuit may be at a high level or a low level, when the first control signal T is at a high level, the first inverter A1 inverts the first control signal T to change it to a low level, the first control signal T converted to a low level is inverted twice under the action of the second inverter A2, and is converted to a high level again, and since the control end of the third switching tube M3 is connected to the output end of the first inverter A1, the control end of the fifteenth switching tube M15 is connected to the output end of the second inverter A2, therefore, when the sources of the third switching tube M3 and the fifteenth switching tube M15 are both connected to the signal ground pin SGND, the third switching tube M3 is turned off and the fifteenth switching tube M15 is turned on, and the fifteenth switching tube M15 pulls the control end of the second switching tube M2 low, so that the second switching tube M2 is turned on; the first voltage INTVCC at the first voltage end is connected to the input end of a fourth inverter A4 through the second switching tube M2, the fourth inverter A4 inverts the first voltage INTVCC and outputs a low level, the low level is connected to the control end of a fifth switching tube M5 through the output end of the fourth inverter A4, the fifth switching tube M5 is turned on, the fifth switching tube M5 pulls up the control end of a sixth switching tube M6, so that the sixth switching tube M6 is turned on, the control end of a seventh switching tube M7 is pulled down again by the sixth switching tube M6, the seventh switching tube M7 is ensured to be in an off state, and the reliability of the driving circuit for reducing the voltage disturbance is improved; meanwhile, the control end of the thirteenth switching tube M13 is pulled up by the fifth switching tube M5, namely, at the moment, the first-stage driving circuit outputs a high-level third control signal TD which is connected to the control end of the thirteenth switching tube M13, and the thirteenth switching tube M13 is pulled up and turned on; the high-level third control signal TD is further connected to the fourteenth switching tube M14 through the fifth inverter A5, so that the fifth inverter A5 inverts the high-level third control signal TD to obtain a low-level control signal, and the low-level control signal pulls down the control end of the fourteenth switching tube M14 to turn off the fourteenth switching tube M14;
Meanwhile, the thirteenth SWITCH tube M13 pulls down the drain electrode of the ninth SWITCH tube M9, and since the second pin voltage of the second pin SWITCH is connected to the gate electrode of the ninth SWITCH tube M9, the second pin voltage of the second pin SWITCH is lower than the first pin voltage of the first pin BOOST, and the source electrode of the ninth SWITCH tube M9 is in a high level state when the third control signal TD is in a low level, the ninth SWITCH tube M9 is turned on, the thirteenth SWITCH tube M13 pulls down the source electrode of the ninth SWITCH tube M9, and the source electrode of the ninth SWITCH tube M9 is connected to the input end of the sixth inverter A6, so that the sixth inverter A6 inputs a low level and outputs a high level signal of the first voltage value, namely a high level second control signal TG related to the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH;
at this time, the gate of the eighth switching tube M8 is also pulled low, the eighth switching tube M8 is turned on, the drain of the tenth switching tube M10 is connected to the drain of the eighth switching tube M8, and the source of the eighth switching tube M8 is connected to the first pin voltage of the first pin BOOST, so that the eighth switching tube M8 pulls the drain of the tenth switching tube M10 high to the first pin voltage of the first pin BOOST, and the source of the tenth switching tube M10 is correspondingly in a low level state when the third control signal TD is in a low level, so that the high level of the drain of the tenth switching tube M10 is transmitted to the source of the tenth switching tube M10 through the parasitic diode of the tenth switching tube M10, and at this time, the source of the tenth switching tube M10 is converted into the first pin voltage of the first pin BOOST;
In addition, since the gate of the tenth SWITCH tube M10 is connected to the second pin voltage of the second pin SWITCH, the second pin voltage of the second pin SWITCH is lower than the first pin voltage of the first pin BOOST, so that the tenth SWITCH tube M10 is turned on, and in addition, the source of the tenth SWITCH tube M10, the gate of the eleventh SWITCH tube M11 and the drain of the twelfth SWITCH tube M12 are connected to the first pin voltage of the relatively high first pin BOOST, so that the eleventh SWITCH tube M11 is turned on, the eleventh SWITCH tube M11 pulls the source of the ninth SWITCH tube M9 to the second pin voltage of the second pin SWITCH, and the gate voltage of the eighth SWITCH tube M8 and the source voltage of the ninth SWITCH tube M9 are further pulled down, so that the eighth SWITCH tube M8 is reliably turned on, and meanwhile, the sixth inverter A6 is ensured to output the second control signal TG of high level, thereby improving the reliability of the driving circuit.
Conversely, when the first control signal T is at a low level, the first inverter A1 inverts the first control signal T to be at a high level, the first control signal T converted to be at a high level is inverted twice under the action of the second inverter A2, and is converted to be at a low level again, and since the control end of the third switching tube M3 is connected to the output end of the first inverter A1 and the control end of the fifteenth switching tube M15 is connected to the output end of the second inverter A2, when the sources of the third switching tube M3 and the fifteenth switching tube M15 are both connected to the signal ground pin SGND, the third switching tube M3 is turned on and the fifteenth switching tube M15 is turned off, and the control end of the first switching tube M1 is pulled down by the third switching tube M3, so that the first switching tube M1 is turned on;
The first voltage INTVCC at the first voltage end is connected to the input end of a third inverter A3 through the first switching tube M1, the third inverter A3 inverts the first voltage INTVCC and outputs a low level, the low level is connected to the control end of a fourth switching tube M4 through the output end of the third inverter A3, the fourth switching tube M4 is turned on, the fourth switching tube M4 pulls up the control end of a seventh switching tube M7 so that the seventh switching tube M7 is turned on, the seventh switching tube M7 pulls down the control end of a thirteenth switching tube M13 to a power ground pin PGND so as to obtain a low level third control signal TD related to the power ground pin PGND, and the gate of the thirteenth switching tube M13 is connected to the low level third control signal TD so that the thirteenth switching tube M13 is turned off; the low-level third control signal TD is connected to the fourteenth switching tube M14 through the fifth inverter A5, so that the fifth inverter A5 inverts the low-level third control signal TD to obtain a high-level control signal, and the high-level control signal pulls up the control end of the fourteenth switching tube M14 to turn on the fourteenth switching tube M14;
at this time, the fourteenth switching tube M14 also pulls down the drain of the tenth switching tube M10, since the second pin voltage of the second pin SWITCH is connected to the gate of the tenth switching tube M10, the second pin voltage of the second pin SWITCH is lower than the first pin voltage of the first pin BOOST, and the source of the tenth switching tube M10 is correspondingly in a high level state when the third control signal TD is in a high level, therefore, the tenth switching tube M10 is turned on, the fourteenth switching tube M14 pulls down the source of the tenth switching tube M10, the source of the tenth switching tube M10 is connected to the gate of the sixteenth switching tube M16, the gate voltage of the sixteenth switching tube M16 is pulled down, so that the sixteenth switching tube M16 is turned on, the sixteenth switching tube M16 pulls up the drain of the ninth switching tube M9 to the first pin voltage of the first pin BOOST, the first pin voltage of the first pin BOOST is at a high level compared with the second pin voltage of the second pin SWITCH, and the source of the ninth SWITCH tube M9 is at a low level when the third control signal TD is at a high level, so that the high voltage of the drain of the ninth SWITCH tube M9 is transmitted to the source of the ninth SWITCH tube M9 through the parasitic diode of the ninth SWITCH tube M9, so that the source of the ninth SWITCH tube M9 is also turned into a high voltage, in addition, the gate of the ninth SWITCH tube M9 is also connected to the second pin voltage of the second pin SWITCH, the second pin voltage of the second pin SWITCH is at a low level compared with the first pin voltage of the first pin SWITCH, the ninth SWITCH tube M9 is turned on, the source voltage of the ninth SWITCH tube M9 is pulled up, and the source of the ninth SWITCH tube M9 is connected to the input terminal of the sixth inverter A6, so that the sixth inverter A6 inputs a high level, outputs a low level signal of the second voltage value, i.e., a low-level second control signal TG related to a first pin voltage of the first pin BOOST and a second pin voltage of the second pin SWITCH;
At this time, the drain of the eleventh switching tube M11 and the gate of the twelfth switching tube M12 are also pulled up to the first pin voltage of the first pin BOOST, the twelfth switching tube M12 is turned on, the source of the tenth switching tube M10 is connected to the drain of the twelfth switching tube M12, the source of the twelfth switching tube M12 is connected to the second pin voltage of the second pin SWITCH, the twelfth switching tube M12 pulls down the source of the tenth switching tube M10 to the second pin voltage of the second pin SWITCH, thereby further reducing the gate voltage of the sixteenth switching tube M16, so that the sixteenth switching tube M16 is reliably turned on, thereby ensuring that the sixth inverter A6 outputs the second control signal TG with a low level, and further improving the reliability of the driving circuit.
In summary, the driving circuit for reducing voltage disturbance according to the present application may convert the first control signal T inside the LED driving chip into a high level signal of a first voltage value or a low level signal of a second voltage value (i.e., convert the first control signal T into a second control signal TG related to the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH), and drive the power SWITCH Q1 in the LED driving chip through the high level signal of the first voltage value or the low level signal of the second voltage value, so that the voltage disturbance generated at the power ground pin PGND is not conducted into the LED driving chip U1, thereby ensuring the safety and stability of LED driving;
According to the power switch tube Q1 in the LED driving chip, the back gates of the switch tubes in the second-stage driving circuit are designed to be connected with the respective source electrodes, so that the situation that the gate-source voltage difference VGS is reduced and the starting voltage VTH is increased is avoided, and therefore, the source voltage of each switch tube in the second-stage driving circuit can be normally reduced to the starting voltage VTH (about 1.2V), and therefore, the driving circuit for reducing the voltage disturbance can rapidly output driving signals and drive the power switch tube Q1 in the LED driving chip; in addition, when the voltage difference between the first pin voltage of the first pin BOOST and the second pin voltage of the second pin SWITCH is reduced to a certain range (about 2.4V), the power SWITCH tube in the LED driving chip U1 can still be driven, so that the reliability of the driving circuit for reducing the voltage disturbance is ensured;
according to the method, the eleventh switching tube M11 and the twelfth switching tube M12 are reasonably arranged as low-voltage switching tubes in the second-stage driving circuit, so that the area of the driving circuit for reducing the voltage disturbance is reduced, and the effect of improving the response speed of the driving circuit for reducing the voltage disturbance is achieved; meanwhile, the isolation islands of the eleventh switching tube M11 and the twelfth switching tube M12 are connected with the first pin voltage with higher voltage, so that the occurrence of electric leakage of the eleventh switching tube M11 and the twelfth switching tube M12 is effectively avoided, and the reliability and the working efficiency of the driving circuit for reducing the voltage disturbance are further improved;
The driving circuit for reducing the voltage disturbance is designed in an LED driving chip U1 in a control circuit of an LED driving power supply, and the LED driving chip U1 comprises a signal grounding pin SGND and a power grounding pin PGND; the LED driving power supply comprises a power circuit except a control circuit, wherein the input end and the output end of the power circuit are grounded and connected to a power grounding pin PGND, the related grounding of the control circuit is grounded and connected to a signal grounding pin SGND, the influence of voltage disturbance on the LED driving power supply can be reduced by the arrangement of the LED driving power supply, the safety and the stability of the LED driving power supply are further improved, in addition, the size of the LED driving power supply can be reduced by the arrangement of the LED driving power supply, and the reliability, the working efficiency and the response speed of the LED driving power supply are improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (12)

1. A drive circuit for reducing voltage disturbances, characterized by; the driving circuit for reducing the voltage disturbance comprises a first-stage driving circuit and a second-stage driving circuit;
in the first stage driving circuit, a first voltage end is connected to a first node through a first switching tube M1; the first node is connected to a signal ground pin SGND through a fifteenth switching tube M15; the first voltage end is connected to a second node through a second switching tube M2; the second node is connected to the signal ground pin SGND through a third switching tube M3; the control end of the first switching tube M1 is connected to a second node; the control end of the second switching tube M2 is connected to the first node; the control end of the fifteenth switching tube M15 is connected with a first control signal, and the control end of the third switching tube M3 is connected with an inverted signal of the first control signal;
the first voltage end is also connected to a third node through a fourth switching tube M4; the third node is connected to a power ground pin PGND through a sixth switching tube M6; the first voltage end is also connected to a fourth node through a fifth switching tube M5; the fourth node is connected to the power ground pin PGND through a seventh switching tube M7; the third node is connected to the control end of the seventh switching tube M7; the fourth node is connected to the control end of the sixth switching tube M6; the level of the control end of the fourth switching tube M4 and the level of the control end of the second switching tube M2 are reversed; the level of the control end of the fifth switching tube M5 and the level of the control end of the first switching tube M1 are reversed;
The input end of the second-stage driving circuit is connected with the fourth node; the grounding end of the second-stage driving circuit is connected to the power grounding pin PGND; when the fourth node is at a high level, the second-stage driving circuit outputs a high-level signal of a first voltage value; when the fourth node is at a low level, the second stage driving circuit outputs a low level signal of a second voltage value;
the high-voltage end of the second-stage driving circuit is connected with the first pin voltage; the low voltage end of the second-stage driving circuit is connected with a second pin voltage;
the first voltage value is related to the first pin voltage; the second voltage value is related to the second pin voltage;
in the second stage driving circuit, the high voltage end is connected to a fifth node through a sixteenth switching tube M16 and a ninth switching tube M9 in sequence; the fifth node is connected to the low voltage terminal through an eleventh switching tube M11;
the high-voltage end is also connected to a sixth node through an eighth switching tube M8 and a tenth switching tube M10 in sequence; the sixth node is connected to the low voltage terminal through a twelfth switching tube M12;
the control end of the sixteenth switching tube M16 and the control end of the eleventh switching tube M11 are connected to the sixth node; the control end of the eighth switching tube M8 and the control end of the twelfth switching tube M12 are connected to the fifth node; the inversion level of the fifth node is the output signal of the second-stage driving circuit;
The high-voltage end is also connected to the power grounding pin PGND through a sixteenth switching tube M16 and a thirteenth switching tube M13 in sequence; the high-voltage end is also connected to the power grounding pin PGND through an eighth switching tube M8 and a fourteenth switching tube M14 in sequence;
the control end of the thirteenth switching tube M13 is connected to the level of the fourth node; the control end of the fourteenth switching tube M14 is connected to the inversion level of the fourth node;
the second pin voltage is connected to the grid electrode of the ninth switching tube M9; the gate of the tenth switch tube M10 is connected to the second pin voltage.
2. The driving circuit for reducing voltage disturbance according to claim 1, wherein the first stage driving circuit further comprises a first inverter A1, a second inverter A2, a third inverter A3, and a fourth inverter A4;
the first control signal is connected with the control end of the third switching tube M3 through a first inverter A1;
the first control signal is connected to the control end of the fifteenth switching tube M15 through a first inverter A1 and a second inverter A2 in sequence;
the first node is connected to the control end of the fourth switching tube M4 through the third inverter A3;
The second node is connected to the control terminal of the fifth switching tube M5 through the fourth inverter A4.
3. The driving circuit for reducing voltage disturbance according to claim 2, wherein positive power supply terminals of the first inverter A1, the second inverter A2, the third inverter A3 and the fourth inverter A4 are respectively connected to the first voltage terminal, and negative power supply terminals are respectively connected to the signal ground pin SGND.
4. A driving circuit for reducing voltage disturbance according to any one of claims 1-3, wherein the first switching tube M1, the second switching tube M2, the fourth switching tube M4 and the fifth switching tube M5 are PMOS tubes, respectively; the third switching tube M3, the sixth switching tube M6, the seventh switching tube M7, and the fifteenth switching tube M15 are NMOS tubes respectively;
or, the first switching tube M1, the second switching tube M2, the fourth switching tube M4 and the fifth switching tube M5 are PNP transistors respectively; the third switching tube M3, the sixth switching tube M6, the seventh switching tube M7, and the fifteenth switching tube M15 are NPN transistors, respectively.
5. The driving circuit for reducing voltage disturbance according to claim 1, wherein the second stage driving circuit further comprises a fifth inverter A5 and a sixth inverter A6;
The fourth node is connected to the control end of the fourteenth switching tube M14 through the fifth inverter A5;
the fifth node outputs a high level signal of a first voltage value or a low level signal of a second voltage value through the sixth inverter A6.
6. The voltage disturbance reducing driving circuit according to claim 5, wherein a positive power supply terminal of the fifth inverter A5 is connected to the first voltage terminal, and a negative power supply terminal is connected to the power ground pin PGND.
7. The voltage disturbance reducing driving circuit according to claim 5, wherein a positive power supply terminal of the sixth inverter A6 is connected to the first pin voltage, and a negative power supply terminal is connected to the second pin voltage.
8. The driving circuit for reducing voltage disturbance according to any one of claims 5 to 7, wherein in the second stage driving circuit, the eighth switching tube M8 to the tenth switching tube M10, and the sixteenth switching tube M16 are high-voltage PMOS tubes;
the eleventh switching tube M11 and the twelfth switching tube M12 are isolated NMOS tubes;
the thirteenth switching tube M13 and the fourteenth switching tube M14 are high-voltage NMOS tubes.
9. The driving circuit for reducing voltage disturbance according to claim 8, wherein the eleventh switching tube M11 and the twelfth switching tube M12 are low-voltage NMOS tubes including isolation islands, and the isolation islands of the eleventh switching tube M11 and the twelfth switching tube M12 are connected to the first pin voltage.
10. The driving circuit for reducing voltage disturbance according to claim 8, wherein the back gates of the eighth switching transistor M8 to the fourteenth switching transistor M14 and the sixteenth switching transistor M16 are connected to respective sources.
11. An LED driving chip, comprising a signal ground pin SGND, a power ground pin PGND, and a driving circuit for reducing voltage disturbance according to any one of claims 1 to 10.
12. An LED driving power supply is characterized by comprising a control circuit; the control circuit includes the LED driving chip as claimed in claim 11.
CN202310301235.3A 2023-03-27 2023-03-27 Drive circuit for reducing voltage disturbance Active CN116075012B (en)

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Citations (1)

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Publication number Priority date Publication date Assignee Title
CN107846759A (en) * 2017-12-12 2018-03-27 上海灿瑞科技股份有限公司 A kind of LED drive chip

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CN203788505U (en) * 2013-12-30 2014-08-20 湖南信息科学职业学院 Multi-loop control-based Buck-Boost semiconductor lighting drive circuit
CN104470082A (en) * 2014-11-22 2015-03-25 成都智利达科技有限公司 In-phase alternating current signal amplification type optical excitation grid drive circuit

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Publication number Priority date Publication date Assignee Title
CN107846759A (en) * 2017-12-12 2018-03-27 上海灿瑞科技股份有限公司 A kind of LED drive chip

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