CN212992206U - Continuous bootstrap booster circuit and device - Google Patents
Continuous bootstrap booster circuit and device Download PDFInfo
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- CN212992206U CN212992206U CN202021583842.1U CN202021583842U CN212992206U CN 212992206 U CN212992206 U CN 212992206U CN 202021583842 U CN202021583842 U CN 202021583842U CN 212992206 U CN212992206 U CN 212992206U
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Abstract
The utility model is suitable for an electronic circuit technical field provides a last bootstrap boost circuit and device, and the circuit includes: the input end of the PWM control module is connected with the PWM signal and used for outputting a voltage pulse signal; the boost maintaining module is connected with the output end of the PWM control module and used for receiving a voltage pulse signal and superposing the voltage pulse signal to the bootstrap capacitor Cr; one end of the switch control module is connected with one end of the bootstrap capacitor Cr, and the other end of the switch control module is connected with the grid electrode of the NMOS tube. The embodiment outputs a voltage pulse signal through the PWM signal function and the PWM control module, the voltage boosting and maintaining module receives the voltage pulse signal and then superposes the voltage pulse signal on the bootstrap capacitor Cr, so that the bootstrap capacitor Cr is maintained at a stable voltage, and the switch control module is connected with the gates of the bootstrap capacitor Cr and the NMOS tube, so that the continuous conduction of the NMOS tube is realized.
Description
Technical Field
The utility model belongs to the technical field of the electronic circuit, especially, relate to a last bootstrap boost circuit and device.
Background
Switching power supplies and power supplies are widely used in appliances, computers, communication control, aviation, medical treatment, and the like. At present, the development of electronic and communication technologies has higher and higher requirements on power supplies, and a switching device of an MOS transistor is the most widely applied and most core part of a power supply system, but a driving circuit of the MOS transistor is stable and reliable and is the dominant part in the core of the switching device of the MOS transistor.
PMOSFETs are mostly used as switches of the plus end in the market for control, the driving is simple, but the PMOS has large on-resistance, large power consumption and large heat productivity; the NMOS on resistance is small, and the power consumption and the heat productivity can be reduced by using the NMOS as a switch control of the plus end; at present, for most of NMOS tube driving circuits, a special driving IC (e.g. IRF2110) is basically used to suspend the gate (G) of the NMOS tube above the source (S) to drive the NMOS tube to turn on and off, and this method needs to provide a stable operating power supply for the driving IC and a peripheral auxiliary circuit to basically implement the driving of the NMOS tube.
SUMMERY OF THE UTILITY MODEL
The utility model provides a last bootstrap boost circuit aims at solving the problem that the drive NMOS pipe lasts to switch on.
The utility model discloses a realize like this, a last bootstrap boost circuit, include:
the input end of the PWM control module is connected with the PWM signal and used for outputting a voltage pulse signal;
the boost maintaining module is connected with the output end of the PWM control module and used for receiving the voltage pulse signal and superposing the voltage pulse signal to the bootstrap capacitor Cr;
and one end of the switch control module is connected with one end of the bootstrap capacitor Cr, and the other end of the switch control module is connected with the grid electrode of the NMOS tube Q4.
Furthermore, the PWM control module includes a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2 and a third transistor Q3, wherein one end of the first resistor R1 is connected to the first voltage terminal VCC, the other end of the first resistor R1 is connected to the base of the first transistor Q1 through the second resistor R2, the other end of the first resistor R1 is further connected to the base of the second transistor Q2 through the third resistor R3, the emitter of the first transistor Q1 is connected to the first voltage terminal VCC, the collector of the first transistor Q1 is connected to the collector of the second transistor Q2, the emitter of the second transistor Q2 is grounded, the other end of the first resistor R1 is further connected to the collector of the third transistor Q3, the base of the third transistor Q3 is connected to the PWM signal, and the emitter of the third transistor Q3 is grounded.
Furthermore, the PWM control module further includes a fourth resistor R4 and a fifth resistor R5, the base of the third transistor Q3 is connected to the PWM signal through the fourth resistor R4, and the base and the emitter of the third transistor Q3 are connected through the fifth resistor R5.
Furthermore, the boost maintaining module includes a sixth resistor R6, a first diode D1, a second diode D2, a third diode D3, and a first capacitor C1, one end of a bootstrap capacitor Cr is connected to the cathode of the first diode D1, the anode of the first diode D1 is connected to the first voltage terminal VCC, the other end of the bootstrap capacitor Cr is grounded through the sixth resistor R6, one end of the bootstrap capacitor Cr is further connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the collector of the first transistor Q1, the other end of the bootstrap capacitor Cr is further connected to the anode of the third diode D3, and the cathode of the third diode D3 is connected to the anode of the second diode D2.
Furthermore, the boost maintaining module further comprises a seventh resistor R7 and an eighth resistor R8, the seventh resistor R7 is connected in series on a line between the first capacitor C1 and the collector of the first transistor Q1, and the eighth resistor R8 is connected in parallel with the first capacitor C1.
Furthermore, the switch control block further includes a ninth resistor R9, a tenth resistor R10, and a first zener diode D4, wherein one end of the switch control module away from the bootstrap capacitor Cr is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the gate of the NMOS transistor Q4, the other end of the bootstrap capacitor Cr is connected to the source of the NMOS transistor Q4, the other end of the bootstrap capacitor Cr is connected to the anode of the first zener diode D4, the cathode of the first zener diode D4 is connected to the gate of the NMOS transistor Q4, and the tenth resistor R10 is connected in parallel to the first zener diode D4.
In a second aspect, the present application further provides a bootstrap voltage boosting apparatus, including an NMOS transistor Q4 and the above continuous bootstrap voltage boosting circuit, where a switch control module of the continuous bootstrap voltage boosting circuit is connected to a gate of the NMOS transistor Q4.
The embodiment of the utility model provides a because through PWM signal effect and PWM control module output voltage pulse signal, it keeps module to add to bootstrap electric capacity Cr to step up after receiving voltage pulse signal, so make bootstrap electric capacity Cr maintain a stable voltage, switch control module connects the grid of bootstrap electric capacity Cr and NMOS pipe Q4, thereby realize that lasting of NMOS pipe Q4 switches on.
Drawings
Fig. 1 is a schematic block diagram of a sustained bootstrap booster circuit provided by the present invention;
fig. 2 is a schematic diagram of a specific circuit structure of an embodiment of the sustained bootstrap boost circuit provided in the present invention;
fig. 3 is a schematic diagram of a specific circuit structure of another embodiment of the sustained bootstrap boost circuit provided in the present invention;
fig. 4 is a schematic diagram of a specific circuit structure of still another embodiment of the sustained bootstrap boost circuit provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Through PWM signal effect and PWM control module output voltage pulse signal, superpose to bootstrap capacitor Cr behind the voltage pulse signal is received to the maintenance module that steps up for bootstrap capacitor Cr maintains a stable voltage, and switch control module connects bootstrap capacitor Cr and NMOS pipe Q4's grid, thereby realizes that lasting of NMOS pipe Q4 switches on.
Example one
In some alternative embodiments, please refer to fig. 1, in which fig. 1 is a block diagram illustrating a continuous bootstrap boost circuit according to an embodiment of the present application.
As shown in fig. 1, the present application provides a continuous bootstrap boost circuit, which includes a PWM control module 1, a boost hold module 2, and a switch control module 3.
The input end of the PWM control module 1 is connected with the PWM signal and used for outputting a voltage pulse signal; the boost maintaining module 2 is connected with the output end of the PWM control module 1 and used for receiving a voltage pulse signal and superposing the voltage pulse signal to the bootstrap capacitor Cr; one end of the switch control module 3 is connected to one end of the bootstrap capacitor Cr, and the other end of the switch control module 3 is connected to the gate of the NMOS transistor Q4.
In the implementation, the MOS is called Metal-Oxide-Semiconductor field effect transistor (MOS-Semiconductor), and the MOS includes an NMOS transistor and a PMOS transistor, where the NMOS transistor is an N-type field effect transistor (N channel) and the PMOS transistor is a P-type field effect transistor (P channel). The PWM signal is a PWM Pulse signal, and PWM (Pulse Width Modulation) modulates the bias of the transistor base or the MOS transistor gate according to the change of the corresponding load to change the conduction time of the transistor or the MOS transistor, thereby changing the output of the switching regulator. The PWM control module 1 generates a voltage pulse signal after receiving the PWM signal and outputs the voltage pulse signal to the boost holding module 2, the boost holding module 2 superimposes a voltage on the bootstrap capacitor Cr according to the voltage pulse signal, so that the bootstrap capacitor Cr is maintained at a relatively stable voltage, two ends of the switch control module 3 are respectively connected with the bootstrap capacitor Cr and a grid electrode of the NMOS tube Q4, and the bootstrap capacitor Cr continuously conducts the NMOS tube Q4, thereby realizing the bootstrap function.
Example two
In some alternative embodiments, please refer to fig. 2, fig. 2 is a schematic circuit diagram of an embodiment of a sustained bootstrap boost circuit according to the present application.
As shown in fig. 2, the PWM control module 1 includes a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2 and a third transistor Q3, wherein one end of the first resistor R1 is connected to the first voltage terminal VCC, the other end of the first resistor R1 is connected to the base of the first transistor Q1 through the second resistor R2, the other end of the first resistor R1 is further connected to the base of the second transistor Q2 through the third resistor R3, the emitter of the first transistor Q1 is connected to the first voltage terminal VCC, the collector of the first transistor Q1 is connected to the collector of the second transistor Q2, the emitter of the second transistor Q2 is grounded, the other end of the first resistor R1 is further connected to the collector of the third transistor Q3, the base of the third transistor Q3 is connected to the PWM signal, and the emitter of the third transistor Q3 is grounded.
The boost holding module 2 comprises a sixth resistor R6, a first diode D1, a second diode D2, a third diode D3 and a first capacitor C1, wherein one end of a bootstrap capacitor Cr is connected to the cathode of the first diode D1, the anode of the first diode D1 is connected to the first voltage terminal VCC, the other end of the bootstrap capacitor Cr is grounded through the sixth resistor R6, one end of the bootstrap capacitor Cr is further connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the collector of the first triode Q1, the other end of the bootstrap capacitor Cr is further connected to the anode of the third diode D3, and the cathode of the third diode D3 is connected to the anode of the second diode D2.
In implementation, the switch control module 3 employs a switch S1, one end of the switch S1 is connected to one end of a bootstrap capacitor Cr close to the first diode D1, the other end of the switch S1 is connected to a gate of an NMOS transistor Q4, one end of the bootstrap capacitor Cr close to a sixth resistor R6 is connected to a source of an NMOS transistor Q4, wherein a PWM pulse signal controls on and off of a third transistor Q3, and further controls on and off of a first transistor Q1 and a second transistor Q2 through the third transistor Q3, a left side voltage of the first capacitor C1 is controlled by the first transistor Q1 and the second transistor Q2, S1 controls on and off of a line between the NMOS transistor Q4 and the bootstrap capacitor Cr, the first voltage terminal VCC is a supply voltage of the circuit, the bootstrap capacitor Cr stores energy from the first voltage terminal VCC through the first diode D1 and the sixth resistor R6, a left side voltage of the first capacitor C1 is controlled by the PWM pulse signal, and the first voltage VCC is an example of a first voltage V12, the voltage pulse of the voltage 0V-12V at the left side of the first capacitor C1 jumps; the switch S1 is closed, the grid voltage of the NMOS tube Q4 starts to rise from 0V to reach Vgsth of the NMOS tube, Vgsth is the NMOS tube starting voltage, the NMOS tube Q4 starts to be conducted, the voltage of Vds becomes small, D represents the drain electrode of the MOS tube, S represents the source electrode of the MOS tube, G represents the grid electrode of the MOS tube, Vds is the drain-source voltage of the NMOS tube, the source electrode voltage of the NMOS tube Q4 rises, the voltage of a bootstrap capacitor Cr rises (bootstrap capacitor), the voltage of Vgs (grid-source electrode) of the NMOS tube Q4 continues to rise, the NMOS tube Q4 is completely opened, the drain electrode of the NMOS tube Q4 is connected with an external voltage end BAT +, and the source electrode voltage of the NMOS tube Q4 is close to BAT + voltage; limited by the capacity of the bootstrap capacitor Cr, the NMOS transistor Q4 cannot be kept on for a long time by the bootstrap capacitor Cr alone, and the Vgs voltage of the NMOS transistor Q4 is reduced; the source voltage Vpack + of the NMOS transistor Q4 continuously charges the first capacitor C1 through the third diode D3, and the voltage on the left side of the first capacitor C1 changes in a pulse manner, so that the voltage on the right side of the first capacitor C1 rises to approximately 10v and the bootstrap capacitor Cr is continuously charged through the second diode D2, so that the two ends of the bootstrap capacitor Cr are maintained at a relatively stable voltage, the Vgs voltage of the NMOS transistor Q4 does not continuously decrease, and the NMOS transistor Q4 is continuously turned on.
In some embodiments, as shown in fig. 4, the first transistor Q1 may also be an NPN transistor, the second transistor Q2 may also be a PNP transistor, and in some embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 may also be MOS transistors, which can control the voltage pulse jump on the left side of the first capacitor C1 through a PWM signal.
EXAMPLE III
In some alternative embodiments, please refer to fig. 3, fig. 3 is a schematic circuit diagram of a specific circuit structure of another embodiment of the sustained bootstrap boost circuit of the present application.
As shown in fig. 3, the PWM control module 1 further includes a fourth resistor R4 and a fifth resistor R5, wherein the base of the third transistor Q3 is connected to the PWM signal through the fourth resistor R4, and the base and the emitter of the third transistor Q3 are connected through the fifth resistor R5. The boost maintaining module 2 further comprises a seventh resistor R7 and an eighth resistor R8, the seventh resistor R7 is connected in series on a line between the first capacitor C1 and the collector of the first triode Q1, and the eighth resistor R8 is connected in parallel with the first capacitor C1. The switch control module 3 further includes a ninth resistor R9, a tenth resistor R10 and a first zener diode D4, one end of the switch control module 3 is connected to the bootstrap capacitor Cr, the other end of the switch control module 3, which is far away from the bootstrap capacitor Cr, is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the gate of the NMOS transistor Q4, the other end of the bootstrap capacitor Cr is connected to the source of the NMOS transistor Q4, the other end of the bootstrap capacitor Cr is connected to the anode of the first zener diode D4, the cathode of the first zener diode D4 is connected to the gate of the NMOS transistor Q4, and the tenth resistor R10 is connected to the first zener diode D4 in parallel.
In implementation, the fourth resistor R4, the fifth resistor R5, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 can limit the current of the circuit and protect the circuit, and the first zener diode D4 can maintain the Vgs voltage of the NMOS transistor Q4 at a relatively stable voltage, so as to prevent the Vgs voltage from exceeding the limit voltage and protect the NMOS transistor Q4.
Example four
In some optional embodiments, based on the same inventive concept, the present application further provides a bootstrap voltage boosting apparatus, including an NMOS transistor Q4 and the above continuous bootstrap voltage boosting circuit, where the switch control module 3 of the continuous bootstrap voltage boosting circuit is connected to the gate of the NMOS transistor Q4.
In this embodiment, the bootstrap voltage boosting device includes an NMOS transistor Q4 and a continuous bootstrap voltage boosting circuit, the PWM signal in the continuous bootstrap voltage boosting circuit acts on and outputs a voltage pulse signal from the PWM control module 1, the voltage boosting and maintaining module 2 receives the voltage pulse signal and then superposes on the bootstrap capacitor Cr, so that the bootstrap capacitor Cr is maintained at a stable voltage, the switch control module 3 connects the gates of the bootstrap capacitor Cr and the NMOS transistor Q4, and the voltage output from the bootstrap capacitor Cr to the gate of the NMOS transistor Q4 realizes the continuous conduction of the NMOS transistor Q4.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. A continuous bootstrap boost circuit, comprising:
the input end of the PWM control module is connected with the PWM signal and used for outputting a voltage pulse signal;
the boost maintaining module is connected with the output end of the PWM control module and used for receiving the voltage pulse signal and superposing the voltage pulse signal to a bootstrap capacitor Cr;
and one end of the switch control module is connected with one end of the bootstrap capacitor Cr, and the other end of the switch control module is connected with the grid electrode of the NMOS tube Q4.
2. The persistent bootstrap boost circuit as claimed in claim 1, wherein the PWM control module includes a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2 and a third transistor Q3, one end of the first resistor R1 is connected to a first voltage terminal VCC, the other end of the first resistor R1 is connected to the base of the first transistor Q1 through the second resistor R2, the other end of the first resistor R1 is further connected to the base of the second transistor Q2 through the third resistor R3, the emitter of the first transistor Q1 is connected to the first voltage terminal VCC, the collector of the first transistor Q1 is connected to the collector of the second transistor Q2, the emitter of the second transistor Q2 is grounded, the other end of the first resistor R1 is further connected to the collector of the third transistor Q3, the base of the third transistor Q3 is connected to the PWM signal, and the emitter of the third transistor Q3 is grounded.
3. The continuous bootstrap boost circuit as recited in claim 2, wherein said PWM control module further includes a fourth resistor R4 and a fifth resistor R5, a base of said third transistor Q3 is connected to said PWM signal through said fourth resistor R4, and a base and an emitter of said third transistor Q3 are connected through said fifth resistor R5.
4. The continuous bootstrap boost circuit of claim 2, characterized in that, the boost hold module includes a sixth resistor R6, a first diode D1, a second diode D2, a third diode D3 and a first capacitor C1, one end of the bootstrap capacitor Cr is connected to the cathode of the first diode D1, the anode of the first diode D1 is connected to the first voltage terminal VCC, the other end of the bootstrap capacitor Cr is grounded through the sixth resistor R6, one end of the bootstrap capacitor Cr is further connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the collector of the first transistor Q1, the other end of the bootstrap capacitor Cr is further connected to an anode of the third diode D3, and a cathode of the third diode D3 is connected to an anode of the second diode D2.
5. The continuous bootstrap boost circuit as recited in claim 4, wherein said boost hold module further comprises a seventh resistor R7 and an eighth resistor R8, said seventh resistor R7 being connected in series on the line between said first capacitor C1 and the collector of said first transistor Q1, said eighth resistor R8 being connected in parallel with said first capacitor C1.
6. The continuous bootstrap voltage boosting circuit as recited in claim 4, wherein said switch control module further includes a ninth resistor R9, a tenth resistor R10 and a first voltage-stabilizing diode D4, one end of said switch control module far from said bootstrap capacitor Cr is connected to one end of said ninth resistor R9, the other end of said ninth resistor R9 is connected to the gate of said NMOS transistor Q4, the other end of said bootstrap capacitor Cr is connected to the source of said NMOS transistor Q4, the other end of said bootstrap capacitor Cr is connected to the anode of said first voltage-stabilizing diode D4, the cathode of said first voltage-stabilizing diode D4 is connected to the gate of said NMOS transistor Q4, and said tenth resistor R10 is connected in parallel to said first voltage-stabilizing diode D4.
7. A bootstrap voltage boosting device, comprising an NMOS transistor Q4 and the continuous bootstrap voltage boosting circuit as claimed in any one of claims 1 to 6, wherein the switch control module of the continuous bootstrap voltage boosting circuit is connected with the gate of the NMOS transistor Q4.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021583842.1U CN212992206U (en) | 2020-08-03 | 2020-08-03 | Continuous bootstrap booster circuit and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021583842.1U CN212992206U (en) | 2020-08-03 | 2020-08-03 | Continuous bootstrap booster circuit and device |
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| CN212992206U true CN212992206U (en) | 2021-04-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113452244A (en) * | 2021-06-25 | 2021-09-28 | 山东航天电子技术研究所 | LCL distribution control circuit |
| CN113538882A (en) * | 2021-07-16 | 2021-10-22 | 上海爻火微电子有限公司 | Signal transmission circuit and electronic equipment |
-
2020
- 2020-08-03 CN CN202021583842.1U patent/CN212992206U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113452244A (en) * | 2021-06-25 | 2021-09-28 | 山东航天电子技术研究所 | LCL distribution control circuit |
| CN113538882A (en) * | 2021-07-16 | 2021-10-22 | 上海爻火微电子有限公司 | Signal transmission circuit and electronic equipment |
| CN113538882B (en) * | 2021-07-16 | 2022-12-13 | 上海爻火微电子有限公司 | Signal transmission circuit and electronic equipment |
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