CN117040512B

CN117040512B - Driving circuit of depletion transistor

Info

Publication number: CN117040512B
Application number: CN202311302481.7A
Authority: CN
Inventors: 钟海峰; 刘志宏; 黎子兰
Original assignee: Guangdong Zhineng Technology Co Ltd
Current assignee: Guangdong Zhineng Technology Co Ltd
Priority date: 2023-10-10
Filing date: 2023-10-10
Publication date: 2024-02-06
Anticipated expiration: 2043-10-10
Also published as: CN117040512A

Abstract

The application provides a drive circuit of a depletion transistor, comprising: a MOSFET cascaded with the depletion transistor; the switch control module is respectively connected with a first node, a second node and a grid electrode of the MOSFET, wherein the first node is arranged between the MOSFET and the depletion transistor, and the second node is an output end of the driving circuit; wherein the gate of the depletion transistor is connected to the second node and is configured to be turned on or off by a control signal output from the driving circuit, and the switch control module is configured to control the MOSFET to be continuously turned on during operation of the depletion transistor. Through this application, can realize the direct drive to depletion type transistor to and effectively reduce the switching loss, can also avoid taking place to introduce extra loss because of MOS avalanche breakdown, perhaps the vibration inefficacy problem that the electric capacity mismatch leads to.

Description

Driving circuit of depletion transistor

Technical Field

The present disclosure relates to semiconductor driving technology, and in particular, to a driving circuit for a depletion transistor.

Background

The semiconductor device prepared by using the third generation semiconductor material, namely the wide bandgap semiconductor material gallium nitride (GaN) has the advantages of higher working voltage, higher switching frequency, lower on-resistance and the like, is compatible with the silicon-based semiconductor integrated circuit process with extremely low cost and extremely high technical maturity, and has great development potential in the fields of new generation high-frequency and small-size power conversion and management systems, electric locomotives, industrial motors and the like.

Gallium nitride power devices are generally classified into depletion type (normally on type) and enhancement type (normally off type). The enhancement type device has a narrow driving voltage range, is generally driven by a special driving IC, is limited in application due to weaker channel current, has strong current capability and high reliability, has lower dynamic on-resistance, and is turned off by negative pressure.

Currently, gallium nitride depletion mode devices are commonly cascaded with an N-channel low voltage MOSFET to form a cascode normally-off device, as shown in fig. 1.

In the cascade type gallium nitride device with the common source and the common gate, the grid electrode of the depletion type gallium nitride HEMT device K1 is connected with the source electrode of the low-voltage MOSFET K2, and the on-off of the whole cascade device can be controlled by driving the on-off of the low-voltage MOSFET K2. However, this structure has the following problems:

(1) In the cascode structure, the gate of the GaN HEMT is directly connected to the source of the low-voltage MOSFET, and the driving device is a silicon MOS device rather than a direct driving HEMT device, which results in failure to control the switching slew rate of the cascode device, and is prone to cause system EMI problems.

(2) When the drive cascode device is turned off, the gate-source capacitance of the HEMT is connected in parallel with the drain-source capacitance of the MOS, and the two capacitances must be charged to the threshold voltage of the HEMT, so the device has a higher combined Coss. Meanwhile, because the current for charging the capacitor comes from the device, compared with a low-voltage driving power supply loop for charging the gate and the source of the HEMT, the power consumption is larger, and the charging is more obvious under a high-frequency switch.

(3) Devices of the cascode structure still have reverse recovery problems. When the third quadrant is conducted, the body diode of the low-voltage MOSFET is conducted, and current for overcoming reverse recovery charge is provided by a high-voltage power supply in the system, so that system loss is increased.

(4) The low-voltage MOSFET and gallium nitride HEMT junction capacitor are difficult to match, the MOSFET avalanche breakdown can be caused when the low-voltage MOSFET and gallium nitride HEMT junction capacitor are improperly matched, extra switching loss is introduced, midpoint voltage oscillation can be caused under special working conditions, and the device can be disabled seriously.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide at least a driving circuit of a depletion transistor to overcome at least one of the above-mentioned drawbacks.

In a first aspect, exemplary embodiments of the present application provide a driving circuit of a depletion transistor, including: a MOSFET cascaded with the depletion transistor; the switch control module is respectively connected with a first node, a second node and a grid electrode of the MOSFET, wherein the first node is arranged between the MOSFET and the depletion transistor, and the second node is an output end of the driving circuit; a first diode, the anode of which is connected to the grid of the depletion transistor, and the cathode of which is connected to the drain of the MOSFET; wherein the gate of the depletion transistor is connected to the second node and is configured to be turned on or off by a control signal output from the driving circuit, and the switch control module is configured to control the MOSFET to be continuously turned on during operation of the depletion transistor.

In one possible embodiment, the operation period of the depletion transistor includes a stage in which the driving circuit is activated to output a control signal.

In one possible embodiment, the MOSFET includes a P-type MOSFET having a source connected to a source of the depletion transistor, and the first node is a source of the P-type MOSFET, wherein the switch control module includes: and the energy storage sub-circuit is respectively connected with a third node and a fourth node, the third node is arranged between the power supply and the first node, the fourth node is arranged between the output end of the driving circuit and the grid electrode of the MOSFET and is used for storing energy and providing high level for the fourth node to control the MOSFET to conduct when the second node is at a high level, and the energy stored by the energy storage sub-circuit is released when the second node is at a low level to provide high level for the fourth node to maintain the MOSFET to conduct.

In one possible implementation, the switch control module further includes: and a clamping sub-circuit connected to the third node and the fourth node, respectively, and configured to clamp voltages at the third node and the fourth node to turn off the MOSFET when there is no control signal at the second node.

In one possible embodiment, the clamp sub-circuit includes a clamp resistor, and the tank sub-circuit includes a tank capacitor configured to discharge through the clamp resistor to provide a high level to the fourth node when the second node is low, wherein the discharge time is less than the duration of the low level.

In one possible implementation, the switch control module further includes: and an auxiliary control sub-circuit connected to the second node and the fourth node, respectively, and configured to supply a high level to the fourth node when the second node is at a high level, and to supply a low level to the fourth node when the second node is at a low level.

In one possible implementation, the auxiliary control sub-circuit includes: the first voltage dividing resistor is respectively connected with the second node and the fifth node; the second voltage dividing resistor is connected with the fifth node and the ground respectively; and the base electrode of the triode is connected to the fifth node, the emitter electrode of the triode is grounded, and the collector electrode of the triode is connected to the fourth node.

In one possible implementation, the auxiliary control sub-circuit further comprises: and the current limiting resistor is arranged between the collector electrode of the triode and the fourth node.

In one possible implementation, the driving circuit further includes: and the anode of the second diode is connected to the power supply, and the cathode of the second diode is connected to the third node.

In one possible implementation, the driving circuit further includes: and the switching regulator sub-circuit is arranged between the second node and the grid electrode of the depletion type transistor so as to regulate the switching speed of the depletion type transistor.

In one possible implementation, the driving circuit further includes: and a reverse path connected with the drain of the depletion transistor and the drain of the P-type MOSFET respectively.

In one possible implementation, the P-type MOSFET and the depletion transistor are packaged as a normally-off switching device, the driving circuit, the energy storage sub-circuit, the clamping sub-circuit, the auxiliary control sub-circuit and the switching regulator sub-circuit are packaged as a driving chip for the normally-off switching device, wherein the drain electrode of the depletion transistor is used as the drain electrode of the normally-off switching device, the source electrode of the depletion transistor is connected with the source electrode of the P-type MOSFET, and the drain electrode of the P-type MOSFET is used as the source electrode of the normally-off switching device; or the P-type MOSFET and the depletion transistor are packaged into a normally-closed switching device, the driving circuit and the auxiliary control subcircuit are packaged into a driving chip aiming at the normally-closed switching device, and the energy storage subcircuit, the clamping subcircuit and the switching regulation subcircuit are led out and connected outside the package; or the energy storage sub-circuit, the clamping sub-circuit, the auxiliary control sub-circuit, the P-type MOSFET and the depletion type transistor are packaged into a depletion type power device, and the driving circuit and the switching regulator sub-circuit are packaged into a driving chip for the depletion type power device; alternatively, all devices are packaged as a power device.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a schematic diagram of a cascode gallium nitride structure;

fig. 2 shows one of schematic diagrams of a driving circuit of a depletion transistor provided in an exemplary embodiment of the present application;

FIG. 3 illustrates a second schematic diagram of a drive circuit for a depletion transistor provided in an exemplary embodiment of the present application;

FIG. 4 illustrates a third schematic diagram of a drive circuit for a depletion transistor provided in an exemplary embodiment of the present application;

fig. 5 shows a fourth schematic diagram of a drive circuit for a depletion transistor provided in an exemplary embodiment of the present application;

fig. 6 shows a fifth schematic diagram of a drive circuit for a depletion transistor provided in an exemplary embodiment of the present application;

fig. 7 shows a schematic diagram of a driving circuit of a depletion transistor provided in an exemplary embodiment of the present application;

FIG. 8 illustrates one of the package form schematics provided by the exemplary embodiments of the present application;

FIG. 9 illustrates one of the package form schematics provided by the exemplary embodiments of the present application;

FIG. 10 illustrates one of the package form schematics provided by the exemplary embodiments of the present application;

fig. 11 shows a schematic diagram of a driving circuit of a depletion transistor according to an exemplary embodiment of the present application;

fig. 12 shows one of simulation results of a driving circuit of a depletion transistor provided in an exemplary embodiment of the present application;

fig. 13 shows a second simulation result of the driving circuit of the depletion transistor provided in the exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be appreciated that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.

The terms "a," "an," "the," and "said" are used in this specification to denote the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second" and the like are used merely as labels, and are not intended to limit the number of their objects.

It should be understood that in embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or" is merely an association relationship describing an association object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. "comprising A, B and/or C" means comprising any 1 or any 2 or 3 of A, B, C.

It should be understood that in the embodiments of the present application, "B corresponding to a", "a corresponding to B", or "B corresponding to a", means that B is associated with a, from which B may be determined. Determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.

In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.

Gallium nitride (GaN) power devices are generally classified into depletion type (normally open type) and enhancement type (normally closed type). The enhancement device has a narrow driving voltage range, is generally driven by a special driving IC, is limited in application due to weak channel current, has strong current capability and high reliability, has lower dynamic on-resistance, and needs to be turned off by negative pressure.

In view of at least one of the above problems, the present application proposes a driving circuit of a depletion transistor, in which the depletion transistor performs a switching operation along with a driving level change, and an additional enable signal is not required to drive a MOSFET to conduct, and only one driving input signal is required for a device.

In order to facilitate understanding of the present application, the structure and the operation principle of the driving circuit of the depletion transistor provided in the embodiments of the present application are described in detail below.

Fig. 2 shows one of schematic diagrams of a driving circuit of a depletion transistor provided in an exemplary embodiment of the present application.

As shown in fig. 2, the driving circuit includes a MOSFET (metal-oxide semiconductor field effect transistor) Q2, which is cascaded with a depletion transistor Q1.

By way of example, the depletion mode transistor Q1 may include, but is not limited to, a gallium nitride transistor (GaN HEMT), or a silicon carbide transistor (SiC HEMT). MOSFET tube Q2 may include, but is not limited to, an enhancement, P-type MOSFET.

The switch control module 10 is respectively connected to the first node P1, the second node P2 and the gate of the MOSFET Q2, where the first node P1 is between the MOSFET Q2 and the depletion transistor Q1, i.e. is the source of the P-type MOSFET, and the second node P2 is the output of the driving circuit 20.

The depletion transistor Q1 is connected in series with the MOSFET Q2, the Source of the depletion transistor Q1 is connected with the Source of the MOSFET Q2, the Drain of the Q1 is used as the Drain Drain of the whole device, and the Drain of the MOSFET Q2 is used as the Source of the whole device.

MOSFET Q2 is cascaded with depletion transistor Q1 to form a normally-off switching device. Specifically, the switch control module 10 is connected in parallel to the gate and the source of the MOSFET Q2, and when the second node P2 is at a low level or has no output signal, the voltage provided to the gate of the MOSFET Q2 is similar to the voltage provided to the first node P1, that is, the gate-source voltage of the MOSFET Q2 is less than the threshold voltage, and the MOSFET Q2 is in an off state. In this way, it is achieved that the MOSFET transistor Q2 is in an off-state without an external driving power source, thereby ensuring that the entire device is in a normally off state (off/non-conducting).

In the exemplary embodiment of the present application, the driving circuit further includes a first diode D1, an anode of the first diode D1 is connected to the gate of the depletion transistor Q1, and a sixth node P6 is shown in the figure, the sixth node P6 is between the second node P2 and the gate of the depletion transistor Q1, and a cathode of the first diode D1 is connected to the drain of the MOSFET transistor Q2. The gate of the depletion transistor Q1 is connected to the drain of the MOSFET Q2, i.e. the source of the entire device, through a diode D1.

The first diode D1 clamps the gate voltage of the depletion transistor Q1 to about 0V, so as to maintain the whole device in an off state when no driving power supply (Vdd, vss) is supplied and no driving signal is generated.

The switch control module 10 is configured to control the MOSFET to be continuously turned on during operation of the depletion transistor Q1, and illustratively, includes a phase in which the drive circuit 20 is activated, outputting a control signal, during operation of the depletion transistor Q1.

Specifically, when the second node P2 is at a high level, the voltage supplied to the gate of the MOSFET Q2 and the voltage supplied to the first node P1 are controlled, i.e., the gate-source voltage of the MOSFET Q2 is made greater than the threshold voltage, the MOSFET Q2 is controlled to be turned on, and after the first turn-on, the MOSFET Q2 is maintained in the turned-on state. When the drive circuit 20 stops outputting the signal, the MOSFET transistor Q2 is controlled to be turned off.

That is, the switching control module 10 is influenced by the output of the driving circuit 20, controls the MOSFET transistor Q2 to be turned on when the control signal output from the driving circuit 20 is initially at a high level, and thereafter, locks the MOSFET in a turned-on state.

The driving circuit 20 is supplied with power from an external power source (positive power source Vdd, negative power source Vss), and its output (second node P2) is connected to the gate of the depletion transistor Q1, and the depletion transistor Q1 is turned on or off by a control signal outputted from the driving circuit 20. Specifically, the depletion transistor Q1 is turned on when the control signal output from the driving circuit 20 is at a high level, and the depletion transistor Q1 is turned off when the control signal output from the driving circuit 20 is at a low level.

That is, the MOSFET transistor Q2 is continuously turned on during normal operation of the device in the circuit, and the turn-on and turn-off processes of the device are completed by the depletion transistor Q1. In the driving circuit, only one path of control signal is needed to be input to control the on and off of the whole device, and no additional enabling signal is needed to drive the MOS to be on.

In the embodiment of the application, during the switching process of the device, the MOSFET Q2 is continuously turned on, and the output capacitor Coss thereof has no frequent charging and discharging process. In addition, the charge and discharge current of the gate-source capacitance Cgs of the depletion transistor Q1 is provided by an external driving power supply, and when the device is in a different mode from a device switch with a cascode structure, the charge and discharge current of the capacitor is provided by the current Ids of the device, so that the switching loss is lower, and the effect is more obvious in a high-frequency application system.

In addition, since the MOSFET Q2 is continuously turned on during operation of the device, no current flows through the body diode of the MOSFET Q2 during operation of the device at the third quadrant, and no reverse recovery problems occur.

Because the depletion type transistor Q1 is directly driven to be turned on and off, the MOSFET Q2 maintains the on state when the device works, and in the switching process, a dynamic voltage division process does not exist between the HEMT and the MOS, so that the problem of capacitance matching does not exist, and the problem of oscillation failure caused by extra loss or capacitance mismatch due to MOS avalanche breakdown is avoided.

In the application circuit, the device can realize forward blocking when the auxiliary driving power supply is not supplied with power. When the auxiliary driving power supply in the system starts to supply power, the MOS and the HEMT are kept in the off state until the system starts to work, after the driving signal level is changed to the high level, the MOS and the HEMT are conducted, and when the system stops working, the driving signal level is changed to the low level, and the MOS and the HEMT are in the off state. Illustratively, the high level is an active level and the low level is an inactive level.

Fig. 3 shows a second schematic diagram of a driving circuit of a depletion transistor according to an exemplary embodiment of the present application.

In a preferred embodiment of the present application, the switch control module 10 may include, but is not limited to, a tank sub-circuit 11, a clamp sub-circuit 12, and an auxiliary control sub-circuit 13.

As shown in fig. 3, the tank sub-circuit 11 is connected to a third node P3 and a fourth node P4, respectively, the third node P3 is between the power supply Vdd and the first node P1, and the fourth node P4 is between the output terminal of the driving circuit 20 and the gate of the MOSFET.

The tank sub-circuit 11 is configured to store energy and provide a high level to the fourth node P4 to control the MOSFET Q2 to turn on when the second node P2 is at a high level, and to provide a high level to the fourth node P4 to maintain the MOSFET Q2 to turn on by discharging the energy stored by the tank sub-circuit 11 when the second node P2 is at a low level.

The clamping sub-circuit 12 is connected to the third node P3 and the fourth node P4, respectively, and is configured to clamp the voltages at the third node P3 and the fourth node P4 to turn off the MOSFET transistor Q2 when there is no control signal at the second node P2.

The auxiliary control sub-circuit 13 is connected to the second node P2 and the fourth node P4, respectively, and is configured to supply a high level to the fourth node P4 when the second node P2 is at a high level, and to supply a low level to the fourth node P4 when the second node P2 is at a low level.

Fig. 4 shows a third schematic diagram of a driving circuit of a depletion transistor according to an exemplary embodiment of the present application.

As shown in fig. 4, the auxiliary control sub-circuit 13 includes a first voltage dividing resistor R2, a second voltage dividing resistor R3, a transistor Q3, and a current limiting resistor R4.

Specifically, the first voltage dividing resistor R2 is connected to the second node P2 and the fifth node P5 respectively, the second voltage dividing resistor R3 is connected to the fifth node P5 and ground respectively, the base of the triode Q3 is connected to the fifth node P5, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is connected to one end of the current limiting resistor R4, and the other end of the current limiting resistor R4 is connected to the fourth node P4.

The transistor Q3 is an NPN transistor, and the output of the driving circuit is divided by the resistors R2 and R3, and then connected to the base of the NPN transistor Q3, the emitter of the transistor Q3 is connected to the negative power supply Vss, and the collector of the transistor Q3 is connected to the gate of the PMOS transistor Q2 through the current limiting resistor R4.

At the gate and source of the MOSFET Q2, an energy storage sub-circuit 11 and a clamp sub-circuit 12 are connected in parallel, the energy storage sub-circuit 11 comprising an energy storage capacitor C1 and the clamp sub-circuit 12 comprising a clamp resistor R1, as an example.

At the low level (e.g., low level) at the second node P2, the storage capacitor C1 is discharged through the clamp resistor R1 to provide the high level to the fourth node P4, wherein the discharge time is less than the duration of the low level.

In the MOS driving circuit, C1 is used as a charge pump, and when the system works normally, the MOS is maintained in a conducting state, and the magnitude of the MOS is selected to influence the switching frequency range of the system. The energy storage capacitor C1 can be charged by taking the triode Q3 as a switch, and also can be charged by taking the N-channel MOS tube as a switch.

Fig. 5 shows a fourth schematic diagram of a driving circuit of a depletion transistor provided in an exemplary embodiment of the present application.

In an exemplary embodiment of the present application, the driving circuit further includes a second diode D2.

Specifically, the anode of the second diode D2 is connected to the power supply Vdd, the cathode of the second diode D2 is connected to the third node P3, and the external positive power supply Vdd is connected to the source of the MOSFET transistor Q2, i.e., the source of the depletion transistor Q1, through the protection diode D2.

After the external driving power supply is turned on, if there is no input signal or when the input signal is at a low level, the driving circuit 20 outputs a low level Vss, the transistor Q3 is turned off, and at this time, the gate-source voltage of the MOSFET Q2 is clamped to 0v by the clamping resistor R1, and the MOSFET Q2 is in an off state.

When the input signal is at a high level, the driving circuit Driver outputs a high level Vdd, and at this time, the transistor Q3 is turned on, and the external driving power supply charges the energy storage capacitor C1 through D2, R4 and Q3.

When the C1 voltage reaches the Q2 on threshold, Q2 starts to conduct, and the voltage is maintained at Vdd-Vss when stable, is higher than the Q2 threshold voltage and leaves margin. After the input signal goes back to low level, since C1 can only be discharged through R1, the discharge time is very slow compared to the switching period, so Q2 can be maintained in the on state during the low level period of one period. The next cycle starts the input signal back to high and the capacitor C1 is charged again. The values of C1 and R2 are properly selected according to the frequency and the duty ratio of the practical system application, so that the Q2 can be ensured to be always kept in a conducting state when the system normally operates.

The above-described driving circuit of the present exemplary embodiment further includes: the switching regulator sub-circuit 30 is disposed between the second node P2 and the gate of the depletion transistor Q1 to regulate the switching speed of the depletion transistor Q1.

Under the condition of no external driving power supply, the clamping resistor R1 enables the Q2 to be in an off state, so that the whole device is guaranteed to be in a normally-off state. When a voltage is applied between the Drain pole and the Source pole of the device, which is lower than the absolute value |Vth_HEMT| of the threshold voltage of the normally-open HEMT device, Q2 bears all voltages because Q1 is in a normally-open state. When the applied voltage of the device is higher than |vth_hemt|, the blocking voltage of Q2 also exceeds |vth_hemt|, and due to the clamping effect of the diode D1, the gate of Q1 is clamped at 0V, so the gate-source voltage of Q1 starts to be lower than the threshold voltage-vth_hemt, so that Q1 is turned off. As the applied voltage of the device Drain pole increases, Q2 will withstand voltages near vth_hemt and Q1 will withstand the rest of the voltage.

Fig. 6 shows a fifth schematic diagram of a driving circuit of a depletion transistor provided in an exemplary embodiment of the present application.

In an exemplary embodiment of the present application, the switching regulator sub-circuit may include a first driving resistor R5.

As shown in fig. 6, the driving circuit Driver is supplied with power from an external power source, ignoring the internal voltage drop, and considering that the output high level is about Vdd, the low level is about Vss, and Vdd-Vss > |vth_hemt|. When the input control signal is at a high level, the driving circuit 20 outputs a high level Vdd, and since the source of the depletion transistor Q1 is clamped at Vdd by D2 (ignoring the D2 drop), the gate-source voltage of Q1 is Vdd-vdd=0v, and Q1 is turned on. When the input control signal is at a low level, the driving circuit 20 outputs a low level Vss, and at this time, the gate-source voltage of Q1 is Vss-Vdd lower than the threshold voltage vth_hemt of Q1, and Q1 is turned off. The charge and discharge speed of the Q1 gate-source capacitor Cgs_HEMT can be adjusted by adjusting the size of the first driving resistor R5, so that the on-off speed of the device is controlled.

That is, when the device works normally in the circuit, Q2 is continuously conducted, the driving circuit directly drives Q1 to finish the switching action, and the switching slew rate of the whole device can be adjusted by adjusting the size of R5.

It should be understood that the driving circuit can adjust the switching speed by one driving resistor R5, and can also adjust the on and off speeds of the device by adjusting R5 and R6, respectively.

Fig. 7 shows a schematic diagram of a driving circuit of a depletion transistor provided in an exemplary embodiment of the present application.

In the present exemplary embodiment, the switching regulator sub-circuit may include a first driving resistor R5, a second driving resistor R6, and a third diode D3.

In the working process of the device, the PMOS transistor Q2 maintains a conducting state, the driving circuit 20 directly drives the depletion transistor Q1, adjusts the driving resistor R5, or respectively sets the resistance values of on and off, and can conveniently adjust the charge and discharge current of the grid electrode of the depletion transistor Q1, thereby adjusting the switching slew rate of the whole device and facilitating solving the problem of system EMI.

When the device works, the whole device is directly driven to normally open HEMT, and the switching speed of the device can be regulated according to the EMI requirement of the system.

In a preferred embodiment, the driving circuit may further include: and a reverse path connected with the drain of the depletion transistor Q1 and the drain of the P-type MOSFET Q2 respectively. As shown in fig. 7, the reverse path may include a fourth diode D4, and the device may be connected in parallel with a SiC diode, providing a third quadrant path, reducing reverse voltage drop, reducing losses, while ensuring no reverse recovery problems.

In the present application, various packaging methods may be used for the driving circuit, which is not limited in the present application. The following list several packaging modes for the driving circuit.

In a first packaging manner, taking the driving circuit shown in fig. 7 as an example, the P-type MOSFET Q2 and the depletion-mode transistor Q1 may be packaged as a normally-off switch device, such as the package 100 shown in fig. 8, wherein the drain of the depletion-mode transistor Q1 is used as the drain of the normally-off switch device, the source of the depletion-mode transistor Q1 is connected to the source of the P-type MOSFET Q2, and the drain of the P-type MOSFET Q2 is used as the source of the normally-off switch device. Illustratively, diodes D1 and D4 may also be packaged into normally-off switching devices, where the normally-off switching devices have pins leading from the gate of depletion transistor Q1, the source of depletion transistor Q1, the gate of P-type MOSFET Q2, the source of the normally-off switching device, and the drain of the normally-off switching device.

Accordingly, the driving circuit 20, the tank sub-circuit 11, the clamp sub-circuit 12, the auxiliary control sub-circuit 13, and the switching regulator sub-circuit 30 are packaged as a driving chip for a normally-closed switching device, as the package 200 shown in fig. 8. That is, devices other than the depletion transistor Q1 and the P-type MOSFET transistor Q2 may be packaged as a driving chip.

And in the second packaging mode, the parameter-adjustable device is led out and connected outside the packaging.

In one example, taking the drive circuit shown in fig. 7 as an example, the P-type MOSFET and the depletion-mode transistor may be packaged as a normally-off switching device, such as package 100 shown in fig. 9, and the diodes D1 and D4 may also be packaged into the normally-off switching device, for example. The driving circuit 20 and the auxiliary control sub-circuit 13 are packaged as a driving chip for a normally closed switching device, such as a package 300 shown in fig. 9, and the energy storage sub-circuit 11, the clamping sub-circuit 12 and the switching regulator sub-circuit 30 are led out, such as a package 400 shown in fig. 9, and are connected outside the package so as to perform parameter regulation.

In another example, at least one of the clamp resistor R1, the storage capacitor C1, and the switching regulator sub-circuit 30 (resistor R5 and/or resistor R6) is led out, and other devices in addition thereto are packaged.

In a third packaging mode, the HEMT driving circuit is arranged outside the packaging, the switching speed is regulated, and other devices are integrated inside the chip.

Illustratively, the tank sub-circuit 11, clamp sub-circuit 12, auxiliary control sub-circuit 13, P-type MOSFET and depletion transistor Q1 are packaged as a depletion power device, such as package 500 shown in fig. 10, and illustratively, diodes D1 and D4 may also be packaged into normally-off switching devices. The driving circuit 20 and the switching regulator sub-circuit 30 are packaged as a driving chip for a depletion type power device, as in the package 600 shown in fig. 10, it is also possible to lead out only the switching regulator sub-circuit 30.

In the fourth packaging mode, all devices are packaged into a power device.

Illustratively, the driving circuit 20, the internal MOS transistor Q2, the HEMT two-way driving circuit, and the clamp diode are all integrated in one chip package.

The simulation process for the above-described driving circuit is described below with reference to fig. 11 to 13.

The simulation circuit is shown in fig. 11, the device works in a hard switching state, the driving signal frequency is 100kHz, and the duty ratio is 20%. The bus voltage was 100V.

As shown in the simulation result of fig. 12, in the I-stage, the driving signal Vgate is at a low level, the system is powered up at a high voltage, the bus voltage Vbus rises to 100V, the gate-source voltage vgs_mos of the low-voltage MOS is close to 0V, Q2 is in an off state, the drain-source voltage vds_mos of Q2 rises along with the rise of the bus voltage, Q1 is turned off after reaching the Q1 threshold voltage |vth_hemt|, vds of the HEMT starts to rise, vds_mos is maintained at around |vth_hemt|, and the HEMT receives the remaining voltage. In the II stage, when the driving signal is changed to a high level, vgate outputs a high level, the capacitor C1 starts to charge, the Vgs_MOS voltage of the MOS transistor rises, the Q2 is conducted, meanwhile, the gate-source voltage of the Q1 rises to about 0V from negative pressure, the Q1 is turned on, and the whole device is conducted. When the driving signal is changed from high level to low level, the voltage of the capacitor C1 is slightly reduced, but still higher than the threshold voltage of the MOS, and the MOS can be kept in an on state during the off period. And the Q1 gate-source capacitor is reversely charged, and the voltage is reduced from 0V to negative voltage, so that the whole device is turned off.

As a result of the simulation shown in fig. 13, when the system stops operating, the driving signal is stopped, the output is low level, Q1 is turned off, and the entire device is turned off in the III-th stage. At this time, the MOS is still on, and the HEMT bears the bus voltage. Meanwhile, as Q3 is turned off, the power supply stops charging C1, and C1 slowly discharges to MOS threshold voltage. In stage IV, when the C1 voltage, i.e., vgs_mos voltage, is lower than the threshold voltage, the MOS is turned off. The MOS drain-source voltage starts to rise, and at the same time the HEMT drain-source voltage drops, and the final voltage division ratio is determined by the respective off-leakage current.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solutions of the present application may be embodied in essence or a part contributing to the prior art or a part of the technical solutions, or in the form of a software product, which is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A driver circuit for a depletion transistor, comprising:

a MOSFET cascaded with the depletion transistor;

the switch control module is respectively connected with a first node, a second node and a grid electrode of the MOSFET, wherein the first node is arranged between the MOSFET and the depletion transistor, and the second node is an output end of the driving circuit;

a first diode, the anode of which is connected to the grid of the depletion transistor, and the cathode of which is connected to the drain of the MOSFET;

wherein the gate of the depletion transistor is connected to the second node and is configured to be turned on or off by a control signal output from the driving circuit, the switch control module is configured to control the MOSFET to be continuously turned on during operation of the depletion transistor,

wherein, the switch control module includes:

and the energy storage sub-circuit is respectively connected with a third node and a fourth node, the third node is arranged between the power supply and the first node, the fourth node is arranged between the output end of the driving circuit and the grid electrode of the MOSFET and is used for storing energy and providing high level for the fourth node to control the MOSFET to conduct when the second node is at a high level, and the energy stored by the energy storage sub-circuit is released when the second node is at a low level to provide high level for the fourth node to maintain the MOSFET to conduct.

2. The drive circuit of claim 1, wherein the period of operation of the depletion transistor includes a stage in which the drive circuit is enabled to output a control signal.

3. The drive circuit of claim 1, wherein the MOSFET comprises a P-type MOSFET, a source of the P-type MOSFET being connected to a source of the depletion transistor, and the first node being a source of the P-type MOSFET.

4. The drive circuit of claim 1, wherein the switch control module further comprises:

and a clamping sub-circuit connected to the third node and the fourth node, respectively, and configured to clamp voltages at the third node and the fourth node to turn off the MOSFET when there is no control signal at the second node.

5. The drive circuit of claim 4, wherein the clamp sub-circuit includes a clamp resistor and the tank sub-circuit includes a tank capacitor configured to discharge through the clamp resistor to provide a high level to the fourth node when the second node is low, wherein the discharge time is less than the duration of the low level.

6. The drive circuit of claim 4, wherein the switch control module further comprises:

and an auxiliary control sub-circuit connected to the second node and the fourth node, respectively, and configured to supply a high level to the fourth node when the second node is at a high level, and to supply a low level to the fourth node when the second node is at a low level.

7. The drive circuit of claim 6, wherein the auxiliary control sub-circuit comprises:

the first voltage dividing resistor is respectively connected with the second node and the fifth node;

the second voltage dividing resistor is connected with the fifth node and the ground respectively;

and the base electrode of the triode is connected to the fifth node, the emitter electrode of the triode is grounded, and the collector electrode of the triode is connected to the fourth node.

8. The drive circuit of claim 7, wherein the auxiliary control sub-circuit further comprises:

and the current limiting resistor is arranged between the collector electrode of the triode and the fourth node.

9. A driver circuit according to claim 3, wherein the driver circuit further comprises:

and the anode of the second diode is connected to the power supply, and the cathode of the second diode is connected to the third node.

10. The drive circuit of claim 6, wherein the drive circuit further comprises:

and the switching regulator sub-circuit is arranged between the second node and the grid electrode of the depletion type transistor so as to regulate the switching speed of the depletion type transistor.

11. A driver circuit according to claim 3, wherein the driver circuit further comprises:

and a reverse path connected with the drain of the depletion transistor and the drain of the P-type MOSFET respectively.

12. The driving circuit of claim 10, wherein the P-type MOSFET and the depletion-mode transistor are packaged as a normally-closed switching device, the driving circuit, the energy storage sub-circuit, the clamp sub-circuit, the auxiliary control sub-circuit, and the switching regulator sub-circuit are packaged as a driving chip for the normally-closed switching device,

the drain electrode of the depletion type transistor is used as the drain electrode of the normally-off switching device, the source electrode of the depletion type transistor is connected with the source electrode of the P type MOSFET, and the drain electrode of the P type MOSFET is used as the source electrode of the normally-off switching device;

or the P-type MOSFET and the depletion transistor are packaged into a normally-closed switching device, the driving circuit and the auxiliary control subcircuit are packaged into a driving chip aiming at the normally-closed switching device, and the energy storage subcircuit, the clamping subcircuit and the switching regulation subcircuit are led out and connected outside the package;

or the energy storage sub-circuit, the clamping sub-circuit, the auxiliary control sub-circuit, the P-type MOSFET and the depletion type transistor are packaged into a depletion type power device, and the driving circuit and the switching regulator sub-circuit are packaged into a driving chip for the depletion type power device;

alternatively, all devices are packaged as a power device.