CN104022776A - Bootstrapping diode artificial circuit in half-bridge driving circuit - Google Patents
Bootstrapping diode artificial circuit in half-bridge driving circuit Download PDFInfo
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- CN104022776A CN104022776A CN201410304459.0A CN201410304459A CN104022776A CN 104022776 A CN104022776 A CN 104022776A CN 201410304459 A CN201410304459 A CN 201410304459A CN 104022776 A CN104022776 A CN 104022776A
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Abstract
The invention provides a bootstrapping diode artificial circuit in a half-bridge driving circuit. An electrical level displacement and a simple charge pump are added into a grid driving circuit structure in an existing bootstrapping diode artificial circuit; when a grid driving input signal is a low electrical level, grid voltage output to an N-channel LDMOS (Lateral Diffusion Metal Oxide Semiconductor) transistor LD1 by a grid driving circuit is a low electrical level; the N-channel LDMOS transistor LD1 is turned off. When the grid driving input signal is a high electrical level, the grid voltage output to the N-channel LDMOS transistor LD1 by the grid driving circuit is a high electrical level so that the grid voltage of the N-channel LDMOS transistor LD1 is improved, the conduction resistance of the LD1 is reduced and the charging current to a bootstrapping capacitor is improved.
Description
Technical field
The present invention relates to half-bridge drive circuit, relate in particular to the bootstrap diode artificial circuit in a kind of half-bridge drive circuit.
Background technology
Half-bridge drive circuit has a wide range of applications in the fields such as motor driving, electric ballast, Switching Power Supply, and it is used for driving two with power MOS pipe or the IGBT of the connection of totem form, makes its alternate conduction.Except the high-pressure level shift circuit as high side and downside circuit interface, (it is positioned at the edge of isolation structure in half-bridge drive circuit inside, need to be operated under the voltage of hundreds of volt), other circuit module lays respectively at higher-pressure region (high side Power supply) and low-pressure area (downside Power supply), all be operated under the voltage of 10 to 20 volts, in order to improve the utilization ratio of power supply, only adopt single power supply, DC power supply VCC power supply is directly used in low-pressure area, higher-pressure region powers by bootstrap capacitor in floating state, as shown in Figure 1, lower pipe (low side pipe) M in half-bridge structure
1conducting, upper pipe (high side pipe) M
2during shutoff, DC power supply VCC is by bootstrap diode D
bwith lower pipe M
1to bootstrap capacitor C
bcharging, when upper pipe is opened, when lower pipe turn-offs, bootstrap capacitor C
bfor high lateral circuit power supply.
External boostrap circuit is by bootstrap diode D
bwith bootstrap capacitor C
bform, but the cost of bootstrap diode meeting increasing circuit, conduction voltage drop affects the charging pressure drop on final electric capacity, and its reverse recovery current causes bootstrap capacitor electric leakage, and the peak current capacity needing due to bootstrap diode is too large, puncture voltage is too high, to such an extent as to can not be integrated in chip, United States Patent (USP) proposes a kind of bootstrap diode emulator with dynamic back of the body gate bias, the bootstrap diode D in alternate figures 1 No. 7215189B2
b, as shown in Figure 2,3, bootstrap diode emulator comprises N raceway groove ldmos transistor LD1, its drain electrode is connected to downside supply voltage, source electrode is connected to the output VB of bootstrap diode emulator, and grid is controlled by gate driver circuit, and back grid is connected to dynamic back of the body gate bias circuit.Only at low side drive output LO, while being high, control the conducting of described N raceway groove ldmos transistor, realize bootstrap capacitor C
bcharging.
Although the gate driver circuit in No. 7215189B2nd, United States Patent (USP) can effectively prevent that LDMOS from opening by mistake and open, and it dynamically carries on the back the parasitic triode conducting that gate bias can prevent N raceway groove ldmos transistor LD1, and the conducting resistance of N raceway groove ldmos transistor LD1 in charging process is constantly reduced, increased bootstrapping charging current.But the driving voltage Vgate that gives N raceway groove ldmos transistor LD1 grid of its gate driver circuit output is not high enough, this makes the conducting resistance of N raceway groove ldmos transistor LD1 still too high, and charging rate is still fast not.This makes this traditional bootstrap diode artificial circuit be not suitable for some application, for example high frequency half bridge drive circuit application.
Summary of the invention
The object of the invention is the shortcoming for bootstrap diode artificial circuit in No. 7215189B2nd, United States Patent (USP), bootstrap diode in a kind of half-bridge drive circuit artificial circuit is provided, gate driver circuit is wherein improved, can improve the gate drive voltage Vgate of N raceway groove ldmos transistor LD1 in bootstrap diode emulator.
To achieve these goals, technical scheme of the present invention is as follows:
A bootstrap diode artificial circuit in half-bridge drive circuit, half-bridge drive circuit comprises the downside NMOS pipe M as load
1with high side NMOS pipe M
2and low side drive circuit, high side drive circuit, logic control circuit, bootstrap capacitor C
bwith bootstrap diode artificial circuit, high side NMOS pipe M
2with downside NMOS pipe M
1mode with totem is connected, high side NMOS pipe M
2drain electrode connect high side power supply VH, high side NMOS pipe M
2grid connect the output HO of high side drive circuit, high side NMOS pipe M
2source electrode and downside NMOS pipe M
1drain electrode interconnect and connect floating ground end VS and the bootstrap capacitor C of high side drive circuit
bone end, bootstrap capacitor C
bthe other end connect the output voltage V B of bootstrap diode artificial circuit, downside NMOS manages M
1grid connect the output LO of low side drive circuit, downside NMOS manages M
1source electrode COM publicly, the feeder ear of low side drive circuit connects downside power supply VCC, the earth terminal of low side drive circuit connects COM publicly, the feeder ear of high side drive circuit connects the output voltage V B of bootstrap diode artificial circuit, the feeder ear of bootstrap diode artificial circuit connects downside power supply VCC, high side input signal HIN and downside input signal LIN export respectively high side signal and side signal to high side drive circuit and low side drive circuit by logic control circuit, downside input signal LIN also connects the signal input part of bootstrap diode artificial circuit, the feeder ear of logic control circuit connects downside power supply VCC, the earth terminal of logic control circuit connects COM publicly,
Bootstrap diode artificial circuit comprises N raceway groove ldmos transistor LD1, gate driver circuit and dynamically carry on the back gate bias circuit, the grid of N raceway groove ldmos transistor LD1 connects the output of gate driver circuit, the output of gate driver circuit also connects dynamic back of the body gate bias circuit, the LDMOS that is used for setovering in moving band back of the body gate bias circuit manages the grid of LD2, the input of gate driver circuit connects downside input signal LIN, the source electrode of N raceway groove ldmos transistor LD1 is the output voltage V B end of bootstrap diode artificial circuit, the drain electrode of N raceway groove ldmos transistor LD1 connects downside power supply VCC, dynamically the input of back of the body gate bias circuit connects downside input signal LIN, dynamically the output of back of the body gate bias circuit connects the back grid of N raceway groove ldmos transistor LD1,
Dynamically back of the body gate bias circuit comprises inverter INV4, NMOS manages MN3, NMOS manages MN4, raceway groove ldmos transistor LD2, current source I3, current source I4 and parasitic triode Q1, the input of inverter INV4 connects downside input signal LIN, the output of inverter INV4 connects the grid of NMOS pipe MN3, the grid of the drain electrode of NMOS pipe MN3 and NMOS pipe MN4, the source electrode of raceway groove ldmos transistor LD2 and the anode of current source I4 connect, the drain electrode of NMOS pipe MN4 connects downside power supply VCC, the NMOS pipe source electrode of MN4 and the anode of current source I3, the back grid of raceway groove ldmos transistor LD2 and the emitter of parasitic triode Q1 link together and the dynamic back grid of carrying on the back the output Vback connection N raceway groove ldmos transistor LD1 of gate bias circuit of conduct, the grid that the grid of raceway groove ldmos transistor LD2 connects N raceway groove ldmos transistor LD1 is the output of gate driver circuit, the drain electrode of raceway groove ldmos transistor LD2 connects the base stage of parasitic triode Q1 and is connected with the output voltage V B of bootstrap diode artificial circuit, the collector electrode of parasitic triode Q1, current source I3, the source electrode of the negative terminal of I4 and NMOS pipe MN3 all connects COM publicly,
It is characterized in that: the gate driver circuit in bootstrap diode artificial circuit comprises inverter INV1, inverter INV2, inverter INV3, capacitor C 1, capacitor C 2, NMOS manages MN1, NMOS manages MN2, PMOS manages MP1, Schmidt trigger S, diode D1, parasitic diode D2 and current source I1 and current source I2, the input of inverter INV1 connects downside input signal LIN, the output of inverter INV1 is connected with the grid of NMOS pipe MN1 with the input of inverter INV2, the output of inverter INV2 connects one end of capacitor C 1, the other end of capacitor C 1 connects the negative electrode of diode D1 and the power end of inverter INV3, the anode of diode D1 links together and is connected downside power supply VCC with PMOS pipe MP1 source electrode with the drain electrode of NMOS pipe MN2, the source electrode of the output of inverter INV3 and NMOS pipe MN1, the anode of parasitic diode D2 is connected with the grid of NMOS pipe MN2, the drain electrode of NMOS pipe MN1 connects the negative electrode of parasitic diode D2, the source electrode of NMOS pipe MN2 connects the PMOS pipe grid of MP1 and the anode of current source I1, the drain electrode of PMOS pipe MP1 connects the input of Schmidt trigger S and the anode of current source I2, current source I1, the equal ground connection of negative terminal of I2, the output of Schmidt trigger S connects one end of capacitor C 2, the other end connection NMOS of capacitor C 2 manages the drain electrode of MN1 and as the output Vgate of gate driver circuit, connects grid and the dynamic grid of carrying on the back raceway groove ldmos transistor LD2 in gate bias circuit of N raceway groove ldmos transistor LD1.
Compared with prior art, the advantage that the present invention has is as follows:
(1) the present invention compares with prior art bootstrap diode artificial circuit Central Plains gate driver circuit, output voltage has increased the voltage VGS2 that level shift circuit is introduced, thereby improved the grid voltage of ldmos transistor LD1, reduce the conducting resistance of LDMOSLD1, improved the charging current to bootstrap capacitor.
(2) while causing electric charge on bootstrap capacitor excessively to be released when chip power starts or due to external environment, more than the charging interval of bootstrap capacitor may need hundreds of microsecond, at capacitance voltage, be not charged to when enough high, the high side of chip, always in under-voltage condition, is managed M on half-bridge
2keep turn-offing, and pulse generator is opened N channel laterally bilateral diffusion MOS pipe in high-pressure level shift circuit as under normal circumstances, electric charge on bootstrap capacitor discharges by resistance and the N raceway groove ldmos transistor of level shift circuit, the electric energy storing on waste bootstrap capacitor, the present invention has shortened electrifying startup time and the charge cycle in under-voltage condition, be equivalent to and reduced the meaningless discharge regime of bootstrap capacitor, improved utilization ratio and the charge efficiency of bootstrap capacitor electric charge.
(3) the present invention has reduced the conducting resistance of ldmos transistor LD1, has reduced the conduction loss bringing due to ldmos transistor LD1 conducting resistance.
Accompanying drawing explanation
Fig. 1 is traditional half-bridge drive circuit that prior art adopts bootstrap diode and bootstrap capacitor;
Fig. 2 is the half-bridge drive circuit that United States Patent (USP) adopts bootstrap diode in bootstrap diode artificial circuit alternate figures 1 for the 7215189 No. B2;
Fig. 3 is the basic structure of bootstrap diode artificial circuit in Fig. 2;
Fig. 4 is the dynamic back of the body gate bias circuit in Fig. 3 bootstrap diode artificial circuit;
Fig. 5 is the gate driver circuit in bootstrap diode artificial circuit of the present invention.
Embodiment
No. 7,215,189 B2, half-bridge drive circuit of the present invention and Fig. 2 United States Patent (USP) are identical, and when low side drive circuit output, LO is that high level makes power tube M
1during unlatching, bootstrap diode artificial circuit allows electric current to flow through bootstrap diode artificial circuit and power tube M from downside supply voltage VCC
2to bootstrap capacitor C
bcharging, thereby bootstrap capacitor C
bbe charged to close to downside supply voltage VCC.As power tube M
2open and power tube M
1during shutoff, bootstrap diode artificial circuit stops electric current to flow to capacitor C from downside supply voltage VCC
bthereby, be stored in bootstrap capacitor C
bin electric charge provide voltage for high side drive circuit.
Bootstrap diode artificial circuit of the present invention is identical with Fig. 3, and the dynamic back of the body gate bias circuit in bootstrap diode artificial circuit is identical with Fig. 4, and gate driver circuit and dynamically back of the body gate bias circuit are controlled by downside input signal LIN.The input control signal of gate driver circuit meets LIN, output is connected to the grid of N raceway groove ldmos transistor LD1, the height of gate driver circuit output Vgate, by input signal, LIN controls, when LIN is low level, Vgate is low level, N raceway groove ldmos transistor LD1 turn-offs, when LIN is high level, Vgate is high level, N raceway groove ldmos transistor LD2 conducting, thus the height of gate driver circuit output Vgate by input signal LIN, controlled, thus make the LD1 conducting of N raceway groove ldmos transistor or shutoff.Dynamically the input control signal of back of the body gate bias circuit meets LIN, output is connected to the back grid of ldmos transistor LD1, back-gate biasing circuit is by applying dynamic bias voltage to ldmos transistor LD1 when the N raceway groove ldmos transistor LD1 conducting, this bias voltage is close to the source voltage of ldmos transistor LD1, but slightly lower than the source voltage of described N raceway groove ldmos transistor LD1.
Referring to Fig. 5, gate driver circuit in bootstrap diode artificial circuit of the present invention comprises inverter INV1, inverter INV2, inverter INV3, capacitor C 1, capacitor C 2, NMOS manages MN1, NMOS manages MN2, PMOS manages MP1, Schmidt trigger S, diode D1, parasitic diode D2 and current source I1 and current source I2, the input of inverter INV1 connects downside input signal LIN, the output of inverter INV1 is connected with the grid of NMOS pipe MN1 with the input of inverter INV2, the output of inverter INV2 connects one end of capacitor C 1, (supply voltage of inverter INV3 is provided by charge pump electric capacity for the negative electrode of the other end connection diode D1 of capacitor C 1 and the power end of inverter INV3, the supply voltage of this inverter is at VCC～2VCC-V in theory
d1, and the supply voltage of other inverter is defaulted as VCC).The anode of diode D1 links together and is connected downside power supply VCC with PMOS pipe MP1 source electrode with the drain electrode of NMOS pipe MN2, the source electrode of the output of inverter INV3 and NMOS pipe MN1, the anode of parasitic diode D2 is connected with the grid of NMOS pipe MN2, the drain electrode of NMOS pipe MN1 connects the negative electrode of parasitic diode D2, the source electrode of NMOS pipe MN2 connects the PMOS pipe grid of MP1 and the anode of current source I1, the drain electrode of PMOS pipe MP1 connects the input of Schmidt trigger S and the anode of current source I2, current source I1, the equal ground connection of negative terminal of I2, the output of Schmidt trigger S connects one end of capacitor C 2, the other end connection NMOS of capacitor C 2 manages the drain electrode of MN1 and as the output Vgate of gate driver circuit, connects grid and the dynamic grid of carrying on the back raceway groove ldmos transistor LD2 in gate bias circuit of N raceway groove ldmos transistor LD1.
According to Fig. 5, the present invention has added a level shift and a simple charge pump in existing grid electrode drive circuit structure, when gate drive input signal is low level, gate driver circuit output Vgate is low level, turn-off ldmos transistor LD1, when gate drive input signal is high level, gate driver circuit output Vgate is high level.The source follower that NMOS pipe MN2 and current source I1 form is as level shift circuit, diode D1, capacitor C 1 and inverter INV3 form simple charge pump, the specific works principle of charge pump bootstrapping is: when downside input signal LIN input low level (0 current potential), the link of inverter INV1 and INV2 is high level, the link of capacitor C 1 and diode D1 is charged to and approaches downside supply voltage VCC, NMOS pipe MN2 grid voltage is that the source electrode of NMOS pipe MN1 is low level, thereby the grid Vgate of N raceway groove ldmos transistor LD1 is low level, because at half-bridge load node (M
1with M
2link) voltage transitions during, when the dV/dt of load node end is larger, the Miller effect electric current of N raceway groove ldmos transistor LD1 may be very large, it is low level that the present invention makes NMOS pipe MN2 gate input voltage, during half-bridge load node level conversion, the gate charge of N raceway groove ldmos transistor LD1 will be managed MN1 by NMOS and be released, and reduce ldmos transistor LD1 and open by mistake the possibility opening, when downside input signal LIN is high level (VCC current potential), the link of inverter INV1 and INV2 is electronegative potential, the output of INV2 is high level, the link voltage of capacitor C 1 and diode D1 is higher than downside supply voltage VCC, the voltage exceeding equals the amount of charged voltage keeping in capacitor C 1, capacitor C 1 is approximately 2 times of VCC with the voltage of diode D1 link, in limited delay, the output of inverter INV3 is that NMOS pipe MN2 gate input voltage is also approximately the threshold voltage that gate source voltage VGS2 that downside supply voltage VCC adds NMOS pipe MN2 deducts PMOS pipe MP1 again, in this limited time delay, PMOS pipe MP1 keeps conducting, Schmidt trigger S is input as high level, thereby Schmidt trigger S is output as low level, this causes capacitor C 1 and the link of diode D1 to charge to capacitor C 2 by the PMOS pipe in inverter INV3 and parasitic diode D2, the voltage of Vgate end raises gradually with respect to Schmidt trigger S output, once the gate input voltage of NMOS pipe MN2 is elevated to the threshold voltage that gate source voltage VGS2 that downside supply voltage VCC adds NMOS MN2 deducts PMOS pipe MP1 again, the grid voltage once PMOS pipe MP1 rises to the threshold voltage that downside supply voltage VCC deducts PMOS pipe MP1, Schmidt trigger S is input as low level, the output of Schmidt trigger S is high level (VCC current potential), thereby the current potential of Vgate end is higher than downside supply voltage, the value exceeding is the voltage keeping in capacitor C 2, now, the voltage of Vgate end is that 2 times of downside supply voltage VCC add that the gate source voltage VGS2 of NMOS pipe deducts the threshold voltage of PMOS pipe MP1 more in theory, but the voltage of Vgate end is less than this value conventionally, impact due to the conduction voltage drop of parasitic diode D2, the voltage of Vgate end also needs to deduct the conduction voltage drop of this parasitic diode D2 again.In addition, be subject to the trigging signal impact that Schmidt trigger S and PMOS manage MP1 branch road, the voltage of actual Vgate end can be slightly smaller again, if but want that the voltage that improves Vgate end can increase the gate source voltage VGS2 that NMOS manages MN2.The present invention has improved a considerable magnitude of voltage VGS2 by the grid voltage of N raceway groove ldmos transistor LD1, effectively reduces the conducting resistance of N raceway groove ldmos transistor, has also improved to bootstrap capacitor C simultaneously
bcharging current, shortened the charging interval.
The course of work of Fig. 5: gate driver circuit makes the LD1 conducting of N raceway groove ldmos transistor or shutoff according to downside input signal LIN.With respect to the drain electrode of N raceway groove ldmos transistor LD1, gate driver circuit provides positive voltage for the grid of N raceway groove ldmos transistor LD1.Because the drain electrode utmost point of N raceway groove ldmos transistor LD1 is connected to downside supply voltage VCC, therefore, the output level Vgate of gate driver circuit need to be higher than downside supply voltage VCC, and this can be by capacitor C 2 bootstrapping charging and its voltage is used for to the grid of driving N raceway groove ldmos transistor LD1 realizes.
Claims (1)
1. the bootstrap diode artificial circuit in half-bridge drive circuit, half-bridge drive circuit comprises the downside NMOS pipe M as load
1with high side NMOS pipe M
2and low side drive circuit, high side drive circuit, logic control circuit, bootstrap capacitor C
bwith bootstrap diode artificial circuit, high side NMOS pipe M
2with downside NMOS pipe M
1mode with totem is connected, high side NMOS pipe M
2drain electrode connect high side power supply VH, high side NMOS pipe M
2grid connect the output HO of high side drive circuit, high side NMOS pipe M
2source electrode and downside NMOS pipe M
1drain electrode interconnect and connect floating ground end VS and the bootstrap capacitor C of high side drive circuit
bone end, bootstrap capacitor C
bthe other end connect the output voltage V B of bootstrap diode artificial circuit, downside NMOS manages M
1grid connect the output LO of low side drive circuit, downside NMOS manages M
1source electrode COM publicly, the feeder ear of low side drive circuit connects downside power supply VCC, the earth terminal of low side drive circuit connects COM publicly, the feeder ear of high side drive circuit connects the output voltage V B of bootstrap diode artificial circuit, the feeder ear of bootstrap diode artificial circuit connects downside power supply VCC, high side input signal HIN and downside input signal LIN export respectively high side signal and side signal to high side drive circuit and low side drive circuit by logic control circuit, downside input signal LIN also connects the signal input part of bootstrap diode artificial circuit, the feeder ear of logic control circuit connects downside power supply VCC, the earth terminal of logic control circuit connects COM publicly,
Bootstrap diode artificial circuit comprises N raceway groove ldmos transistor LD1, gate driver circuit and dynamically carry on the back gate bias circuit, the grid of N raceway groove ldmos transistor LD1 connects the output of gate driver circuit, the output of gate driver circuit also connects dynamic back of the body gate bias circuit, the LDMOS that is used for setovering in moving band back of the body gate bias circuit manages the grid of LD2, the input of gate driver circuit connects downside input signal LIN, the source electrode of N raceway groove ldmos transistor LD1 is the output voltage V B end of bootstrap diode artificial circuit, the drain electrode of N raceway groove ldmos transistor LD1 connects downside power supply VCC, dynamically the input of back of the body gate bias circuit connects downside input signal LIN, dynamically the output of back of the body gate bias circuit connects the back grid of N raceway groove ldmos transistor LD1,
Dynamically back of the body gate bias circuit comprises inverter INV4, NMOS manages MN3, NMOS manages MN4, raceway groove ldmos transistor LD2, current source I3, current source I4 and parasitic triode Q1, the input of inverter INV4 connects downside input signal LIN, the output of inverter INV4 connects the grid of NMOS pipe MN3, the grid of the drain electrode of NMOS pipe MN3 and NMOS pipe MN4, the source electrode of raceway groove ldmos transistor LD2 and the anode of current source I4 connect, the drain electrode of NMOS pipe MN4 connects downside power supply VCC, the NMOS pipe source electrode of MN4 and the anode of current source I3, the back grid of raceway groove ldmos transistor LD2 and the emitter of parasitic triode Q1 link together and the dynamic back grid of carrying on the back the output Vback connection N raceway groove ldmos transistor LD1 of gate bias circuit of conduct, the grid that the grid of raceway groove ldmos transistor LD2 connects N raceway groove ldmos transistor LD1 is the output of gate driver circuit, the drain electrode of raceway groove ldmos transistor LD2 connects the base stage of parasitic triode Q1 and is connected with the output voltage V B of bootstrap diode artificial circuit, the collector electrode of parasitic triode Q1, current source I3, the negative terminal of I4 is all connected COM publicly with the source electrode of NMOS pipe MN3,
It is characterized in that: the gate driver circuit in bootstrap diode artificial circuit comprises inverter INV1, inverter INV2, inverter INV3, capacitor C 1, capacitor C 2, NMOS manages MN1, NMOS manages MN2, PMOS manages MP1, Schmidt trigger S, diode D1, parasitic diode D2 and current source I1 and current source I2, the input of inverter INV1 connects downside input signal LIN, the output of inverter INV1 is connected with the grid of NMOS pipe MN1 with the input of inverter INV2, the output of inverter INV2 connects one end of capacitor C 1, the other end of capacitor C 1 connects the negative electrode of diode D1 and the power end of inverter INV3, the anode of diode D1 links together and is connected downside power supply VCC with PMOS pipe MP1 source electrode with the drain electrode of NMOS pipe MN2, the source electrode of the output of inverter INV3 and NMOS pipe MN1, the anode of parasitic diode D2 is connected with the grid of NMOS pipe MN2, the drain electrode of NMOS pipe MN1 connects the negative electrode of parasitic diode D2, the source electrode of NMOS pipe MN2 connects the PMOS pipe grid of MP1 and the anode of current source I1, the drain electrode of PMOS pipe MP1 connects the input of Schmidt trigger S and the anode of current source I2, current source I1, the equal ground connection of negative terminal of I2, the output of Schmidt trigger S connects one end of capacitor C 2, the other end connection NMOS of capacitor C 2 manages the drain electrode of MN1 and as the output Vgate of gate driver circuit, connects grid and the dynamic grid of carrying on the back raceway groove ldmos transistor LD2 in gate bias circuit of N raceway groove ldmos transistor LD1.
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| CN201410304459.0A CN104022776B (en) | 2014-06-27 | 2014-06-27 | Bootstrapping diode artificial circuit in half-bridge driving circuit |
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|---|---|---|---|
| CN201410304459.0A CN104022776B (en) | 2014-06-27 | 2014-06-27 | Bootstrapping diode artificial circuit in half-bridge driving circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134204A (en) * | 1994-07-15 | 1996-10-23 | 菲利浦电子有限公司 | Driver circuit for bridge circuit employing bootstrap diode emulator |
| CN1879111A (en) * | 2003-11-12 | 2006-12-13 | 国际整流器公司 | Bootstrap diode emulator with dynamic back-gate biasing |
| CN101465597A (en) * | 2007-12-21 | 2009-06-24 | 英飞凌科技股份有限公司 | Circuit arrangement for providing a voltage supply for a transistor driver circuit |
| CN102904220A (en) * | 2012-11-07 | 2013-01-30 | 东南大学 | Under-voltage protection method of high-voltage half-bridge driving chip and high-voltage half-bridge circuit |
-
2014
- 2014-06-27 CN CN201410304459.0A patent/CN104022776B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134204A (en) * | 1994-07-15 | 1996-10-23 | 菲利浦电子有限公司 | Driver circuit for bridge circuit employing bootstrap diode emulator |
| CN1879111A (en) * | 2003-11-12 | 2006-12-13 | 国际整流器公司 | Bootstrap diode emulator with dynamic back-gate biasing |
| CN101465597A (en) * | 2007-12-21 | 2009-06-24 | 英飞凌科技股份有限公司 | Circuit arrangement for providing a voltage supply for a transistor driver circuit |
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