CN111555595B - GaN power tube gate drive circuit with controllable opening rate - Google Patents
GaN power tube gate drive circuit with controllable opening rate Download PDFInfo
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- CN111555595B CN111555595B CN202010603190.1A CN202010603190A CN111555595B CN 111555595 B CN111555595 B CN 111555595B CN 202010603190 A CN202010603190 A CN 202010603190A CN 111555595 B CN111555595 B CN 111555595B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
A GaN power tube grid driving circuit with a controllable starting rate comprises an internal power generation module, a grid driving module, a charge pump module, an external capacitor and a current-limiting resistor, wherein the grid driving module controls the grid electrode of a GaN power tube to charge and discharge according to an external control signal; the external capacitor is connected with the power supply end of the gate driving module after passing through the current-limiting resistor; the internal power generation module comprises a power adjusting tube controlled by the charge pump module, and the charge pump module controls the power adjusting tube to be disconnected before the GaN power tube is connected, so that the first power supply generated by the internal power generation module is disconnected from the power supply end of the gate driving module, the power is supplied to the gate driving module only by the external capacitor, and the grid charging rate of the GaN power tube is reduced; after the GaN power tube is conducted and set time delay is carried out, the charge pump module controls the power adjusting tube to be conducted, so that the first power supply is connected to the power supply end of the grid driving module, the first power supply and the external capacitor jointly supply power to the grid driving module, and the grid charging rate of the GaN power tube is increased.
Description
Technical Field
The invention belongs to the technical field of grid driving of power devices, and relates to a grid driving circuit of a GaN power tube with controllable starting rate.
Background
Compared with the traditional silicon power device, the GaN transistor is a good scheme for designing a power converter with high frequency and high power density due to smaller parasitic capacitance and higher conductivity. However, with the continuous increase of the working frequency of the chip, the GaN power tube performs a fast switching operation under a high voltage (600V) condition, which introduces a large current change rate di/dt and a large voltage change rate dv/dt to the chip, thereby causing an EMI (electromagnetic Interference) problem, which seriously affects the working performance of related systems such as automobiles or consumer electronics.
Conventional driver chips limit the charging current by using a suitable resistor in series with the driver output, but this is not a good way to balance efficiency, as in practice a small current is not always required to charge the gate capacitance of the power tube. Moreover, this strategy is not very flexible in SiP (System in Package) solutions, since the current limiting resistor is fixed inside the Package and cannot be freely adjusted. As shown in fig. 1, a schematic diagram of a conventional GaN gate driver chip adopting an SiP package form is shown, and the package can package a gate driver circuit and a GaN power tube in the same tube, so that the routing length of the gate driver output to the GaN power tube is reduced to a great extent, the parasitic inductance effect is reduced, the chip turn-on and turn-off speed is increased, and the problems of switching loss, ringing and chip reliability are reduced. However, the current limiting resistor between the gate driving output and the GaN power tube gate will be fixed inside the package, and the charging speed of the power tube gate and the EMI optimization cannot be improved from the outside. On the other hand, for the intelligent gate driver with segmented control, since the turn-on process of the GaN device is very short (< 10 ns), the limited response speed of the gate driver makes it difficult to change the charging current of the power tube in time, and a high-frequency controller with extremely high resolution is used, thereby increasing the chip cost.
Another strategy for GaN power tube gate drive is to charge control the miller platform as the sampled information, but capturing the actual miller platform is difficult because it is related to the load current, i.e., a sample-and-hold circuit is required.
Disclosure of Invention
Aiming at the problem that high-speed level and current change are generated in a circuit due to the fact that the GaN power tube is switched on and off quickly to cause EMI noise, and the defects that a grid driver and the GaN power tube are packaged in a mixed mode through SiP in a first traditional GaN power tube grid driving scheme, so that a current-limiting resistor is fixed in the package and cannot be adjusted freely, high cost is caused, and an actual Miller platform is difficult to obtain in a second traditional GaN power tube grid driving scheme.
The technical scheme of the invention is as follows:
a GaN power tube grid driving circuit with controllable starting rate comprises an internal power generation module, a grid driving module, a charge pump module, an external capacitor and a current-limiting resistor,
the grid driving module is used for generating a GaN power tube grid driving signal according to an external control signal to control the GaN power tube grid to charge and discharge;
one end of the current-limiting resistor is connected with the power supply end of the gate driving module, and the other end of the current-limiting resistor is grounded after passing through the external capacitor;
the internal power supply generation module is used for generating a first power supply, the internal power supply generation module comprises a power adjusting tube controlled by the charge pump module, when the power adjusting tube is conducted, the internal power supply generation module connects the first power supply to the power supply end of the grid driving module, the first power supply and the external capacitor jointly supply power to the grid driving module, and the grid charging rate of the GaN power tube is accelerated; when the power adjusting tube is disconnected, the internal power supply generation module disconnects the first power supply from the power supply end of the grid driving module, and the external capacitor only supplies power to the grid driving module, so that the grid charging rate of the GaN power tube is reduced;
the charge pump module is used for disconnecting the power adjusting tube before the GaN power tube is conducted, and conducting the power adjusting tube after the GaN power tube is conducted and a set time delay is carried out, wherein the setting of the time delay is determined according to the resistance value of the current limiting resistor.
Specifically, the gate driving module is configured to phase-connect the external control signal with an under-voltage signal to obtain a gate driving control signal, where the under-voltage signal is used to control the GaN power tube to be turned off when the first power supply is lower than an under-voltage threshold.
Specifically, the charge pump module comprises a short pulse generating unit, a first stage bootstrap inverter unit, a second stage bootstrap inverter unit and a control switch tube,
the short pulse generating unit comprises a first capacitor, a second capacitor, a first resistor, a second resistor and a first NMOS transistor,
one end of the first capacitor is connected with the gate drive control signal, and the other end of the first capacitor, which is taken as the output end of the short pulse generation unit, is connected with the drain electrode of the first NMOS tube and is grounded through the first resistor;
one end of the second resistor is connected with the GaN power tube gate driving signal, and the other end of the second resistor is connected with the grid electrode of the first NMOS tube and is grounded through the second capacitor;
the source electrode of the first NMOS tube is grounded;
the first stage bootstrap phase inverter unit comprises a third resistor, a third capacitor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor,
the grid-drain short circuit of the fifth NMOS tube is connected with a second power supply, and the source electrode of the fifth NMOS tube is connected with one end of a third resistor and one end of a third capacitor;
the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube and the output end of the short pulse generating unit, the drain electrode of the second NMOS tube is connected with the grid electrode of the fourth NMOS tube and the other end of the third resistor, and the source electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube and grounded;
the drain electrode of the fourth NMOS tube is connected with the second power supply, and the source electrode of the fourth NMOS tube is connected with the other end of the third capacitor and the drain electrode of the third NMOS tube and serves as the output end of the first-stage bootstrap phase inverter unit;
the second stage bootstrap phase inverter unit comprises a fourth resistor, a fourth capacitor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor,
the grid-drain short circuit of the sixth NMOS tube is connected with the second power supply, and the source electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube, one end of a fourth resistor and one end of a fourth capacitor;
the grid electrode of the seventh NMOS tube is connected with the grid electrode of a fourth NMOS tube in the primary bootstrap phase inverter unit, and the drain electrode of the seventh NMOS tube is connected with the second power supply;
the grid electrode of the ninth NMOS tube is connected with the grid electrode of the tenth NMOS tube and the output end of the first-stage bootstrap phase inverter unit, the drain electrode of the ninth NMOS tube is connected with the grid electrode of the eighth NMOS tube, the grid electrode of the control switch tube and the other end of the fourth resistor, and the source electrode of the ninth NMOS tube is connected with the source electrode of the tenth NMOS tube and grounded;
the drain electrode of the eighth NMOS tube is connected with the source electrode of the control switch tube, and the source electrode of the eighth NMOS tube is connected with the other end of the fourth capacitor and the drain electrode of the tenth NMOS tube;
the power adjusting tube is an NMOS tube, the drain electrode of the power adjusting tube is connected with an external power supply, and the source electrode of the power adjusting tube outputs the first power supply; the drain electrode of the control switch tube is connected with the grid electrode of the power adjusting tube, and the source electrode of the control switch tube is connected with the source electrode of the power adjusting tube.
Specifically, the charge pump module is controlled by an enable signal to work or not.
Specifically, the second power supply is generated by the internal power generation module.
Specifically, the gate driving module comprises a Schmitt trigger, a NAND gate, a first inverter, a logic unit, a first PMOS tube and an eleventh NMOS tube,
the input end of the Schmitt trigger is connected with the external control signal, and the output end of the Schmitt trigger is connected with the first input end of the NAND gate;
the second input end of the NAND gate is connected with the undervoltage signal, and the output end of the NAND gate is connected with the input end of the first phase inverter and the input end of the logic unit;
the output end of the first inverter outputs the gate drive control signal;
the logic unit is used for processing the output end signal of the NAND gate and then driving the grids of the first PMOS tube and the eleventh NMOS tube;
the source electrode of the first PMOS tube is connected with the power supply end of the gate driving module, and the drain electrode of the first PMOS tube is connected with the drain electrode of the eleventh NMOS tube and outputs the gate driving signal of the GaN power tube;
and the source electrode of the eleventh NMOS tube is grounded.
The working principle of the invention is as follows:
the invention obtains the conduction condition of the GaN power tube by using the control signal in the charge pump module sampling gate driving module, and the power adjusting tube M of the internal power generation module is used before the GaN power tube is started 1 Short-circuiting, disconnecting the first power supply V DD_dri The power supply end of the grid driving module is connected, so that the internal power generation module loses the function of supplying power to the chip, and the GaN power tube can only pass through the external capacitor C before the GaN power tube is started and the Miller platform is finished OUT Charging its grid, and adding external capacitor C OUT A current limiting resistor R is added between the grid driving module and the power supply end C Current limiting resistor R C The power-on speed of the GaN power tube will be controlled. After the grid voltage of the GaN power tube sampled by the charge pump module reaches the threshold voltage and is delayed for a set period of time, the power adjusting tube M of the internal power generation module 1 Switching in again to output the first power supply V DD_dri To the power supply end of the gate drive module, the internal power generation module recovers the power supply function of the chip and the first power supply V DD_dri And an external capacitor C OUT And jointly charging the grid electrode of the GaN power tube, and accelerating the charging of the GaN power tube to a final stable state.
The beneficial effects of the invention are as follows: the invention provides a novel sectional driving mode, wherein an end point of a Miller platform of a GaN power tube is simulated by setting RC (resistance capacitance) time delay, and an external capacitor C is used before the Miller platform is finished OUT Through a current limiting resistor R C Charging GaN power tube grid electrode, current limiting resistor R C On one hand, the charging speed of the grid electrode of the power tube can be limited, the large stress of the grid electrode of the GaN power tube caused by large current is prevented, the reliability of grid driving is improved, and on the other hand, the change of rapid voltage and current can be reduced by slowing down the starting speed of the GaN power tube; meanwhile, after the Miller platform is withdrawn, the GaN power tube grid electrode is charged with a large current to quickly and completely open the GaN power tube, so that the generation of the high-voltage GaN power tube in the opening process can be effectively reduced on the basis of sacrificing a certain opening speedLarger dv/dt and di/dt, thereby reducing the EMI noise of the chip.
Drawings
Fig. 1 is a schematic diagram of a conventional GaN gate driving chip in SiP package.
Fig. 2 is a structural diagram of a gate driving circuit of a GaN power transistor with a controllable turn-on rate according to the present invention.
Fig. 3 is a circuit diagram of a charge pump module in a GaN power transistor gate driving circuit with a controllable turn-on rate according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a relationship between dv/dt and a current limiting resistor in a GaN power transistor gate driving circuit with a controllable turn-on rate according to the present invention.
Detailed Description
The following detailed description of the invention, taken in conjunction with the drawings, illustrates the principles and embodiments of the invention.
The invention provides a GaN power tube gate drive circuit with controllable starting rate, which comprises an internal power generation module, a gate drive module, a charge pump module and an external capacitor C out And a current limiting resistor R C Wherein the internal power generation module, the gate drive module and the charge pump module are integrated in the chip, and the external capacitor C out And a current limiting resistor R C The current limiting resistor is arranged outside the chip, and the problem that the current limiting resistor cannot be freely adjusted when the gate driver and the GaN power tube are packaged in a mixed mode through the traditional SiP packaging is solved.
The internal power supply generation module is used for generating a first power supply V for supplying power to the gate drive module DD_dri First power supply V DD_dri Receiving power adjusting tube M 1 And controlling whether to connect the power supply end of the gate driving module. In some embodiments, the remaining internal power supplies are, for example, a second power supply V for powering the charge pump module DD Or may be generated by an internal power generation module.
The grid driving module is used for generating a GaN power tube grid driving signal V according to an external control signal IN OUT For controlling charging and discharging of the grid electrode of the GaN power tube, the grid drive module can be designed by adopting the existing grid drive logic, as shown in FIG. 2An implementation structure of the gate driving module is provided, IN this embodiment, the under-voltage protection is combined, the under-voltage signal UVLO and the external control signal IN are connected to the input of the first phase inverter and the logic unit after passing through the nand gate, and the logic unit processes the output end signal of the nand gate and then is used for driving the pull-up PMOS transistor, i.e., the first PMOS transistor M P And a pull-down NMOS transistor M N The output end of the first inverter outputs a gate drive control signal V C Gate drive control signal V C Is a square wave signal, a gate drive control signal V C And GaN power tube grid driving signal V OUT Are signals that characterize the gate drive of the GaN power tube.
The charge pump module samples signals representing GaN power tube gate drive to control whether the internal power supply generation module generates a first power supply V DD_dri Supplying power to the gate drive module to control the gate charging rate of the GaN power tube, and turning off the power adjusting tube M before the GaN power tube is turned on 1 Only by externally hanging electricity C out The grid driving module is powered by adding a current limiting resistor R C Limiting the magnitude of the grid charging current of the GaN power tube to enable the grid charging rate of the GaN power tube to be slower; after the GaN power tube is conducted and set time delay is passed, the power regulating tube M is connected with the GaN power tube 1 Conducting, wherein the Miller platform of the GaN power tube is considered to be finished, and the first power supply V supplies power to the GaN power tube DD_dri And an external capacitor C out The grid driving module is powered together, and the grid charging rate of the GaN power tube is accelerated. An enable signal En may also be added to control whether the charge pump module operates as shown in fig. 2.
The operation of the present invention will be described in detail with reference to the specific structure of the charge pump module in the embodiment shown in fig. 3.
As shown in FIG. 3, the charge pump module includes a short pulse generating unit, a first-stage bootstrap inverter unit, a second-stage bootstrap inverter unit and a control switch tube M C The short pulse generating unit comprises a first capacitor C 3 A second capacitor C 4 A first resistor R 7 A second resistor R 8 And a first NMOS transistor M 7 First capacitor C 3 One end is connected with a gate drive control signal V C The other end of the short pulse generating unit is connected with the first NMOS tube M as the output end of the short pulse generating unit 7 And through a first resistor R 7 Then grounding; a second resistor R 8 One end is connected with a grid driving signal V of the GaN power tube OUT The other end is connected with a first NMOS tube M 7 And through a second capacitor C 4 The back is grounded; first NMOS transistor M 7 Is grounded.
Wherein the first resistor R 7 In order to initialize the resistor, the output end of the short pulse generating unit, namely the A node, is pulled to the ground potential in the initial state, and the short pulse generating unit samples a grid driving control signal V C Passes through the first capacitor C 3 The coupling action of (b) pulls the a node high. A second resistor R 8 And a second capacitor C 4 Forming an RC delay structure for setting delay time; gaN power tube grid driving signal V OUT After reaching the threshold voltage, passes through a second resistor R 8 And a second capacitor C 4 The formed RC time delay structure leads the first NMOS transistor M to be connected with the second NMOS transistor M 7 Is turned on and pulls the point A low again, so that the rising edge of the short pulse generated by the short pulse generating unit is the sampled gate drive control signal V C After the GaN power tube reaches the threshold voltage and the short pulse falling edge is generated after RC time delay, the power tube Miller platform can be considered to be finished after the short pulse is finished. A second resistor R 8 And a second capacitor C 4 The RC delay structure is a low-pass filter for setting the delay time required by the invention, and the delay time is determined by the external resistor R C The value range is determined reasonably. Short pulse rising edge due to sampling gate drive control signal V C Therefore, the first capacitor C is not required 3 Or by the gate drive control signal V C Pull node A high, but if first capacitor C is removed 3 Then, the first NMOS tube M is started when the GaN power tube is started 7 When the power transistor is turned on, the node A is pulled down again, so that a gate drive signal is pulled down, and the power transistor is turned off mistakenly, therefore, the first capacitor C is arranged 3 。
As shown in FIG. 3, the first stage bootstrapped inverter cell includes a third resistor R 9 A third capacitor C 5 A second NMOS transistor M 8 And the third NMOS transistor M 9 And the fourth NMOS tube M 10 And a fifth NMOS transistor M 11 Fifth NMOS transistor M 11 Is connected with a second power supply V DD The source of which is connected with a third resistor R 9 And a third capacitor C 5 One end of (a); second NMOS transistor M 8 Is connected with a third NMOS tube M 9 And a drain electrode of the short pulse generating unit is connected with the fourth NMOS transistor M 10 And a third resistor R 9 The source electrode of the other end of the first NMOS tube is connected with a third NMOS tube M 9 The source of (a) is grounded; fourth NMOS transistor M 10 Is connected with a second power supply and a second power supply V DD The source of which is connected to a third capacitor C 5 And the other end of the third NMOS tube M 9 And as the output of the first stage bootstrapped inverter cell.
The first stage bootstrap phase inverter unit shapes the short pulse signal generated by the node A, and the fifth NMOS transistor M 11 Is a third capacitor C 5 Charging, the fourth NMOS transistor M 10 An upper tube of the inverter, a third NMOS tube M 9 Is a lower tube of the inverter, and a third resistor R 9 Is a decoupling resistor. When the A node is raised, the second NMOS tube M 8 And a third NMOS transistor M 9 Open, and connect the C node (second NMOS transistor M) 8 Drain terminal of) and an output terminal V which is a first stage bootstrap inverter unit CK Pull-down, node B (fifth NMOS transistor M) 11 Source terminal of) to about VDD-Vth of the fifth NMOS transistor M 11 Threshold voltage of, fourth NMOS transistor M 10 The turn-off is realized, and the power consumption of the inverter is the third resistor R 9 Resulting in power dissipation if the third resistor R is removed 9 And a second NMOS transistor M 8 Then the fourth NMOS transistor M 10 Will always be kept on, when the A node is turned up, the fourth NMOS transistor M 10 Will generate larger current in saturation region, therefore the invention sets the third resistor R 9 And a second NMOS transistor M 8 The loss of the inverter can be reduced. The A node is turned down to enable the second NMOS tube M 8 And a third NMOS transistor M 9 Off, third capacitance C 5 The stored charge passes through the third resistor R 9 Charging the C node, and a fourth NMOS transistor M 10 Tube open, third capacitance C 5 The output end V of the first stage bootstrap phase inverter unit is used as a bootstrap capacitor CK To a second power supply V DD And (4) electric potential.
As shown in FIG. 3, the second stage bootstrapped inverter cell includes a fourth resistor R 10 A fourth capacitor C 6 And a sixth NMOS transistor M 12 And a seventh NMOS transistor M 13 And the eighth NMOS transistor M 14 And a ninth NMOS transistor M 15 And a tenth NMOS transistor M 16 Sixth NMOS transistor M 12 Is connected with a second power supply V DD The source electrode of the NMOS transistor is connected with a seventh NMOS transistor M 13 Source electrode of (1), fourth resistor R 10 And a fourth capacitor C 6 One end of (a); seventh NMOS transistor M 13 The grid electrode of the first-stage bootstrap inverter unit is connected with a fourth NMOS tube M in the first-stage bootstrap inverter unit 10 A drain electrode of the grid electrode is connected with a second power supply V DD (ii) a Ninth NMOS transistor M 15 The grid of the NMOS transistor is connected with a tenth NMOS transistor M 16 The grid of the first stage bootstrap phase inverter unit and the output end of the first stage bootstrap phase inverter unit, and the drain electrode of the first stage bootstrap phase inverter unit is connected with an eighth NMOS tube M 14 Grid and control switch tube M C And a fourth resistor R 10 The source of the other end of (2) is connected with a tenth NMOS tube M 16 The source of (2) is grounded; eighth NMOS transistor M 14 Drain electrode of the switch tube M is connected with the control switch tube M C A source electrode of the first capacitor C is connected with the source electrode of the second capacitor C 6 And the other end of the tenth NMOS transistor M 16 A drain electrode of (1); power adjusting tube M 1 Is an NMOS tube, and has its drain connected with an external power supply V CC A source thereof outputting a first power supply V DD_dri (ii) a Control switch tube M C Drain electrode of the transistor M is connected with a power adjusting tube M 1 A source electrode of the grid electrode is connected with the power adjusting tube M 1 Of the substrate.
Sixth NMOS transistor M in second-stage bootstrap phase inverter unit 12 Is a bootstrap capacitor, i.e. a fourth capacitor C 6 Performing initialization power-on, and bootstrapping a fourth capacitor C in the inverter unit at the second stage 6 A fourth resistor R 10 And a ninth NMOS transistor M 15 And the eighth NMOS transistor M 14 And a tenth NMOS transistor M 16 And a third capacitor C in the first stage bootstrap inverter unit 5 A third resistor R 9 A second NMOS transistor M 8 And the third NMOS transistor M 9 And a fourth NMOS transistor M 10 The function is completely the same, and the seventh NMOS tube M 13 The grid is controlled by the C node of the first stage bootstrap phase inverter unit, when the output of the first stage bootstrap phase inverter unit is V DD While, the fourth capacitor C 6 Charging is carried out, and the C node is caused by the third capacitor C 5 Is raised to 2V DD Level of Vth, so that the seventh NMOS transistor M is turned on 13 Pressed into the deep linear region, the D node can thus be charged to V DD The sixth NMOS transistor M is reduced 12 Loss of charging potential of node D by threshold voltage of tube, and third capacitor C 5 Also a bootstrap capacitor. When the output of the first stage bootstrapped inverter cell is low, the C node and V CK Turned down, the seventh NMOS transistor M 13 Tube cut-off, fourth capacitance C 6 Raising the potential of the node D, and connecting the eighth NMOS transistor M 14 The tube is pressed into the deep linear region. M C The transistor is a charge pump control switch transistor, a grid control signal of the charge pump control switch transistor is provided by a second stage bootstrap phase inverter unit of the charge pump module, and a control switch transistor M C The drain electrode and the source electrode of the power supply are respectively connected with a power adjusting tube M in the internal power supply generation module 1 The pull-up transistor of the second stage bootstrap inverter unit, namely the eighth NMOS transistor M 14 Drain electrode and control switch tube M C The source is connected to the same potential because of the external capacitor C OUT When the grid electrode of the GaN power tube is charged, the first power supply V DD_dri Fail to obtain sufficient charge compensation and drop if the eighth NMOS transistor M 14 Pipe connected with second power supply V DD Then will control the switch tube M C The gate-source voltage of the transistor is instantly increased to control the switch tube M C The risk of gate-source breakdown is generated, so the eighth NMOS transistor M is adopted by the invention 14 The drain terminal of the first power supply V DD_dri Can clamp and control the switch tube M C Gate source voltage of the control switch tube M C Is not broken down.
In this embodiment, during the GaN power transistor turn-on process, the charge pump module samples the gate driving control signal V at the same time C And GaN power tube grid driving signal V OUT Generating short pulse signal and further controlling and changing control switch tube M C The grid end control signal of the GaN power tube controls the switch tube M before the GaN power tube is conducted C Pressing into deep linear region, thereby being equivalent to pressing power adjusting tube M in internal power generation module 1 The grid electrode and the source electrode are connected by the on-resistance of the MOS tube, and the power adjusting tube M can be connected by the on-resistance with very low resistance 1 When the grid drive module fails, the starting signal of the grid drive module is transmitted to the GaN power tube, the grid electrode of the GaN power tube is charged, but the internal power supply generation module fails, so that the first power supply V cannot be provided DD_dri The GaN power tube grid is charged, so that the external voltage-stabilizing capacitor, namely the external capacitor C, can only be used for charging the GaN power tube grid out Charging is carried out, and an output pin V of the internal power supply generation module DD_dri And an external capacitor C out A current limiting resistor R is added between C The function is to limit the magnitude of the charging current of the grid electrode of the GaN power tube, thereby controlling di/dt and dv/dt when the GaN power tube is opened and the current-limiting resistor R C The setting is easily adjusted outside the chip, and different current-limiting resistors R can be replaced according to different working requirements of the chip C The method can adjust the dv/dt which is larger when the GaN power tube is started, and achieve the purpose of optimizing the EMI of the chip.
In the power tube starting process, the charge pump module simultaneously samples a GaN power tube gate drive signal V OUT GaN power tube gate drive signal V OUT The level of the GaN power tube reaches the threshold voltage of the GaN power tube and then passes through a second resistor R 8 And a second capacitor C 4 The set section of RC time delay forming the RC time delay structure can be regarded as that the Miller platform of the GaN power tube is finished, and at the moment, the charge pump module is controlled to switch the tube M C Power adjusting tube M of turn-off and internal power generation module 1 Resume charging function, first power supply V DD_dri And an external capacitor C out And rapidly charging the grid level of the GaN power tube together to complete the electrifying process of the GaN power tube.
External resistor R C And dv/dt at the time of GaN power tube turn-on are as follows:
dV sw /dt≈(V Cout -V GS,Miller )/[(R C +R dson )·C GD ]
wherein d is Vsw Is the drain terminal dv/dt, V of the GaN power tube cout Is an external capacitor C out Voltage of V GS,Miller Is the voltage of Miller platform, R, of GaN power tube C Is an externally-hung current-limiting resistor R dson Is a drive-stage pull-up PMOS transistor M P On-resistance of (C) GD The equivalent grid leakage capacitance of the GaN power tube.
FIG. 4 shows a schematic diagram of the relationship between dv/dt and the current-limiting resistance during the GaN power transistor turn-on process, and the external resistor R C The adjustment of dv/dt when the GaN power tube is turned on can exceed 5 times when the GaN power tube is turned from 0 omega to 10 omega, thereby effectively reducing EMI and switching noise of the power GaN power tube in the process of hard switching.
Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its aspects.
Claims (6)
1. A GaN power tube grid drive circuit with controllable turn-on rate is characterized in that the GaN power tube grid drive circuit comprises an internal power generation module, a grid drive module, a charge pump module, an external capacitor and a current-limiting resistor,
the grid driving module is used for generating a GaN power tube grid driving signal according to an external control signal to control the charging and discharging of the GaN power tube grid;
one end of the current-limiting resistor is connected with the power supply end of the gate driving module, and the other end of the current-limiting resistor is grounded after passing through the external capacitor;
the internal power supply generation module is used for generating a first power supply, the internal power supply generation module comprises a power adjusting tube controlled by the charge pump module, when the power adjusting tube is conducted, the internal power supply generation module connects the first power supply to the power supply end of the grid driving module, the first power supply and the external capacitor jointly supply power to the grid driving module, and the grid charging rate of the GaN power tube is accelerated; when the power adjusting tube is disconnected, the internal power supply generation module disconnects the first power supply from the power supply end of the grid driving module, and the external capacitor only supplies power to the grid driving module, so that the grid charging rate of the GaN power tube is reduced;
the charge pump module is used for disconnecting the power adjusting tube before the GaN power tube is conducted, conducting the power adjusting tube after the GaN power tube is conducted and set time delay is carried out, wherein the setting of the time delay is determined according to the resistance value of the current limiting resistor.
2. The gate driving circuit of claim 1, wherein the gate driving module is configured to phase-intersect the external control signal with an under-voltage signal to obtain a gate driving control signal, and wherein the under-voltage signal is configured to control the GaN power transistor to be turned off when the first power supply is lower than an under-voltage threshold.
3. The GaN power tube gate driving circuit with controllable turn-on rate according to claim 2, wherein the charge pump module comprises a short pulse generation unit, a first stage bootstrap inverter unit, a second stage bootstrap inverter unit and a control switch tube,
the short pulse generating unit comprises a first capacitor, a second capacitor, a first resistor, a second resistor and a first NMOS transistor,
one end of the first capacitor is connected with the gate drive control signal, and the other end of the first capacitor, which is taken as the output end of the short pulse generation unit, is connected with the drain electrode of the first NMOS tube and is grounded through the first resistor;
one end of the second resistor is connected with the GaN power tube gate driving signal, and the other end of the second resistor is connected with the grid electrode of the first NMOS tube and is grounded through the second capacitor;
the source electrode of the first NMOS tube is grounded;
the first stage bootstrap phase inverter unit comprises a third resistor, a third capacitor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor,
the grid drain of the fifth NMOS tube is in short circuit and is connected with a second power supply, and the source electrode of the fifth NMOS tube is connected with one end of a third resistor and one end of a third capacitor;
the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube and the output end of the short pulse generating unit, the drain electrode of the second NMOS tube is connected with the grid electrode of the fourth NMOS tube and the other end of the third resistor, and the source electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube and grounded;
the drain electrode of the fourth NMOS tube is connected with the second power supply, and the source electrode of the fourth NMOS tube is connected with the other end of the third capacitor and the drain electrode of the third NMOS tube and serves as the output end of the first-stage bootstrap phase inverter unit;
the second stage bootstrap phase inverter unit comprises a fourth resistor, a fourth capacitor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor,
the grid drain of the sixth NMOS tube is in short circuit and is connected with the second power supply, and the source electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube, one end of a fourth resistor and one end of a fourth capacitor;
the grid electrode of the seventh NMOS tube is connected with the grid electrode of a fourth NMOS tube in the primary bootstrap phase inverter unit, and the drain electrode of the seventh NMOS tube is connected with the second power supply;
the grid electrode of the ninth NMOS tube is connected with the grid electrode of the tenth NMOS tube and the output end of the first-stage bootstrap phase inverter unit, the drain electrode of the ninth NMOS tube is connected with the grid electrode of the eighth NMOS tube, the grid electrode of the control switch tube and the other end of the fourth resistor, and the source electrode of the ninth NMOS tube is connected with the source electrode of the tenth NMOS tube and grounded;
the drain electrode of the eighth NMOS tube is connected with the source electrode of the control switch tube, and the source electrode of the eighth NMOS tube is connected with the other end of the fourth capacitor and the drain electrode of the tenth NMOS tube;
the power adjusting tube is an NMOS tube, the drain electrode of the power adjusting tube is connected with an external power supply, and the source electrode of the power adjusting tube outputs the first power supply; the drain electrode of the control switch tube is connected with the grid electrode of the power adjusting tube, and the source electrode of the control switch tube is connected with the source electrode of the power adjusting tube.
4. The gate driving circuit of claim 3, wherein the charge pump module is controlled by an enable signal to operate.
5. The GaN power tube gate driving circuit with controllable turn-on rate of claim 3, wherein the second power supply is generated by the internal power generation module.
6. The gate drive circuit of any one of claims 2-5, wherein the gate drive module comprises a Schmitt trigger, a NAND gate, a first inverter, a logic unit, a first PMOS transistor and an eleventh NMOS transistor,
the input end of the Schmitt trigger is connected with the external control signal, and the output end of the Schmitt trigger is connected with the first input end of the NAND gate;
the second input end of the NAND gate is connected with the undervoltage signal, and the output end of the NAND gate is connected with the input end of the first phase inverter and the input end of the logic unit;
the output end of the first inverter outputs the gate drive control signal;
the logic unit processes the output end signal of the NAND gate and then is used for driving the grids of the first PMOS tube and the eleventh NMOS tube;
the source electrode of the first PMOS tube is connected with the power supply end of the gate driving module, and the drain electrode of the first PMOS tube is connected with the drain electrode of the eleventh NMOS tube and outputs the gate driving signal of the GaN power tube;
and the source electrode of the eleventh NMOS tube is grounded.
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| CN114785099B (en) * | 2022-06-17 | 2022-09-13 | 深圳芯能半导体技术有限公司 | Grid driving circuit |
| CN116545422B (en) * | 2023-06-28 | 2023-09-05 | 杰夫微电子（四川）有限公司 | Ultra-low power consumption load switch based on timer control and control method thereof |
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