CN114244148B - Output driving device of switch power supply - Google Patents
Output driving device of switch power supply Download PDFInfo
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- CN114244148B CN114244148B CN202111478948.4A CN202111478948A CN114244148B CN 114244148 B CN114244148 B CN 114244148B CN 202111478948 A CN202111478948 A CN 202111478948A CN 114244148 B CN114244148 B CN 114244148B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to a switching power supply output driving device, which comprises a multistage ladder driving unit, wherein the multistage ladder driving unit can charge a grid electrode of a first NMOS tube according to the grid voltage of the first NMOS tube of a switching power supply, and turn on the first NMOS tube; each step driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the input end of the digital logic unit receives a signal for controlling the step driving unit. The invention can effectively reduce the power consumption and improve the working reliability.
Description
Technical Field
The invention relates to a switching power supply output driving device.
Background
The switching power supply is widely applied to the fields of electronic and electrical equipment and household appliances. The development of the novel power device promotes the high frequency of the switching power supply, the benefit brought by the high frequency is that the switching power supply device is miniaturized unprecedentedly, the switching power supply is brought into wider fields, particularly the application in the high and new technical fields, the miniaturization and the portability of the high and new technical products are promoted, and in addition, the development and the application of the switching power supply have profound significance in the aspects of saving resources and protecting environment. The power MOS tube and IGBT can make the working frequency of the small and medium-sized switching power supply reach 400kHz (AC/DC), 1MHz (DC/DC), and the development of control technology and the production of special control chips, so that the power supply circuit is greatly simplified, and the dynamic performance and reliability of the switching power supply are greatly improved.
The development of the switching power supply to the integration direction is a main trend in the future, the power density is larger and larger, and the requirements on the process are also higher and higher. Before there is no new breakthrough in semiconductor devices and magnetic materials, significant technological advances may be difficult to achieve, and technological innovation focuses on how to improve the efficiency and reliability of switching power supplies. In order to improve the efficiency of the switching power supply, the switching loss and the conduction loss of the output power tube of the switching power supply must be reduced, and in order to improve the reliability of the switching power supply, the output power tube of the switching power supply must be effectively protected. Therefore, it is required to develop a switching power supply output driving device capable of reducing energy loss of a switching power supply power tube as much as possible and improving reliability of the power tube.
The switching frequency of the bipolar transistor adopted by the power tube in the switching power supply in the market at present can reach tens of kilohertz, and the switching power supply conversion frequency of the MOS transistor can reach hundreds of kilohertz. Most switching power supply output power transistors use MOS transistors because of the high frequency of the switching power supply. The MOS transistor has the advantages of low on-resistance and large load current, and is very suitable for being used as an output device of a switching power supply.
At present, the existing switching power supply output driving device mainly has four types: the first is a direct driving device of a power supply chip, because the driving capability of different chips is different, if the power supply chip has no relatively large driving peak current, the conduction speed of the tube is relatively slow, which can lead to the rapid increase of the switching loss of the switching power supply and reduce the output efficiency. The second is a push-pull output driving device, which has the advantages of providing enough current driving capability, rapidly completing the charging process of the grid electrode input capacitor of the MOS power tube, improving the switching speed, but not matching the rising slope of the grid electrode voltage of the NMOS tube, so that the overshoot and oscillation of the output waveform caused by the excessive instant rising slope of the grid electrode driving voltage of the MOS tube can generally occur, thereby greatly reducing the reliability of the switching power supply and increasing the EMI problem. The third is to accelerate the turn-off driving device, the driving circuit can provide a low impedance path for the rapid discharge of the capacitance charge between the grid and the source of the MOS power tube at the moment of turn-off of the power tube, and a resistor and a diode are usually connected in parallel on the driving resistor, so the device is only beneficial to the rapid turn-off of the MOS power tube, but can not effectively control the turn-on state of the MOS power tube, and can not substantially improve the output efficiency of the switching power supply. The fourth is an isolation driving device, which is used for meeting the driving of a few high-end MOS tubes, needs to be driven by a transformer, can separate direct current and is communicated, but the magnetic core of the device is saturated frequently and easily, and meanwhile, inductance and capacitance on a PCB (printed circuit board) are required to be matched, so that the manufacturing cost is high, and the device is rarely used in the market.
Therefore, there is a need to develop a switching power supply output driving device that overcomes the above-mentioned drawbacks of the various driving devices. The device needs not only can reduce the energy loss of the MOS power tube to the greatest extent to improve the output efficiency, but also can avoid overshoot and oscillation of an output waveform to improve the reliability of the switching power supply and reduce the EMI problem, and meanwhile, the driving device needs to comprise a temperature compensation function to ensure that the driving device can keep constant driving capacity in a full temperature range, and the driving device also needs to comprise a grid voltage clamping protection function and a dead time control function, so that the output efficiency and the use reliability of the switching power supply can be greatly improved.
Disclosure of Invention
The invention aims to provide a switching power supply output driving device which can effectively reduce power consumption and improve working reliability.
The technical scheme for realizing the purpose of the invention comprises the following steps:
the switching power supply output driving device comprises a multistage ladder driving unit, wherein the multistage ladder driving unit is used for charging a grid electrode of a first NMOS tube of a switching power supply according to the grid electrode voltage of the first NMOS tube so as to turn on the first NMOS tube;
each step driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the digital logic unit is used for receiving signals to control the step driving units.
Further, the driving circuit of the step driving unit comprises a constant current source, a first PMOS tube (P1), a second PMOS tube (P11) and a third PMOS tube (P12), wherein the first PMOS tube (P1) and the second PMOS tube (P11) form a mirror current circuit, and the drain electrode of the first PMOS tube (P1) is the output end of the driving circuit and is connected with the grid electrode of the first NMOS tube; the constant current source is connected with the drain electrode of the third PMOS tube (P12), and the source electrode of the third PMOS tube (P12) is connected with the drain electrode of the second PMOS tube (P11).
Further, the digital logic unit also comprises a voltage detection unit, wherein the voltage detection unit is connected with the grid electrode of the first NMOS tube and the first input end of the digital logic unit and is used for starting a corresponding step driving unit to charge the grid electrode of the first NMOS tube according to the voltage of the grid electrode of the first NMOS tube.
Further, the device also comprises a second NMOS tube, wherein the drain electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube and is used for discharging the grid electrode of the first NMOS tube so as to close the first NMOS tube.
Further, the digital logic unit also comprises a dead time control unit, wherein the dead time control unit generates a first PMW signal for controlling the step driving unit and a second PMW signal for controlling the second NMOS tube, and the first PMW signal is output to the digital logic unit; the dead time control unit controls the step driving unit and the second NMOS tube to enable the charging and discharging of the grid electrode of the first MOS tube not to be in the same time period.
Further, the dead time control unit comprises a delay circuit composed of a resistor and a capacitor, and a time interval exists between the generated first PMW signal and the generated second PMW signal through the delay circuit, so that the charging and discharging of the grid electrode of the first MOS tube are not in the same time period.
Further, the temperature compensation unit is used for performing temperature compensation on the charging current output by the step driving unit.
Further, the device further comprises a voltage clamping unit, wherein the voltage clamping unit is used for clamping the grid voltage of the first NMOS tube.
Further, the multistage step driving unit is used for providing multistage charging current for the grid electrode of the first NMOS tube, each stage of step driving unit correspondingly provides one stage of charging current, and each stage of charging current is increased stepwise.
Further, when the first NMOS transistor gate voltage exceeds the set threshold, the multi-stage step driving unit increases the charging current provided to the first NMOS transistor gate momentarily, for quickly avoiding the miller plateau voltage of the first NMOS transistor gate.
The invention has the beneficial effects that:
the multi-stage ladder driving unit can charge the grid electrode of the first NMOS tube according to the grid voltage of the first NMOS tube of the switching power supply, and the first NMOS tube is started; each step driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the input end of the digital logic unit receives a signal for controlling the step driving unit. According to the invention, the first NMOS tube grid electrode of the switching power supply is charged through the multistage step driving unit according to the first NMOS tube grid electrode voltage, so that the loss can be reduced to the greatest extent, the output efficiency is improved, overshoot and oscillation of an output waveform can be avoided, the reliability of the switching power supply is improved, and the EMI problem is reduced.
The digital logic unit comprises a voltage detection unit, wherein the input end of the voltage detection unit is connected with the grid electrode of a first NMOS tube, the output end of the voltage detection unit is connected with the first input end of the digital logic unit, and the voltage detection unit starts a corresponding step driving unit to charge the grid electrode of the first NMOS tube according to the voltage of the grid electrode of the first NMOS tube. According to the invention, the voltage detection unit detects the grid voltage of the first NMOS tube, and the corresponding step driving unit is started to charge the grid of the first NMOS tube according to the grid voltage of the first NMOS tube, so that the power consumption is further effectively reduced, and the working reliability is improved.
The temperature compensation unit is used for performing temperature compensation on the charging current output by the step driving unit, and the device can drive the first NMOS tube to stably work in a full temperature range through the temperature compensation unit, so that the problem of abnormal driving caused by severe temperature change is avoided. The invention comprises a voltage clamping unit, wherein the voltage clamping unit is used for clamping the grid voltage of the first NMOS tube, and the voltage clamping unit clamps the grid voltage of the first NMOS tube, so that the problem of damage to the transistor caused by overhigh grid voltage of the first NMOS tube is avoided, and the working reliability is further ensured.
The dead time control unit is used for controlling the step driving unit and the second MOS transistor so that the first MOS transistor grid charge and the first MOS transistor grid discharge are not in the same time period; the dead time control unit receives a PMW signal for controlling the switching power supply and comprises a delay circuit composed of a resistor and a capacitor, and a time interval is reserved between the generated first PMW signal and the generated second PMW signal through the delay circuit, so that the first MOS transistor grid electrode charge and the first MOS transistor grid electrode discharge are not in the same time period. The invention realizes the output dead time control function through the dead time control unit, avoids the simultaneous conduction of the first PMOS tube (output upper tube) and the second NMOS tube (output lower tube) of the step driving unit, further avoids the risk that the transistor is burnt out due to high current when the power supply is directly communicated, and further ensures the working reliability.
The multistage ladder driving unit can provide multistage charging current for the grid electrode of the first NMOS tube, each stage of ladder driving unit correspondingly provides one stage of charging current, each stage of charging current is increased stepwise, when the voltage of the grid electrode of the first NMOS tube exceeds a set threshold value, the multistage ladder driving unit instantly increases the charging current for the grid electrode of the first NMOS tube and is used for rapidly avoiding the Miller platform voltage of the grid electrode of the first NMOS tube, switching loss can be further guaranteed to be reduced to the greatest extent, overshoot and oscillation of an output waveform are avoided, and the reliability of a switching power supply is improved.
Drawings
FIG. 1 is a schematic circuit diagram of a switching power supply output drive of the present invention;
FIG. 2 is a schematic circuit diagram of a two-stage step drive unit of the present invention;
FIG. 3 is a schematic circuit diagram of a temperature compensation unit of the present invention;
FIG. 4 is a schematic circuit diagram of a voltage detection unit of the present invention;
FIG. 5 is a schematic circuit diagram of a voltage clamping unit of the present invention;
fig. 6 is a schematic circuit diagram of the dead time control unit of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the embodiments shown in the drawings, but it should be understood that the embodiments are not limited to the present invention, and functional, method, or structural equivalents and alternatives according to the embodiments are within the scope of protection of the present invention by those skilled in the art.
As shown in fig. 1, the output driving device of the switching power supply of the present invention includes a multi-stage step driving unit, where the multi-stage step driving unit can charge the gate of the first NMOS transistor N0 according to the gate voltage of the first NMOS transistor N0 of the switching power supply, and turn on the first NMOS transistor N0. The device comprises a second NMOS tube N1, wherein the drain electrode of the second NMOS tube N1 is connected with the grid electrode of a first NMOS tube N0, and the second NMOS tube N1 is used for discharging the grid electrode of the first NMOS tube N0 and closing the first NMOS tube. The multistage step driving unit can provide multistage charging current for the grid electrode of the first NMOS tube N0, each stage of step driving unit correspondingly provides one stage of charging current, and each stage of charging current is increased step by step. When the grid voltage of the first NMOS tube N0 exceeds a set threshold value, the multi-stage ladder driving unit instantaneously increases the charging current of the grid of the first NMOS tube N0 and is used for quickly avoiding the Miller platform voltage of the grid of the first NMOS tube N0.
As shown in fig. 2, in the present embodiment, a two-stage step driving unit is employed.
Each stage of step driving unit comprises a driving circuit and a digital logic unit, taking the first stage of step driving unit as an example, the output end of the driving circuit is connected with the grid electrode of the first NMOS tube N0, the output end of the digital logic unit X1 is connected with the control end of the driving circuit, and the input end of the digital logic unit X1 receives signals (including a first PMW signal PMW1 and control signals output by the voltage detection unit) for controlling the step driving unit. The driving circuit of the step driving unit comprises a constant current source 1, a first PMOS tube P1 (an output upper tube), a second PMOS tube P11 and a third PMOS tube P12, wherein the first PMOS tube P1 and the second PMOS tube P11 form a mirror current circuit, and the drain electrode of the first PMOS tube P1 is the output end of the driving circuit and is connected with the grid electrode of a first NMOS tube N0; the constant current source 1 is connected with the drain electrode of the third PMOS tube P12, and the source electrode of the third PMOS tube P12 is connected with the drain electrode of the second PMOS tube P11. Correspondingly, the second stage ladder driving unit comprises a digital logic unit X2, an output upper pipe P2, and the nth stage ladder driving unit comprises a digital logic unit Xn, and an output upper pipe Pn.
As shown in fig. 4 and fig. 1, the voltage detection unit includes a voltage detection unit, an input end of the voltage detection unit is connected to a gate of the first NMOS transistor N0, an output end of the voltage detection unit is connected to a first input end of the digital logic unit X1, and the voltage detection unit starts the step driving unit to charge the gate of the first NMOS transistor N0 according to the gate voltage of the first NMOS transistor N0. As shown in fig. 4, the voltage detection unit includes voltage sampling resistors R1, R2 and a voltage comparator. When the gate voltage of the first NMOS NO is Vgs and the reference voltage Vref1 of the voltage comparator is set, the voltage comparator outputs a high-level signal when the gate voltage Vgs of the NMOS is greater than Vref1 [ (r1+r2)/R2 ], so as to control the corresponding digital logic unit X1 to operate, and further start the first step driving unit to charge the gate of the first NMOS N0.
As shown in fig. 6 and fig. 1, the dead time control unit is configured to generate a first PMW signal for controlling the step driving unit and a second PMW signal for controlling the second NMOS transistor N1, where an output end of the first PMW signal is connected to a second input end of the digital logic unit X1, and the dead time control unit controls the step driving unit and the second NMOS transistor N1, so that the gate charge of the first MOS transistor N0 and the gate discharge of the first MOS transistor N0 are not in the same time period, that is, the first PMOS transistor P1 and the second NMOS transistor N1 are not simultaneously turned on.
As shown in fig. 6, the dead time control unit receives a PMW signal for controlling the switching power supply, and the dead time control unit includes a delay circuit composed of a resistor R4, a capacitor C1, a resistor R5, and a capacitor C2, and a time interval is formed between the generated first PMW signal PMW1 and the second PMW signal PMW2 through the delay circuit, so that the gate charge of the first MOS transistor N0 and the gate discharge of the first MOS transistor N0 are not in the same time period. When the PWM signal is a high-level signal, the PWM1 signal channel is firstly conducted, the PWM1 signal outputs a low level, and then the signal is transmitted to the PWM2 signal channel after the RC delay structure delays, and the PWM2 outputs a high level. Similarly, when the PWM signal is a low level signal, the PWM2 signal channel is first turned on, the PWM2 signal outputs a low level, and then the PWM signal is transmitted to the PWM1 signal channel after being delayed by the RC delay structure, and the PWM1 outputs a high level. Let the power supply voltage be Vcc, the digital gate inversion threshold be vth=0.5×vcc, and the initial voltage of the capacitor C be vo=0, then the dead time is equal to the RC delay time, and t=rχ c×ln [ (Vcc-Vo)/(Vcc-Vth) ]=rχ c×ln2, which we can set the corresponding dead time by adjusting the value of RC.
As shown in fig. 3 and 1, the temperature compensation unit is provided to compensate the temperature of the charging current output from the step driving unit. In fig. 3, a reference voltage Vref, a compensation current adjusting resistor R, a temperature compensation current Icom, a bias current Ibias, a zero temperature drift current isuource after compensation, and a constant current source 1.
First case: if the reference voltage Vref is a positive temperature drift voltage, the bias current Ibias is a negative temperature drift current, and the resistor R is a zero temperature drift resistor. Therefore, in this case, the temperature compensation current icom=vref/R is a positive temperature drift compensation current, and the bias current Ibias is a negative temperature drift current, so that the current isuurce is zero temperature drift by adjusting the absolute value of the temperature drift coefficients of the reference voltage Vref and the bias current Ibias to be equal, and the constant current source 1 and isuurce form a current mirror structure, so that the constant current source 1 can completely mirror-image the isuurce current and the temperature characteristic is identical to the temperature characteristic of the isuurce current. Therefore, the constant current source 1 in the step driving unit driving circuit can reach zero temperature drift finally.
Second case: if the reference voltage Vref is zero temperature drift voltage and the bias current Ibias is negative temperature drift current, the resistor R must be selected as a negative temperature drift resistor. Therefore, in this case, the temperature compensation current icom=vref/R is a positive temperature drift compensation current, and the bias current Ibias is a negative temperature drift current, and Isource=icom+ibias, so that the current Isource is zero temperature drift by adjusting the absolute value of the temperature drift coefficients of the resistor R and the bias current Ibias to be equal, and since the constant current source 1 and Isource form a current mirror structure, the constant current source 1 can completely mirror-image the Isource current and the temperature characteristic is identical to the temperature characteristic of the Isource current. Therefore, the constant current source 1 in the step driving unit driving circuit can reach zero temperature drift finally.
Third case: if the reference voltage Vref is zero temperature drift voltage and the bias current Ibias is positive temperature drift current, the resistor R must be selected as the positive temperature drift resistor. Therefore, in this case, the temperature compensation current icom=vref/R is a negative temperature drift compensation current, and the bias current Ibias is a positive temperature drift current, and Isource=icom+ibias, so that the current Isource is zero temperature drift by adjusting the absolute value of the temperature drift coefficients of the resistor R and the bias current Ibias to be equal, and since the constant current source 1 and Isource form a current mirror structure, the constant current source 1 can completely mirror-image the Isource current and the temperature characteristic is identical to the temperature characteristic of the Isource current. Therefore, the constant current source 1 in the step driving unit driving circuit can reach zero temperature drift finally.
Fourth case: if the reference voltage Vref is a negative temperature drift voltage, the bias current Ibias is a positive temperature drift current, and the resistor R is a zero temperature drift resistor. Therefore, in this case, the temperature compensation current icom=vref/R is a negative temperature drift compensation current, and the bias current Ibias is a positive temperature drift current, and Isource=icom+ibias, so that the current Isource is zero temperature drift by adjusting the absolute value of the temperature drift coefficients of the reference voltage Vref and the bias current Ibias to be equal, and since the constant current source 1 and Isource form a current mirror structure, the constant current source 1 can completely mirror-image the Isource current and the temperature characteristic is identical to the temperature characteristic of the Isource current. Therefore, the constant current source 1 in the step driving unit driving circuit can reach zero temperature drift finally.
According to the analysis of the four conditions, as long as we have proper temperature drift coefficients of the reference voltage Vref, the bias current Ibias and the resistor R, the current Isource can be enabled to be zero temperature drift, and the constant current source 1 and Isource form a current mirror structure, so that the constant current source 1 can completely mirror-image copy Isource current, and the temperature characteristic is consistent with that of Isource current. Therefore, the constant current source 1 in the step driving unit driving circuit can reach zero temperature drift finally.
As shown in fig. 5 and 1, the NMOS transistor includes a voltage clamp unit that clamps the gate voltage of the first NMOS transistor N1, and the clamp voltage Vclamp is 14V. The voltage clamping unit comprises two zener diodes Z1 and Z2 and a resistor R3, the voltage stabilizing principle is that the characteristic that the pn junction of the zener diode is in a reverse breakdown state, the current of the zener diode can be changed in a large range and the voltage is basically unchanged is utilized, the voltage stabilizing clamping function is realized on the grid electrode of the first NMOS tube, the reverse breakdown voltage of the zener diode is vz=7V, the clamping voltage of the zener diode is Vclamp=2Xvz=14V, and the resistor R is a resistor with a small resistance value and plays a role in the current limiting protection of the zener diode.
Let the on threshold voltage vth=2v of the first NMOS transistor N0, the miller plateau voltage vgp=3v, and the gate voltage of the first NMOS transistor N0 be Vgs. The driving current of the first stage step driving unit is 20uA, the driving current of the second stage step driving unit is 200uA, when the PWM switching signal arrives, the PWM switching control signal is converted into a two-phase non-overlapping square wave signal, namely a PWM1 signal and a PWM2 signal, and the output upper tube (a first PMOS tube P1, a PMOS tube P2) and the output lower tube (a second NMOS tube N1) are respectively controlled to work.
When the voltage detection unit detects that the grid potential Vgs < vth=2v of the first NMOS tube NO, the first stage step driving unit is selectively turned on to work, and the grid of the first NMOS tube NO is slowly charged with 20uA current; when the voltage detection unit detects that the grid potential Vgs of the first NMOS tube NO is larger than Vth=2V, the second stage step driving unit is selectively turned on to work, the grid of the first NMOS tube NO is rapidly charged with 200uA current, so that the grid potential of the first NMOS tube NO can rapidly cross the miller platform voltage vgp=3V, the second stage step driving unit continues to charge the grid of the first NMOS tube NO until the clamping voltage Vclamp=14V is reached, and the voltage clamping unit is started to clamp the grid of the output upper tube at the 14V.
Therefore, the output driving device of the switching power supply can control the charging current of the grid electrode of the first NMOS tube NO to be increased stepwise, so that overshoot and oscillation of an output waveform caused by overlarge instantaneous rising slope of the grid electrode driving voltage can be avoided, the reliability of the switching power supply is improved, the EMI problem is reduced, meanwhile, the voltage change of the grid electrode miller platform of the NMOS tube can be accurately judged according to the voltage detection unit, the grid electrode of the first NMOS tube NO is charged with large current in an accelerating way, the influence of the voltage of the miller platform is reduced to the greatest extent, the rising speed of the drain electrode current of the first NMOS tube NO is matched with the falling speed of the drain electrode voltage, the switching loss of the first NMOS tube NO is reduced to the lowest, and the output efficiency is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (5)
1. The switching power supply output driving device is characterized by comprising a multi-stage ladder driving unit, wherein the multi-stage ladder driving unit is used for charging a grid electrode of a first NMOS tube of a switching power supply according to the grid electrode voltage of the first NMOS tube so as to turn on the first NMOS tube;
each stage of step driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the digital logic unit is used for receiving signals to control the step driving unit;
the voltage detection unit is connected with the grid electrode of the first NMOS tube and the first input end of the digital logic unit and is used for starting the corresponding step driving unit to charge the grid electrode of the first NMOS tube according to the voltage of the grid electrode of the first NMOS tube;
the second NMOS transistor is connected with the grid electrode of the first NMOS transistor, and is used for discharging the grid electrode of the first NMOS transistor to close the first NMOS transistor;
the dead time control unit is used for generating a first PMW signal for controlling the step driving unit and a second PMW signal for controlling the second NMOS tube, and the first PMW signal is output to the digital logic unit; the dead time control unit controls the step driving unit and the second NMOS tube so that the charging and discharging of the grid electrode of the first MOS tube are not in the same time period;
the dead time control unit comprises a delay circuit consisting of a resistor and a capacitor, and a time interval exists between a generated first PMW signal and a generated second PMW signal through the delay circuit, so that the charging and discharging of the grid electrode of the first MOS tube are not in the same time period;
the temperature compensation unit is used for performing temperature compensation on the charging current output by the step driving unit.
2. The switching power supply output driving apparatus according to claim 1, wherein: the driving circuit of the step driving unit comprises a constant current source, a first PMOS tube (P1), a second PMOS tube (P11) and a third PMOS tube (P12), wherein the first PMOS tube (P1) and the second PMOS tube (P11) form a mirror current circuit, and the drain electrode of the first PMOS tube (P1) is a driving circuit output end and is connected with the grid electrode of the first NMOS tube; the constant current source is connected with the drain electrode of the third PMOS tube (P12), and the source electrode of the third PMOS tube (P12) is connected with the drain electrode of the second PMOS tube (P11).
3. The switching power supply output driving apparatus according to claim 1, wherein: the device further comprises a voltage clamping unit, wherein the voltage clamping unit is used for clamping the grid voltage of the first NMOS tube.
4. The switching power supply output driving apparatus according to claim 1, wherein: the multistage ladder driving unit is used for providing multistage charging current for the grid electrode of the first NMOS tube, each stage of ladder driving unit correspondingly provides one stage of charging current, and each stage of charging current is increased stepwise.
5. The switching power supply output driving apparatus as claimed in claim 4, wherein: when the voltage of the grid electrode of the first NMOS tube exceeds a set threshold value, the multi-stage ladder driving unit instantaneously increases the charging current provided for the grid electrode of the first NMOS tube and is used for quickly avoiding the Miller platform voltage of the grid electrode of the first NMOS tube.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017133084A1 (en) * | 2016-02-02 | 2017-08-10 | 京东方科技集团股份有限公司 | Shift register unit, shift register, gate drive circuit and display device |
| CN108023464A (en) * | 2017-12-26 | 2018-05-11 | 上海数明半导体有限公司 | A kind of super-low standby power consumption circuit for motor drive ic |
| CN108429445A (en) * | 2017-02-13 | 2018-08-21 | 珠海全志科技股份有限公司 | A kind of soft starting circuit applied to charge pump |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109920357B (en) * | 2018-07-26 | 2020-06-02 | 京东方科技集团股份有限公司 | Gate drive circuit and method and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017133084A1 (en) * | 2016-02-02 | 2017-08-10 | 京东方科技集团股份有限公司 | Shift register unit, shift register, gate drive circuit and display device |
| CN108429445A (en) * | 2017-02-13 | 2018-08-21 | 珠海全志科技股份有限公司 | A kind of soft starting circuit applied to charge pump |
| CN108023464A (en) * | 2017-12-26 | 2018-05-11 | 上海数明半导体有限公司 | A kind of super-low standby power consumption circuit for motor drive ic |
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