CN114244148A - Switching power supply output driving device - Google Patents
Switching power supply output driving device Download PDFInfo
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- CN114244148A CN114244148A CN202111478948.4A CN202111478948A CN114244148A CN 114244148 A CN114244148 A CN 114244148A CN 202111478948 A CN202111478948 A CN 202111478948A CN 114244148 A CN114244148 A CN 114244148A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to a switching power supply output driving device which comprises a multistage step driving unit, wherein the multistage step driving unit can charge a grid electrode of a first N-channel metal oxide semiconductor (NMOS) tube according to the grid electrode voltage of the first NMOS tube of a switching power supply and start the first NMOS tube; each stage of ladder driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the input end of the digital logic unit receives a signal for controlling the ladder driving unit. The invention can effectively reduce power consumption and improve working reliability.
Description
Technical Field
The invention relates to a switching power supply output driving device.
Background
The switching power supply is widely applied to the fields of electronic and electric equipment and household appliances. The development of novel power devices promotes the high frequency of the switching power supply, the high frequency brings benefits of enabling the switching power supply device to be miniaturized unprecedentedly, enabling the switching power supply to enter wider fields, particularly application in the high and new technology field, promoting the miniaturization and the lightness of high and new technology products, and in addition, the development and the application of the switching power supply have profound significance in the aspects of saving resources and protecting the environment. The power MOS tube and the IGBT can enable the working frequency of a small and medium-sized switching power supply to reach 400kHz (AC/DC) and 1MHz (DC/DC), and the development of a control technology and the production of a special control chip greatly simplify a power supply circuit and greatly improve the dynamic performance and the reliability of the switching power supply.
The development of the switching power supply towards integration is the main trend in the future, the power density is higher and higher, and the requirements on the process are higher and higher. Without new breakthroughs in semiconductor devices and magnetic materials, significant technological advances may be difficult to achieve, and the emphasis on technological innovation will be on how to improve the efficiency and reliability of switching power supplies. It is known that to improve the efficiency of a switching power supply, the switching loss and the conduction loss of an output power tube of the switching power supply must be reduced, and to improve the reliability of the switching power supply, the output power tube of the switching power supply must be effectively protected. Therefore, there is a need to develop a switching power supply output driving apparatus capable of reducing energy loss of a switching power supply power tube as much as possible and improving reliability of the power tube.
The switching frequency of a bipolar transistor adopted by a power tube in a switching power supply in the market at present can reach dozens of kilohertz, and the switching frequency of the switching power supply adopting an MOS transistor can reach hundreds of kilohertz. Because of the high frequency of the switching power supply, most of the switching power supply output power transistors use MOS transistors. The MOS transistor has advantages of low on-resistance and large load current, and thus is very suitable for use as an output device of a switching power supply.
The current switching power supply output driving device mainly has four types: the first is a direct driving device of a power chip, and because different chips have different driving capacities, if the power chip does not have a larger driving peak current, the conduction speed of a tube is slower, which will cause the switching loss of the switching power supply to be increased sharply and reduce the output efficiency. The second one is a push-pull output driving device, which has the advantages of providing sufficient current driving capability, rapidly completing the charging process of the gate input capacitor of the MOS power tube, increasing the switching speed, but not matching the rising slope of the gate voltage of the NMOS tube, so that the overshoot and oscillation of the output waveform caused by the instantaneous rising slope of the gate driving voltage of the MOS tube usually occur, greatly reducing the reliability of the switching power supply and increasing the EMI problem. The third is an accelerated turn-off driving device, which is characterized in that a driving circuit can provide a low-impedance path for fast discharging of capacitance charges between the gate and the source of an MOS power tube at the turn-off moment of the power tube, and a resistor and a diode are usually connected in parallel to a driving resistor, so that the device is only beneficial to fast turn-off of the MOS power tube, cannot effectively control the turn-on state of the MOS power tube, and cannot substantially improve the output efficiency of a switching power supply. The fourth is an isolation driving device, which is used to satisfy the driving of a very small number of high-end MOS transistors, and needs to adopt a transformer for driving, and the device can isolate direct current and pass through alternating current, but the device is often easy to have magnetic core saturation, and simultaneously needs matching of inductance and capacitance on a PCB board, and has high manufacturing cost, so the device is rarely used in the market.
Therefore, there is a need to develop a switching power output driving apparatus that can overcome the above-mentioned drawbacks of various driving apparatuses. The device can reduce the energy loss of the MOS power tube to the maximum extent, so that the output efficiency is improved, overshoot and oscillation of an output waveform can be avoided, the reliability of the switching power supply is improved, and the EMI problem is reduced.
Disclosure of Invention
The invention aims to provide a switching power supply output driving device which can effectively reduce power consumption and improve working reliability.
The technical scheme for realizing the purpose of the invention is as follows:
a switching power supply output driving device comprises a multi-stage step driving unit, wherein the multi-stage step driving unit is used for charging a grid electrode of a first NMOS (N-channel metal oxide semiconductor) tube according to the grid electrode voltage of the first NMOS tube of a switching power supply so as to start the first NMOS tube;
each step driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the digital logic unit is used for receiving signals to control the step driving unit.
Furthermore, the drive circuit of the ladder drive unit comprises a constant current source, a first PMOS (P-channel metal oxide semiconductor) tube (P1), a second PMOS tube (P11) and a third PMOS tube (P12), wherein the first PMOS tube (P1) and the second PMOS tube (P11) form a mirror current circuit, and the drain electrode of the first PMOS tube (P1) is the output end of the drive circuit and is connected with the grid electrode of the first NMOS tube; the constant current source is connected with the drain electrode of the third PMOS tube (P12), and the source electrode of the third PMOS tube (P12) is connected with the drain electrode of the second PMOS tube (P11).
The voltage detection unit is connected with the grid electrode of the first NMOS tube and the first input end of the digital logic unit and used for starting the corresponding step driving unit to charge the grid electrode of the first NMOS tube according to the grid electrode voltage of the first NMOS tube.
The drain electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube and is used for discharging the grid electrode of the first NMOS tube to close the first NMOS tube.
Further, the device also comprises a dead time control unit, wherein the dead time control unit generates a first PMW signal for controlling the step driving unit and a second PMW signal for controlling the second NMOS tube, and the first PMW signal is output to the digital logic unit; the dead time control unit controls the step driving unit and the second NMOS tube, so that the charging and discharging of the grid electrode of the first MOS tube are not in the same time period.
Further, the dead time control unit comprises a delay circuit composed of a resistor and a capacitor, and a time interval exists between the generated first PMW signal and the second PMW signal through the delay circuit, so that the charging and the discharging of the grid electrode of the first MOS transistor are not in the same time period.
Further, the charging device further comprises a temperature compensation unit, wherein the temperature compensation unit is used for performing temperature compensation on the charging current output by the step driving unit.
Further, the voltage clamping unit is further included and used for clamping the grid voltage of the first NMOS pipe.
Furthermore, the multistage step drive unit is used for providing multistage charging current for the grid electrode of the first NMOS tube, each stage of step drive unit correspondingly provides one stage of charging current, and each stage of charging current is increased step by step.
Further, when the voltage of the gate of the first NMOS transistor exceeds the set threshold, the multi-step driving unit instantly increases the charging current provided to the gate of the first NMOS transistor for rapidly avoiding the miller platform voltage of the gate of the first NMOS transistor.
The invention has the following beneficial effects:
the multi-stage step driving unit can charge the grid electrode of the first NMOS tube according to the grid electrode voltage of the first NMOS tube of the switching power supply and start the first NMOS tube; each stage of ladder driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the input end of the digital logic unit receives a signal for controlling the ladder driving unit. According to the grid voltage of the first NMOS tube of the switching power supply, the grid of the first NMOS tube is charged through the multi-stage step driving unit, so that the loss can be reduced to the greatest extent, the output efficiency is improved, overshoot and oscillation of an output waveform can be avoided, the reliability of the switching power supply is improved, and the EMI problem is reduced.
The voltage detection unit starts a corresponding step drive unit to charge the grid electrode of the first NMOS tube according to the grid electrode voltage of the first NMOS tube. According to the invention, the voltage of the grid electrode of the first NMOS tube is detected by the voltage detection unit, and the corresponding step drive unit is started to charge the grid electrode of the first NMOS tube according to the voltage of the grid electrode of the first NMOS tube, so that the reduction of power consumption is further effectively ensured, and the working reliability is improved.
The temperature compensation unit is used for compensating the temperature of the charging current output by the step driving unit, so that the device can drive the first NMOS tube to stably work in the full temperature range, and the problem of abnormal driving caused by severe temperature change is solved. The voltage clamping unit clamps the grid voltage of the first NMOS tube, so that the problem of transistor damage caused by overhigh grid voltage of the first NMOS tube is avoided, and the working reliability is further ensured.
The device comprises a dead time control unit, wherein the dead time control unit generates a first PMW signal for controlling a step driving unit and a second PMW signal for controlling a second NMOS tube, the output end of the first PMW signal is connected with the second input end of a digital logic unit, and the dead time control unit controls the step driving unit and the second NMOS tube so that the grid charging of a first MOS tube and the grid discharging of the first MOS tube are not in the same time period; the dead time control unit receives a PMW signal for controlling the switching power supply, and comprises a time delay circuit consisting of a resistor and a capacitor, and a time interval is formed between the generated first PMW signal and the second PMW signal through the time delay circuit, so that the grid charging of the first MOS tube and the grid discharging of the first MOS tube are not in the same time period. According to the invention, the dead time control unit is used for realizing the control function of the output dead time, so that the first PMOS tube (output upper tube) and the second NMOS tube (output lower tube) of the step drive unit are prevented from being conducted simultaneously, the risk that the transistors are burnt by large current due to the direct connection of a power supply to the ground is further avoided, and the working reliability is further ensured.
The multistage step driving unit can provide multistage charging current for the grid electrode of the first NMOS tube, each stage of step driving unit correspondingly provides one stage of charging current, each stage of charging current is increased in a step-by-step mode, when the grid electrode voltage of the first NMOS tube exceeds a set threshold value, the multistage step driving unit instantly increases the charging current for the grid electrode of the first NMOS tube, the multistage step driving unit is used for rapidly avoiding the Miller platform voltage of the grid electrode of the first NMOS tube, the switching loss can be further reduced to the maximum degree, overshoot and oscillation of an output waveform are avoided, and the reliability of a switching power supply is improved.
Drawings
Fig. 1 is a schematic circuit diagram of an output driving apparatus of a switching power supply of the present invention;
FIG. 2 is a schematic circuit diagram of a two-stage step drive unit of the present invention;
FIG. 3 is a schematic circuit diagram of the temperature compensation unit of the present invention;
FIG. 4 is a schematic circuit diagram of the voltage detection unit of the present invention;
FIG. 5 is a circuit schematic of the voltage clamping unit of the present invention;
fig. 6 is a circuit schematic of the dead time control unit of the present invention.
Detailed Description
The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.
As shown in fig. 1, the switching power supply output driving apparatus of the present invention includes a multi-stage ladder driving unit, which charges the gate of the first NMOS transistor N0 according to the gate voltage of the first NMOS transistor N0 of the switching power supply, and turns on the first NMOS transistor N0. The power supply circuit comprises a second NMOS transistor N1, wherein the drain electrode of the second NMOS transistor N1 is connected with the grid electrode of the first NMOS transistor N0, and the second NMOS transistor N1 is used for discharging the grid electrode of the first NMOS transistor N0 and closing the first NMOS transistor. The multistage step drive unit can provide multistage charging current to first NMOS pipe N0 grid, and each stage of step drive unit correspondingly provides one stage of charging current, and each stage of charging current is stepped up step by step. When the gate voltage of the first NMOS transistor N0 exceeds the set threshold, the multi-step driving unit instantaneously increases the charging current to the gate of the first NMOS transistor N0, so as to rapidly avoid the miller platform voltage of the gate of the first NMOS transistor N0.
As shown in fig. 2, in the present embodiment, a two-stage step drive unit is employed.
Each stage of ladder driving unit comprises a driving circuit and a digital logic unit, taking the first stage of ladder driving unit as an example, the output end of the driving circuit is connected with the grid electrode of the first NMOS pipe N0, the output end of the digital logic unit X1 is connected with the control end of the driving circuit, and the input end of the digital logic unit X1 receives signals (including the first PMW signal PMW1 and control signals output by the voltage detection unit) for controlling the ladder driving unit. The drive circuit of the step drive unit comprises a constant current source 1, a first PMOS tube P1 (output upper tube), a second PMOS tube P11 and a third PMOS tube P12, wherein the first PMOS tube P1 and the second PMOS tube P11 form a mirror current circuit, and the drain electrode of the first PMOS tube P1 is the output end of the drive circuit and is connected with the grid electrode of a first NMOS tube N0; the constant current source 1 is connected with the drain electrode of a third PMOS tube P12, and the source electrode of the third PMOS tube P12 is connected with the drain electrode of a second PMOS tube P11. Correspondingly, the second stage ladder driving unit comprises a digital logic unit X2 and an output upper tube P2, and the nth stage ladder driving unit comprises a digital logic unit Xn and an output upper tube Pn.
As shown in fig. 4 and fig. 1, the voltage detection unit is included, an input end of the voltage detection unit is connected with a gate of the first NMOS transistor N0, an output end of the voltage detection unit is connected with a first input end of the digital logic unit X1, and the voltage detection unit starts the step driving unit to charge the gate of the first NMOS transistor N0 according to a gate voltage of the first NMOS transistor N0. As shown in fig. 4, the voltage detection unit includes voltage sampling resistors R1, R2, and a voltage comparator. And if the gate voltage of the first NMOS transistor NO is Vgs and the reference voltage Vref1 of the voltage comparator is set, when the gate voltage Vgs of the NMOS transistor is greater than Vref1 [ (R1+ R2)/R2], the voltage comparator outputs a high-level signal to control the corresponding digital logic unit X1 to operate, and further, the first step driving unit is started to charge the gate of the first NMOS transistor N0.
As shown in fig. 6 and 1, the device comprises a dead time control unit, wherein the dead time control unit generates a first PMW signal for controlling the step driving unit and a second PMW signal for controlling the second NMOS transistor N1, the first PMW signal output end is connected with the second input end of the digital logic unit X1, and the dead time control unit controls the step driving unit and the second NMOS transistor N1, so that the gate charging of the first MOS transistor N0 and the gate discharging of the first MOS transistor N0 are not in the same time period, namely, the first PMOS transistor P1 and the second NMOS transistor N1 are not simultaneously conducted.
As shown in fig. 6, the dead time control unit receives a PMW signal for controlling the switching power supply, and includes a delay circuit composed of a resistor R4, a capacitor C1, a resistor R5 and a capacitor C2, and a time interval is allowed between the first PMW signal PMW1 and the second PMW signal PMW2 generated by the delay circuit, so that the gate charging of the first MOS transistor N0 and the gate discharging of the first MOS transistor N0 are not in the same time period. When the PWM signal is a high level signal, the PWM1 signal channel is firstly turned on, the PWM1 signal outputs a low level, the signal is delayed by the RC delay structure and then transmitted to the PWM2 signal channel, and the PWM2 outputs a high level. Similarly, when the PWM signal is a low level signal, the PWM2 signal channel is firstly turned on, the PWM2 signal outputs a low level, the RC delay structure delays the PWM signal and transmits the PWM signal to the PWM1 signal channel, and the PWM1 outputs a high level. Assuming that the power voltage is Vcc, the digital gate flipping threshold is Vth ═ 0.5 × Vcc, and the initial voltage of the capacitor C is Vo ═ 0, then the dead time delay time is equal to the RC delay time, and t ═ R × ln [ (Vcc-Vo)/(Vcc-Vth) ] ═ R × C × ln2, we can set the corresponding dead time by adjusting the value of RC.
As shown in fig. 3 and fig. 1, the charging circuit includes a temperature compensation unit for performing temperature compensation on the charging current output by the step driving unit. In fig. 3, a reference voltage Vref, a compensation current adjusting resistor R, a temperature compensation current Icom, a bias current Ibias, a compensated zero temperature drift current Isource, and a constant current source 1.
In the first case: if the reference voltage Vref is a positive temperature drift voltage, the bias current Ibias is a negative temperature drift current, and the resistor R is a zero temperature drift resistor. Therefore, in this case, since the temperature compensation current Icom/R is a positive temperature drift compensation current, the bias current Ibias is a negative temperature drift current, and Isource is Icom + Ibias, the purpose of making the current Isource zero temperature drift can be achieved by adjusting the absolute value of the temperature drift coefficients of the reference voltage Vref and the bias current Ibias to be equal, and since the constant current source 1 and Isource form a current mirror structure, the constant current source 1 can completely mirror-copy the Isource current and the temperature characteristic also matches the Isource current temperature characteristic. Therefore, the constant current source 1 in the driving circuit of the step driving unit can finally reach zero temperature drift.
In the second case: if the reference voltage Vref is zero temperature drift voltage and the bias current Ibias is negative temperature drift current, the resistor R must be selected as a negative temperature drift resistor. Therefore, in this case, the temperature compensation current Icom ═ Vref/R is a positive temperature drift compensation current, the bias current Ibias is a negative temperature drift current, and Isource ═ Icom + Ibias, so that the purpose of making the current Isource zero temperature drift can be achieved by adjusting the absolute value of the temperature drift coefficients of the resistor R and the bias current Ibias to be equal, and since the constant current source 1 and Isource form a current mirror structure, the constant current source 1 can completely mirror-copy the Isource current and the temperature characteristic also matches the Isource current temperature characteristic. Therefore, the constant current source 1 in the driving circuit of the step driving unit can finally reach zero temperature drift.
In the third case: if the reference voltage Vref is zero temperature drift voltage and the bias current Ibias is positive temperature drift current, the resistor R must be selected as the positive temperature drift resistor. Therefore, in this case, the temperature compensation current Icom is a negative temperature drift compensation current, the bias current Ibias is a positive temperature drift current, and Isource is Icom + Ibias, so that the purpose of making the current Isource zero temperature drift can be achieved by adjusting the absolute value of the temperature drift coefficients of the resistor R and the bias current Ibias to be equal, and since the constant current source 1 and Isource form a current mirror structure, the constant current source 1 can completely mirror-copy the Isource current and the temperature characteristic is also consistent with the Isource current temperature characteristic. Therefore, the constant current source 1 in the driving circuit of the step driving unit can finally reach zero temperature drift.
In a fourth case: if the reference voltage Vref is a negative temperature drift voltage and the bias current Ibias is a positive temperature drift current, the resistor R is a zero temperature drift resistor. Therefore, in this case, the temperature compensation current Icom/R is a negative temperature drift compensation current, the bias current Ibias is a positive temperature drift current, and Isource is Icom + Ibias, so that the purpose of making the current Isource zero temperature drift can be achieved by adjusting the absolute value of the temperature drift coefficients of the reference voltage Vref and the bias current Ibias to be equal, and since the constant current source 1 and Isource form a current mirror structure, the constant current source 1 can completely mirror-copy the Isource current and the temperature characteristic also matches the Isource current temperature characteristic. Therefore, the constant current source 1 in the driving circuit of the step driving unit can finally reach zero temperature drift.
According to the above four conditions, it can be known that the current Isource can be zero temperature drift by configuring the reference voltage Vref, the bias current Ibias and the appropriate temperature drift coefficient of the resistor R, and the constant current source 1 can completely mirror and copy the Isource current and the temperature characteristic is consistent with the Isource current temperature characteristic because the constant current source 1 and the Isource form a current mirror structure. Therefore, the constant current source 1 in the driving circuit of the step driving unit can finally reach zero temperature drift.
As shown in fig. 5 and fig. 1, the NMOS transistor includes a voltage clamping unit for clamping the gate voltage of the first NMOS transistor N1, and the clamping voltage Vclamp is 14V. The voltage clamping unit comprises two Zener diodes Z1 and Z2 and a resistor R3, the voltage stabilizing principle is that the characteristic that the current of the pn junction of the Zener diode can change in a large range and the voltage is basically unchanged is utilized, the characteristic that the pn junction of the Zener diode is in a reverse breakdown state is utilized, the voltage stabilizing clamping function is realized on the grid electrode of the first NMOS tube, the reverse breakdown voltage of the Zener diode is 7V, the clamping voltage is Vclamp 2 Vz 14V, and the resistor R is a resistor with a small resistance value and plays a role in current limiting protection of the Zener diode.
Let the turn-on threshold voltage Vth of the first NMOS transistor N0 be 2V, the miller plateau voltage Vgp be 3V, and the gate voltage of the first NMOS transistor N0 be Vgs. When the PWM switching signal arrives, the dead time control unit is firstly passed through, the PWM switching control signal is converted into two-phase non-overlapping square wave signals, namely a PWM1 signal and a PWM2 signal, and the two-phase non-overlapping square wave signals are generated to respectively control an output upper tube (a first PMOS tube P1 and a PMOS tube P2) and an output lower tube (a second NMOS tube N1) to work.
When the voltage detection unit detects that the grid potential Vgs < Vth of the first NMOS tube NO is 2V, the first-stage step driving unit is selected to be turned on to work, and the grid of the first NMOS tube NO is slowly charged with 20uA current; when the voltage detection unit detects that the grid potential Vgs of the first NMOS tube NO is larger than Vth and is 2V, the second-stage step driving unit is selected to be started to work, the grid of the first NMOS tube NO is rapidly charged by 200uA current, therefore, the grid potential of the first NMOS tube NO can rapidly cross the Miller platform voltage Vgp and is 3V, the second-stage step driving unit continues to charge the grid of the first NMOS tube NO until the clamping voltage Vclamp reaches 14V, at the moment, the voltage clamping unit is started, and the grid of the output upper tube is clamped at 14V.
Therefore, the switching power supply output driving device can control the charging current of the NO grid of the first NMOS tube to increase step by step, so that overshoot and oscillation of an output waveform caused by overlarge instantaneous rising slope of grid driving voltage can be avoided, the reliability of the switching power supply is improved, the EMI problem is reduced, meanwhile, the voltage change of the Miller platform of the grid of the NMOS tube can be accurately judged according to the voltage detection unit, the NO grid of the first NMOS tube is charged at high current acceleration, the influence of the Miller platform voltage is reduced to the maximum extent, the rising speed of the NO drain current of the first NMOS tube is matched with the falling speed of the NO drain voltage, the switching loss of the NO of the first NMOS tube is reduced to the minimum, and the output efficiency is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (10)
1. The switching power supply output driving device is characterized by comprising a multi-stage step driving unit, wherein the multi-stage step driving unit is used for charging a grid electrode of a first NMOS (N-channel metal oxide semiconductor) tube according to a grid electrode voltage of the first NMOS tube of a switching power supply so as to start the first NMOS tube;
each step driving unit comprises a driving circuit and a digital logic unit, wherein the output end of the driving circuit is connected with the grid electrode of the first NMOS tube, the output end of the digital logic unit is connected with the control end of the driving circuit, and the digital logic unit is used for receiving signals to control the step driving unit.
2. The switching power supply output driving device according to claim 1, wherein: the drive circuit of the step drive unit comprises a constant current source, a first PMOS (P1), a second PMOS (P11) and a third PMOS (P12), wherein the first PMOS (P1) and the second PMOS (P11) form a mirror current circuit, and the drain electrode of the first PMOS (P1) is the output end of the drive circuit and is connected with the grid electrode of the first NMOS; the constant current source is connected with the drain electrode of the third PMOS tube (P12), and the source electrode of the third PMOS tube (P12) is connected with the drain electrode of the second PMOS tube (P11).
3. The switching power supply output driving device according to claim 1, wherein: the voltage detection unit is connected with the first NMOS tube grid electrode and the first input end of the digital logic unit and used for starting the corresponding step driving unit to charge the first NMOS tube grid electrode according to the first NMOS tube grid electrode voltage.
4. The switching power supply output driving device according to claim 1, wherein: the drain electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube and is used for discharging the grid electrode of the first NMOS tube to close the first NMOS tube.
5. The switching power supply output driving device according to claim 4, wherein: the digital logic unit is used for generating a first PMW signal for controlling the step driving unit and a second PMW signal for controlling the second NMOS tube, and the first PMW signal is output to the digital logic unit; the dead time control unit controls the step driving unit and the second NMOS tube, so that the charging and discharging of the grid electrode of the first MOS tube are not in the same time period.
6. The switching power supply output driving device according to claim 5, wherein: the dead time control unit comprises a delay circuit composed of a resistor and a capacitor, and a time interval exists between the generated first PMW signal and the second PMW signal through the delay circuit, so that the charging and discharging of the grid electrode of the first MOS transistor are not in the same time period.
7. The switching power supply output driving device according to claim 1, wherein: the temperature compensation unit is used for performing temperature compensation on the charging current output by the step driving unit.
8. The switching power supply output driving device according to claim 1, wherein: the voltage clamping unit is used for clamping the grid voltage of the first NMOS tube.
9. The switching power supply output driving device according to claim 1, wherein: the multistage step drive unit is used for providing multistage charging current for the grid electrode of the first NMOS tube, each stage of step drive unit correspondingly provides one stage of charging current, and each stage of charging current is increased step by step.
10. The switching power supply output driving device according to claim 9, wherein: when the voltage of the grid electrode of the first NMOS tube exceeds a set threshold value, the multistage step driving unit instantly increases the charging current provided for the grid electrode of the first NMOS tube so as to quickly avoid the Miller platform voltage of the grid electrode of the first NMOS tube.
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| US20200302854A1 (en) * | 2018-07-26 | 2020-09-24 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Gate driving circuit, driving method, and display device |
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| WO2017133084A1 (en) * | 2016-02-02 | 2017-08-10 | 京东方科技集团股份有限公司 | Shift register unit, shift register, gate drive circuit and display device |
| CN108429445A (en) * | 2017-02-13 | 2018-08-21 | 珠海全志科技股份有限公司 | A kind of soft starting circuit applied to charge pump |
| CN108023464A (en) * | 2017-12-26 | 2018-05-11 | 上海数明半导体有限公司 | A kind of super-low standby power consumption circuit for motor drive ic |
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