CN113517813B - Fixed frequency dual-mode synchronous buck controller - Google Patents
Fixed frequency dual-mode synchronous buck controller Download PDFInfo
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- CN113517813B CN113517813B CN202110528103.5A CN202110528103A CN113517813B CN 113517813 B CN113517813 B CN 113517813B CN 202110528103 A CN202110528103 A CN 202110528103A CN 113517813 B CN113517813 B CN 113517813B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention relates to a fixed frequency dual-mode synchronous buck controller, which relates to the integrated circuit technology, and comprises the following steps: an on-time circuit having an output coupled to a first input of the digital logic circuit; a comparator having an output connected to the second input of the digital logic circuit; the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end and controlling the level states of the two output ends according to the level of the second input end; and the positive input end of the switch selection circuit is connected with the second reference voltage end, and the negative input end of the switch selection circuit is connected with the feedback voltage end. The invention makes the conversion frequency be a fixed value, avoids the conversion frequency of the traditional hysteresis control mode from being influenced by ESR, inductance L and other parameters, thereby effectively reducing EMI interference and effectively improving the reliability and stability of equipment in the system.
Description
Technical Field
The present invention relates to integrated circuit technology.
Background
The synchronous buck controller with the fixed switching frequency dual control mode function belongs to a very important component part in power management application, and is mainly applied to various environments such as power supplies of set top boxes, notebook computers, mobile power supply systems and linear voltage regulators. The anti-interference device has the advantages of small volume, low cost, convenient application, strong anti-interference capability and the like, and is widely applied.
In a portable application environment, the operating frequency of a mobile communication device may range from several hundred KHz to several tens of MHz. In this wide bandwidth range, noise may affect the stability of normal operation of the electronic device, so that the communication quality of the communication device may be reduced. This requires a DC-DC converter with a fixed switching frequency, which reduces EMI interference and improves the stability and anti-interference capability of the product equipment by means of filtering devices on the periphery of the PCB.
Fig. 1 is a schematic diagram of a DC-DC buck converter in a conventional hysteretic control mode. In the DC-DC converter of the conventional hysteresis control mode, a conversion frequency formula is shown as follows.
From the formula, the conversion frequency is subjected to the input voltage, the output voltage, the ESR value, the inductance L value and the voltage ripple amplitude value V of the feedback point of the series resistor HYS Delay time t d And the like. Therefore, in a practical application environment, the switching frequency generated by the DC-DC converter of the conventional hysteresis control mode is not a fixed value, but a switching frequency is randomly generated within a certain frequency range. This gives EMI interference signals to other devices in the PCB board, ultimately affecting the reliability and stability of the system.
Therefore, in order to avoid the above-mentioned problems, it is necessary to redesign and optimize the overall circuit structure based on the DC-DC converter of the conventional hysteresis control mode, to design the COT control mode having a fast transient response characteristic and a fixed switching frequency and the current control mode having a high-precision output voltage and a fixed switching frequency, and to implement the dual control mode function of one chip to implement both the COT control mode and the current control mode.
Disclosure of Invention
The invention aims to solve the technical problemsThe problem is that based on the traditional hysteresis control mode, the whole circuit structure is redesigned to make the conversion frequency be a fixed value so as to reduce EMI interference, and solve the problems that the conversion frequency of the traditional hysteresis control mode is along with the input voltage, the output voltage, the ESR value, the inductance L value and the voltage ripple amplitude value V of the series resistance feedback point HYS Delay time t d And the like, and the like.
The technical scheme adopted by the invention for solving the technical problems is that the fixed-frequency dual-mode synchronous buck controller is characterized by comprising the following parts:
an on-time circuit having an output coupled to a first input of the digital logic circuit;
a comparator having an output connected to the second input of the digital logic circuit;
the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end and controlling the level states of the two output ends according to the level of the second input end;
the switch selection circuit is characterized in that a zero input end of the switch selection circuit is connected with an output end of the transconductance amplifier, a first input end of the switch selection circuit is connected with a feedback voltage end, a second input end of the switch selection circuit is connected with a first reference voltage end, a third input end of the switch selection circuit is connected with a CS end, a fourth input end of the switch selection circuit is connected with a PGND end, a fifth input end of the switch selection circuit is connected with a second reference voltage end, a first output end of the switch selection circuit is connected with a first negative input end of the comparator, a second output end of the switch selection circuit is connected with a first positive input end of the comparator, a third output end of the switch selection circuit is connected with a second positive input end of the comparator, and a fourth output end of the switch selection circuit is connected with a second negative input end of the comparator according to a zero input end signal;
the positive input end of the transconductance amplifier is connected with the second reference voltage end, and the negative input end of the transconductance amplifier is connected with the feedback voltage end.
The on-time circuit includes:
a switching Voltage (VDDQ) detection circuit formed by series connection of resistors,
the SW port voltage detection circuit comprises a twenty-first NMOS tube and a twenty-eighth NMOS tube, wherein the source electrode of the twenty-first NMOS tube is connected with the drain electrode of the twenty-eighth NMOS tube and a twenty-fifth resistor, the twenty-fifth resistor is grounded through a capacitor, the source electrode of the twenty-eighth NMOS tube is grounded, and the source electrode of the twenty-first NMOS tube is used as an output end;
a twenty-first PMOS tube, wherein the source electrode of the twenty-first PMOS tube is connected with the VCC end, the drain electrode of the twenty-first PMOS tube is grounded through the twenty-first triode, and the grid electrode of the twenty-first PMOS tube is connected with the first bias signal end;
a twenty-first triode, the base electrode of which is connected with the output end of the conversion voltage detection circuit;
a twenty-second PMOS tube, the source electrode of which is connected with the VCC end, and the grid electrode and the drain electrode of which are connected with the drain electrode of the twenty-fifth NMOS tube;
a twenty-fifth NMOS tube, the grid electrode of which is connected with the second bias signal end, the source electrode of which is connected with the drain electrode of the twenty-second NMOS tube,
a twenty-second NMOS tube, a grid electrode connected with the drain electrode of the twenty-first PMOS tube, a source electrode connected with the drain electrode of the twenty-seventh NMOS tube, a source electrode of the twenty-seventh NMOS tube grounded,
a twenty-third PMOS tube, the grid electrode of which is connected with the grid electrode of the twenty-second PMOS tube, the source electrode of which is connected with the VCC end, the drain electrode of which is connected with the drain electrode of the twenty-fourth NMOS tube,
a grid electrode of the twenty-fourth NMOS tube is connected with the second bias signal end, and a source electrode of the twenty-fourth NMOS tube is connected with a drain electrode of the twenty-third NMOS tube;
a source electrode of the twenty-third NMOS tube is connected with a drain electrode of the twenty-seventh NMOS tube;
the grid electrode of the twenty-seventh NMOS tube is connected with a third bias signal end;
a grid electrode of the twenty-fourth PMOS tube is connected with a first bias signal end, a source electrode of the twenty-fourth PMOS tube is connected with a VCC end, a drain electrode of the twenty-fourth PMOS tube is grounded through a twenty-second triode, and a base electrode of the twenty-second triode is connected with a source electrode of the twenty-first NMOS tube;
a twenty-fifth PMOS tube, the grid electrode of which is connected with the drain electrode of the twenty-third PMOS tube, the source electrode of which is connected with the VCC end, the drain electrode of which is used as the output end through an inverter,
and the grid electrode of the twenty-sixth NMOS tube is connected with the third bias signal end, the source electrode of the twenty-sixth NMOS tube is grounded, and the drain electrode of the twenty-fifth NMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube.
The working logic of the digital logic circuit is as follows:
when the first input end receives the trigger signal, the first output end is set to be low level, and the second output end is set to be high level;
when the second input end receives the trigger signal, the second output end is set to be low level, and the first output end is set to be high level.
Further, when the first input end receives the trigger signal, the first output end is set to be at a low level, and after a preset second time delay, the second output end is set to be at a high level;
when the second input end receives the trigger signal, the second output end is set to be at a low level, and after a preset first time delay, the first output end is set to be at a high level.
The invention enables the chip to realize a COT control mode with fixed conversion frequency and quick transient response characteristic and a current control mode with fixed conversion frequency and high-precision output voltage characteristic, and in the practical application process, the chip flexibly selects any control mode by changing the connection relation of external pins COMP.
Drawings
Fig. 1 is a schematic diagram of a DC-DC buck converter in a conventional hysteretic control mode.
Fig. 2 is a schematic diagram of an on-time circuit.
FIG. 3 is a logic timing diagram of the on-time circuit and PWM comparator control power transistors.
Fig. 4 is a schematic diagram of a switch selection circuit configuration.
Fig. 5 is a schematic diagram of the switch selection circuit selection result in the COT mode.
Fig. 6 is a schematic diagram of the switch selection circuit selection result in the current mode.
Fig. 7 is a schematic diagram of a COT control mode with a fixed switching frequency.
Fig. 8 is a schematic diagram of a current control mode with a fixed switching frequency.
Fig. 9 is a schematic diagram of a switching frequency spectrum simulation waveform employing the present invention.
Detailed description of the preferred embodiments
The invention comprises a PWM comparator, a reference circuit, a conduction time circuit, a digital logic circuit, a transconductance amplifier and a switch selection circuit, wherein the reference circuit is used for generating a reference voltage of 1.2V and a reference voltage of 0.75V; the PWM comparator is used for comparing the reference voltage with the feedback voltage; the on-time circuit is used for generating a fixed switching frequency; the digital logic circuit is used for controlling the working states of the DRVH and the DRVL and providing driving capability for the external power tube; the switch selection circuit is used for selecting the feedback voltage according to different control modes.
Referring to fig. 2 to 8, the present invention includes the following parts:
an on-time circuit having an output coupled to a first input of the digital logic circuit;
a comparator having an output connected to the second input of the digital logic circuit;
the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end EN_on_time and controlling the level states of the two output ends according to the level of the second input end EN_off_time;
the switch selection circuit is characterized in that a zero input end of the switch selection circuit is connected with an output end of the transconductance amplifier, a first input end of the switch selection circuit is connected with a feedback voltage end FB, a second input end of the switch selection circuit is connected with a first reference voltage end (1.2V), a third input end of the switch selection circuit is connected with a CS end, a fourth input end of the switch selection circuit is connected with a PGND end, a fifth input end of the switch selection circuit is connected with a second reference voltage end (0.75V), a first output end of the switch selection circuit is connected with a first positive input end of the comparator, a third output end of the switch selection circuit is connected with a second positive input end of the comparator, and a fourth output end of the switch selection circuit is connected with a second negative input end of the comparator according to a zero input end signal;
the positive input end of the transconductance amplifier is connected with the second reference voltage end (0.75V), and the negative input end of the transconductance amplifier is connected with the feedback voltage end.
The on-time circuit includes:
and a switching voltage detection circuit formed by serially connecting resistors.
Referring to fig. 2, the twenty-first NMOS transistor in the present invention is referred to as "NMOS21" in the figure, and the marks of other MOS transistors are the same.
The SW port voltage detection circuit comprises a twenty-first NMOS tube and a twenty-eighth NMOS tube, wherein the source electrode of the twenty-first NMOS tube is connected with the drain electrode of the twenty-eighth NMOS tube and a twenty-fifth resistor, the twenty-fifth resistor is grounded through a capacitor, the source electrode of the twenty-eighth NMOS tube is grounded, and the source electrode of the twenty-first NMOS tube is used as an output end;
a twenty-first PMOS tube, wherein the source electrode of the twenty-first PMOS tube is connected with the VCC end, the drain electrode of the twenty-first PMOS tube is grounded through the PNP21 of the twenty-first triode, and the grid electrode of the twenty-first PMOS tube is connected with the first bias signal end;
a twenty-first triode PNP21, the base electrode of which is connected with the output end of the conversion voltage detection circuit;
a twenty-second PMOS tube, the source electrode of which is connected with the VCC end, and the grid electrode and the drain electrode of which are connected with the drain electrode of the twenty-fifth NMOS tube;
a twenty-fifth NMOS tube, the grid electrode of which is connected with the second bias signal end, the source electrode of which is connected with the drain electrode of the twenty-second NMOS tube,
a twenty-second NMOS tube, a grid electrode connected with the drain electrode of the twenty-first PMOS tube, a source electrode connected with the drain electrode of the twenty-seventh NMOS tube, a source electrode of the twenty-seventh NMOS tube grounded,
a twenty-third PMOS tube, the grid electrode of which is connected with the grid electrode of the twenty-second PMOS tube, the source electrode of which is connected with the VCC end, the drain electrode of which is connected with the drain electrode of the twenty-fourth NMOS tube,
a grid electrode of the twenty-fourth NMOS tube is connected with the second bias signal end, and a source electrode of the twenty-fourth NMOS tube is connected with a drain electrode of the twenty-third NMOS tube;
a source electrode of the twenty-third NMOS tube is connected with a drain electrode of the twenty-seventh NMOS tube;
the grid electrode of the twenty-seventh NMOS tube is connected with a third bias signal end;
a grid electrode of the twenty-fourth PMOS tube is connected with the first bias signal end, a source electrode of the twenty-fourth PMOS tube is connected with the VCC end, a drain electrode of the twenty-second PMOS tube is grounded through a PNP22 of the twenty-second triode, and a base electrode of the twenty-second triode is connected with a source electrode of the twenty-first NMOS tube;
a twenty-fifth PMOS tube, the grid electrode of which is connected with the drain electrode of the twenty-third PMOS tube, the source electrode of which is connected with the VCC end, the drain electrode of which is used as the output end through an inverter,
and the grid electrode of the twenty-sixth NMOS tube is connected with the third bias signal end, the source electrode of the twenty-sixth NMOS tube is grounded, and the drain electrode of the twenty-fifth NMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube.
As an example, the working logic of the digital logic circuit is:
when the first input end receives the trigger signal, the first output end is set to be low level, and the second output end is set to be high level;
when the second input end receives the trigger signal, the second output end is set to be low level, and the first output end is set to be high level.
Examples:
as shown in fig. 2, in the present embodiment, the turn-on circuit includes resistors R1, R2, R3 for detecting the VDDQ voltage value; generating R5 and C1 of the conversion frequency; a comparator circuit.
In the on-time circuit, the resistor r1=r2=r3 detects the output voltage value VDDQ of DC-DC,the voltage value is used as a reference voltage of the comparator; the enable signal EN turns on the NMOS1 to detect the SW port voltage (POWER 1 on, SW port voltage is approximately equal to the POWER supply voltage Vin), and the SW port charges the resistor R5 and the capacitor C1. Therefore, on time +.>When DRVH is high, POWER1 is turned on, and the voltage value of SW port is equal to Vin, SW charges R5 and C1, the voltage value of R800_NEG is gradually increased, and when it reaches->At the time of the voltage value, the inverter INV outputs a low level signal. This signal causes DRVH to be low, POWER1 is turned off, POWER2 is turned on, and VDDQ starts to decrease at this time; when the feedback voltage FB is lower than the reference voltage 0.75V, the PWM comparator outputs a low level, so that POWER2 is turned off, POWER1 is turned on, the DC-DC output terminal VDDQ voltage starts to increase, the feedback voltage FB increases, and the SW port voltage is approximately equal to the POWER supply voltage Vin, and SW charges R5 and C1. This completes a cycle process.
In the POWER1 conducting state, the POWER voltage Vin can be periodically detected, so that the conversion frequency is a fixed value; meanwhile, the on time is regulated by regulating the duty ratio D, and the on time is in direct proportion to the output voltage VDDQ and in inverse proportion to the input voltage Vin.
The invention has the main function of enabling the conversion frequency to be a fixed value, avoiding the conversion frequency of the traditional hysteresis control mode from being influenced by ESR, inductance L and other parameters, further effectively reducing EMI interference and effectively improving the reliability and stability of equipment in the system.
FIG. 3 is a logic timing diagram of the on-time circuit and the PWM comparator control power transistor.
The output signal of the on-time circuit is low, the signal makes DRVH be low, POWER1 is closed, DRVL be high after delay time, and POWER2 is turned on; the PWM output signal is low, DRVL is low, POWER2 is off, DRVH is high, and POWER1 is on after a delay time.
Fig. 4 is a switch selection circuit configuration.
An important feature of the present invention is the dual control mode, which requires the switch select circuit to select the input signal of the corresponding PWM comparator according to the different control modes. The COMP port is used to select the control mode. The output end of the transconductance amplifier circuit is connected with the COMP port. When COMP is connected to the power supply voltage Vin, the chip works in the COT mode, the NMOS8 and the NMOS4 are turned on, and the reference voltage 0.75V is connected to the non-inverting input terminals 1 and 2 of the PWM comparator; NMOS6 and NMOS2 are conducted, and feedback voltage FB is connected with negative phase input ends 1 and 2 of the PWM comparator. When COMP is connected with external compensation circuits Rc and Cc, the chip works in a current mode, NMOS7 is conducted, and COMP is connected with a positive input end 1 of the PWM comparator; NMOS3 is conducted, and CS port voltage is connected with positive input end 2 of PWM comparator; NMOS5 is conducted, and reference voltage 1.2V is connected with negative phase input end 1 of PWM comparator; NMOS1 is conducted, and PGND is connected with negative phase input end 2 of PWM comparator.
Fig. 5 is a schematic diagram of the switch select circuit with reference voltage 0.75V and feedback voltage FB as input signals to the PWM comparator by connecting the COMP port to the power supply Vin to operate the chip in the COT mode.
Fig. 6 shows a chip operating in a current mode by connecting the COMP port to external compensation circuits Rc and Cc, and the switch selection circuit uses the reference voltage 1.2V, COMP port voltage, the CS port voltage, and the PGND port voltage as input signals to the PWM comparator.
Fig. 7 is a circuit configuration of the COT control mode with a fixed switching frequency.
The embodiment comprises the following steps: the chip is internally connected with feedback resistors Rf1 and Rf2, a PWM comparator, a conduction time circuit and a digital logic circuit in series; the peripheral devices include POWER switching transistors POWER1, POWER2, inductance L, and the like.
The working principle of the invention is that the inductance current generates ripple wave on ESR, when the ripple wave voltage gradually decreases, the feedback point FB voltage also decreases, when the feedback voltage FB is lower than the reference voltage 0.75V, the PWM comparator outputs low level, the signal makes POWER2 closed, POWER1 conducted, and the output voltage VDDQ begins to increase; after POWER1 is turned on, in the on-time circuit, the SW port charges R5 and C1 to generate ripple voltage, the voltage reaches the reference voltageAt this time, the on-time circuit outputs a low level, which turns off POWER1, POWER2 is turned on, and the output voltage VDDQ starts to drop.
Fig. 8 is a circuit configuration of a current control mode with a fixed switching frequency.
The embodiment comprises the following steps: the chip is internally connected with feedback resistors Rf1 and Rf2, a transconductance amplifier, a PWM comparator, a conduction time circuit and a digital logic circuit in series; the peripheral devices include POWER switching transistors POWER1, POWER2, an inductor L, a current detection resistor Rs, and the like. Based on the COT mode, a transconductance amplifier, an external detection resistor Rs and compensation circuits Rc and Cc are added, so that the chip has a current control mode.
The working principle of the invention is that POWER2 is conducted, voltage drop is generated on a detection resistor Rs, and the difference value generated by the voltage value and PGND is compared with the difference value generated by COMP port voltage and reference 1.2V through a PWM comparator, so that the conduction state or the closing state of a POWER switch tube is controlled.
The transconductance amplifier is mainly utilized for designing the current mode, the loop gain is increased, and the output voltage precision is improved. The gain of the feedback voltage FB to the output terminal VDDQ isThe gain produced by the transconductance amplifier is A V2 ＝ G m×R 0 The method comprises the steps of carrying out a first treatment on the surface of the The gain of the PWM comparator and the power switch tube is +.>So the loop gain is +.>
Fig. 9 is an overall circuit simulation waveform. When the frequency is converted to 400KHz, the generated electromagnetic interference is the largest, and the interference is small on the other frequency points. Simulation results prove that the scheme is feasible, and the defect of the traditional hysteresis control mode is overcome.
Claims (4)
1. The fixed frequency dual-mode synchronous buck controller is characterized by comprising the following parts:
an on-time circuit having an output coupled to a first input of the digital logic circuit;
a comparator having an output connected to the second input of the digital logic circuit;
the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end and controlling the level states of the two output ends according to the level of the second input end;
the switch selection circuit is characterized in that a zero input end of the switch selection circuit is connected with an output end of the transconductance amplifier, a first input end of the switch selection circuit is connected with a feedback voltage end, a second input end of the switch selection circuit is connected with a first reference voltage end, a third input end of the switch selection circuit is connected with a CS end, a fourth input end of the switch selection circuit is connected with a PGND end, a fifth input end of the switch selection circuit is connected with a second reference voltage end, a first output end of the switch selection circuit is connected with a first negative input end of the comparator, a second output end of the switch selection circuit is connected with a first positive input end of the comparator, a third output end of the switch selection circuit is connected with a second positive input end of the comparator, and a fourth output end of the switch selection circuit is connected with a second negative input end of the comparator according to a zero input end signal;
the positive input end of the transconductance amplifier is connected with the second reference voltage end, and the negative input end of the transconductance amplifier is connected with the feedback voltage end.
2. The fixed frequency dual mode synchronous buck controller according to claim 1, wherein the on-time circuit includes:
a switching voltage detection circuit formed by serially connecting resistors,
the SW port voltage detection circuit comprises a twenty-first NMOS tube and a twenty-eighth NMOS tube, wherein the source electrode of the twenty-first NMOS tube is connected with the drain electrode of the twenty-eighth NMOS tube and a twenty-fifth resistor, the twenty-fifth resistor is grounded through a capacitor, the source electrode of the twenty-eighth NMOS tube is grounded, and the source electrode of the twenty-first NMOS tube is used as an output end;
a twenty-first PMOS tube, wherein the source electrode of the twenty-first PMOS tube is connected with the VCC end, the drain electrode of the twenty-first PMOS tube is grounded through the twenty-first triode, and the grid electrode of the twenty-first PMOS tube is connected with the first bias signal end;
a twenty-first triode, the base electrode of which is connected with the output end of the conversion voltage detection circuit;
a twenty-second PMOS tube, the source electrode of which is connected with the VCC end, and the grid electrode and the drain electrode of which are connected with the drain electrode of the twenty-fifth NMOS tube;
a twenty-fifth NMOS tube, the grid electrode of which is connected with the second bias signal end, the source electrode of which is connected with the drain electrode of the twenty-second NMOS tube,
a twenty-second NMOS tube, a grid electrode connected with the drain electrode of the twenty-first PMOS tube, a source electrode connected with the drain electrode of the twenty-seventh NMOS tube, a source electrode of the twenty-seventh NMOS tube grounded,
a twenty-third PMOS tube, the grid electrode of which is connected with the grid electrode of the twenty-second PMOS tube, the source electrode of which is connected with the VCC end, the drain electrode of which is connected with the drain electrode of the twenty-fourth NMOS tube,
a grid electrode of the twenty-fourth NMOS tube is connected with the second bias signal end, and a source electrode of the twenty-fourth NMOS tube is connected with a drain electrode of the twenty-third NMOS tube;
a source electrode of the twenty-third NMOS tube is connected with a drain electrode of the twenty-seventh NMOS tube;
the grid electrode of the twenty-seventh NMOS tube is connected with a third bias signal end;
a grid electrode of the twenty-fourth PMOS tube is connected with a first bias signal end, a source electrode of the twenty-fourth PMOS tube is connected with a VCC end, a drain electrode of the twenty-fourth PMOS tube is grounded through a twenty-second triode, and a base electrode of the twenty-second triode is connected with a source electrode of the twenty-first NMOS tube;
a twenty-fifth PMOS tube, the grid electrode of which is connected with the drain electrode of the twenty-third PMOS tube, the source electrode of which is connected with the VCC end, the drain electrode of which is used as the output end through an inverter,
and the grid electrode of the twenty-sixth NMOS tube is connected with the third bias signal end, the source electrode of the twenty-sixth NMOS tube is grounded, and the drain electrode of the twenty-fifth NMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube.
3. The fixed frequency dual mode synchronous buck controller according to claim 1, wherein the operating logic of the digital logic circuit is:
when the first input end receives the trigger signal, the first output end is set to be low level, and the second output end is set to be high level;
when the second input end receives the trigger signal, the second output end is set to be low level, and the first output end is set to be high level.
4. The fixed frequency dual mode synchronous buck controller according to claim 3, wherein,
when the first input end receives the trigger signal, the first output end is set to be at a low level, and after a preset second time delay, the second output end is set to be at a high level;
when the second input end receives the trigger signal, the second output end is set to be at a low level, and after a preset first time delay, the first output end is set to be at a high level.
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