CN108023464A - A kind of super-low standby power consumption circuit for motor drive ic - Google Patents

A kind of super-low standby power consumption circuit for motor drive ic Download PDF

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Publication number
CN108023464A
CN108023464A CN201711441909.0A CN201711441909A CN108023464A CN 108023464 A CN108023464 A CN 108023464A CN 201711441909 A CN201711441909 A CN 201711441909A CN 108023464 A CN108023464 A CN 108023464A
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resistance
tube
signals
pmos
nmos
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CN108023464B (en
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吴国明
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SHANGHAI SILLUMIN SEMICONDUCTOR Co Ltd
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SHANGHAI SILLUMIN SEMICONDUCTOR Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Ac Motors In General (AREA)

Abstract

The invention discloses a kind of super-low standby power consumption circuit for motor drive ic, including logic control element to produce P_CTRL and N_CTRL signals according to IN1 the and IN2 signals of input through logical process；High-end power stage produces supply voltage VIN VDD according to IN1 the and IN2 signals of input；Low side power stage unit produces supply voltage VDD according to IN1 the and IN2 signals of input；High-side driver level is according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV signals that become larger；Low side driving stage is according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV signals that become larger；Resistance R1 one end is connected with the output terminal of high-side driver level and the grid of PMOS power tubes P1, and the other end is connected with the source electrode of the input terminal and PMOS power tubes P1 of high-side driver level and high-end power stage；Resistance R2 one end is connected with the output terminal of low side driving stage and the grid of NMOS power tubes N1, and the other end is connected and while is grounded with the source electrode of NMOS power tubes N1；The drain electrode of PMOS power tubes P1 is connected with the drain electrode of NMOS power tubes N1.

Description

A kind of super-low standby power consumption circuit for motor drive ic
Technical field
The present invention relates to technical field of electronic products, more particularly to a kind of super-low standby power consumption for motor drive ic Circuit.
Background technology
At present, people are higher and higher to the performance requirement of portable product, this is not only shown to body of velocity proved recipe face It is substantially improved, power problems equally have the function that to hold the balance, if power problems do not solve, the convenience of product and user Experience will be greatly affected.
However, with the lifting of circuit speed, theoretically the power consumption of circuit also can proportional increase；In addition from mesh Preceding Industry sees that the speed of circuit performance lifting is much larger than the increased speed of battery capacity again.Two above factor is determined The index for having determined product power consumption will directly affect the performance of product, have decisive influence to the competitiveness of product.
Green energy conservation is the developing direction of whole electronics industry, with the application and development of various mobile electronic devices, such as The stand-by time what extends equipment increasingly becomes the problem that everybody pays close attention to.Motor drive ic is as various mobile printing devices In acp chip, it is also desirable to meet the design concept of super-low standby power consumption.
The content of the invention
In order to overcome deficiency of the prior art, the present invention provides a kind of super-low standby power consumption for motor drive ic Circuit, it is intended to reduce stand-by power consumption.
In order to reach foregoing invention purpose, technical solution is as follows used by solving its technical problem：
A kind of super-low standby power consumption circuit for motor drive ic, including logic control element, high-end power stage list Member, low side power stage unit, high-side driver level unit, low side driving stage unit, resistance R1, resistance R2, PMOS power tube P1 and NMOS power tube N1, wherein：
The logic control element produces P_CTRL and N_ according to IN1 the and IN2 signals of input after logical process CTRL signal；
The high-end power stage unit produces supply voltage VIN-VDD according to IN1 the and IN2 signals of input, for institute State the power supply of high-side driver level unit；
The low side power stage unit produces supply voltage VDD according to IN1 the and IN2 signals of input, for described low Hold driving stage unit and logic control element power supply；
The high-side driver level unit is according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV that becomes larger Signal；
The low side driving stage unit is according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV that becomes larger Signal；
Described resistance R1 one end connects with the output terminal of the high-side driver level unit and the grid of the PMOS power tubes P1 Connect, the other end and the high-side driver level unit and the input terminal of high-end power stage unit and the source of the PMOS power tubes P1 Pole connects；
Described resistance R2 one end connects with the output terminal of the low side driving stage unit and the grid of the NMOS power tubes N1 Connect, the other end is connected and while is grounded with the source electrode of the NMOS power tubes N1；
The drain electrode of the PMOS power tubes P1 is connected with the drain electrode of the NMOS power tubes N1.
Further, the low side power stage unit include NMOS tube N2, NMOS tube N3, NMOS tube N4, PMOS tube P2, PMOS tube P3, resistance R3, resistance R4 and voltage-stabiliser tube Z1, wherein：
The grid connection IN1 signals of the NMOS tube N2, it, which drains, connects one end of the resistance R3, its source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N3, it, which drains, connects one end of the resistance R3, its source electrode ground connection；
The grid of the PMOS tube P2 connects the grid of the PMOS tube P3, its source electrode connects the PMOS tube P3's respectively The drain electrode of source electrode and the NMOS tube N4, it, which drains, connects the other end of the resistance R3；
The other end of the resistance R3 is also connected to the grid of the PMOS tube P2 and the grid of the PMOS tube P3 at the same time；
The drain electrode of the PMOS tube P3 connects the anode of the voltage-stabiliser tube Z1, one end of the resistance R4 and described respectively The grid of NMOS tube N4；
The plus earth of the voltage-stabiliser tube Z1；
The other end ground connection of the resistance R4；
The source electrode connection supply voltage VDD of the NMOS tube N4.
Further, the low side driving stage unit includes several phase inverters, several described phase inverters are sequentially connected in series Connection, the input terminal input N_CTRL signals of first phase inverter, the recommending output mode N_DRV signals after several phase inverters.
Further, the high-end power stage unit includes NMOS tube N5, NMOS tube N6, PMOS tube P4, resistance R5, resistance R6, resistance R7 and voltage-stabiliser tube Z2, wherein：
The grid connection IN1 signals of the NMOS tube N5, it, which drains, connects one end of the resistance R5, its source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N6, it, which drains, connects one end of the resistance R5, its source electrode ground connection；
The one end of the anode of the voltage-stabiliser tube Z2 respectively with the resistance R6 and resistance R7 is connected；
The other end of the resistance R5 other end with the resistance R6, the cathode of the voltage-stabiliser tube Z2 and described respectively The grid connection of PMOS tube P4；
The source electrode of the PMOS tube P4 connects the other end of the resistance R7, its grounded drain.
Further, the high-side driver level unit includes several phase inverters, several described phase inverters are sequentially connected in series Connection, the input terminal input P_CTRL signals of first phase inverter, the recommending output mode P_DRV signals after several phase inverters.
The present invention is due to using above technical scheme, being allowed to compared with prior art, have the following advantages that and actively imitate Fruit：
In a kind of super-low standby power consumption circuit for motor drive ic of the invention, when input signal IN1 and IN2 are When low, low side power stage unit and high-end power stage unit do not produce VDD and VIN-VDD voltages all in off state, so High-side driver level unit and low side driving stage unit are also in off state, at this time, PMOS power tube P1 and NMOS power tubes N1 is pulled up and pulled down by resistance R1 and R2 respectively, is also in off state.And logic control element without VDD also because supply Electricity, is also at off state.Because whole system circuit does not consume any quiescent current all in off state, whole circuit, Therefore it can realize ultra low quiescent power consumption.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment Attached drawing be briefly described.It is clear that drawings in the following description are only some embodiments of the present invention, for ability For field technique personnel, without creative efforts, other attached drawings can also be obtained according to these attached drawings.It is attached In figure：
Fig. 1 is a kind of integrated circuit schematic diagram of super-low standby power consumption circuit for motor drive ic of the invention；
Fig. 2 is a kind of super-low standby power consumption circuit low and middle-end power stage element circuit for motor drive ic of the invention Schematic diagram；
Fig. 3 is a kind of super-low standby power consumption circuit low and middle-end driving stage element circuit for motor drive ic of the invention Schematic diagram；
Fig. 4 is a kind of super-low standby power consumption circuit middle and high end power stage element circuit for motor drive ic of the invention Schematic diagram；
Fig. 5 is a kind of super-low standby power consumption circuit middle and high end driving stage element circuit for motor drive ic of the invention Schematic diagram.
Embodiment
Below with reference to the attached drawing of the present invention, clear, complete description is carried out to the technical solution in the embodiment of the present invention And discussion, it is clear that as described herein is only a part of example of the present invention, is not whole examples, based on the present invention In embodiment, the every other implementation that those of ordinary skill in the art are obtained on the premise of creative work is not made Example, belongs to protection scope of the present invention.
As shown in Figure 1, present embodiment discloses a kind of super-low standby power consumption circuit for motor drive ic, including patrol Collect control unit, high-end power stage unit, low side power stage unit, high-side driver level unit, low side driving stage unit, resistance R1, resistance R2, PMOS power tube P1 and NMOS power tube N1, wherein：
The logic control element produces P_CTRL and N_ according to IN1 the and IN2 signals of input after logical process CTRL signal；When P_CTRL is high, passes through high-side driver level unit and drive PMOS power tubes P1 to open.When N_CTRL is height When, drive NMOS power tubes N1 to open by low side driving stage unit.
The high-end power stage unit produces supply voltage VIN-VDD according to IN1 the and IN2 signals of input, for institute State the power supply of high-side driver level unit；
The low side power stage unit produces supply voltage VDD according to IN1 the and IN2 signals of input, for described low Hold driving stage unit and logic control element power supply；
The high-side driver level unit is according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV that becomes larger Signal；
The low side driving stage unit is according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV that becomes larger Signal；
Described resistance R1 one end connects with the output terminal of the high-side driver level unit and the grid of the PMOS power tubes P1 Connect, the other end and the high-side driver level unit and the input terminal of high-end power stage unit and the source of the PMOS power tubes P1 Pole connects, for when the difference power supply of high-side driver level unit is zero, the grid of pull-up PMOS power tubes P1 to ensure to VIN PMOS power tubes P1 is turned off.
Described resistance R2 one end connects with the output terminal of the low side driving stage unit and the grid of the NMOS power tubes N1 Connect, the other end be connected with the source electrode of the NMOS power tubes N1 and while be grounded, for the power vd D in low side driving stage unit When being zero, the grid of pull-down NMOS power tube N1 ensures NMOS power tubes N1 shut-offs to ground.
The drain electrode of the PMOS power tubes P1 is connected with the drain electrode of the NMOS power tubes N1.
In Fig. 1, IN1 and IN2 are input control signals, and specific logic is shown in Table 1：
IN1 IN2 PMOS NMOS
0 0 OFF OFF
0 1 OFF ON
1 0 ON OFF
1 1 OFF OFF
Table 1
When IN1 is low, IN2 is low, PMOS power tube P1 and NMOS power tubes N1 is turned off.When IN1 for it is low, When IN2 is high, PMOS power tubes P1 shut-offs, NMOS power tubes N1 is opened.When IN1 is high, IN2 is low, PMOS Power tube P1 is opened, NMOS power tubes N1 shut-offs.When IN1 is high, IN2 is high, PMOS power tubes P1 shut-offs, NMOS work( Rate pipe N1 be also switched off (logical interlock, prevent PMOS power tubes P1 and NMOS power tube N1 and meanwhile opening cause short circuit, so at the same time It is turned off, the input logic of IN1 and IN2 will not occur for height at the same time under normal circumstances).Due to logic control element and have VDD powers, and when IN1 or IN2 is high, vdd voltage is normal, logic control element normal work.When IN1 and IN2 are low, It is zero that VDD, which is turned off, so logic control element does not consume any quiescent current.
As shown in Fig. 2, the low side power stage unit include NMOS tube N2, NMOS tube N3, NMOS tube N4, PMOS tube P2, PMOS tube P3, resistance R3, resistance R4 and voltage-stabiliser tube Z1, wherein：
The grid connection IN1 signals of the NMOS tube N2, it, which drains, connects one end of the resistance R3, its source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N3, it, which drains, connects one end of the resistance R3, its source electrode ground connection；
The grid of the PMOS tube P2 connects the grid of the PMOS tube P3, its source electrode connects the PMOS tube P3's respectively The drain electrode of source electrode and the NMOS tube N4, it, which drains, connects the other end of the resistance R3；
The other end of the resistance R3 is also connected to the grid of the PMOS tube P2 and the grid of the PMOS tube P3 at the same time；
The drain electrode of the PMOS tube P3 connects the anode of the voltage-stabiliser tube Z1, one end of the resistance R4 and described respectively The grid of NMOS tube N4；
The plus earth of the voltage-stabiliser tube Z1；
The other end ground connection of the resistance R4；
The source electrode connection supply voltage VDD of the NMOS tube N4.
Specifically, in low side power stage element circuit figure, when IN1 and IN2 is low, NMOS tube N2 and NMOS Pipe N3 is all in off state, therefore no electric current flows through PMOS tube P2 and PMOS tube P3, meanwhile, also no electric current flows through voltage stabilizing The grid voltage G1 of pipe Z1, NMOS tube N4 move zero to by resistance R4, so the source voltage VDD of NMOS tube N4 is also zero.At this time, Low side power stage unit does not consume any quiescent current.When any one IN1 or IN2 become higher, NMOS tube N2 or NMOS tube N3 In open mode, there is electric current to flow through PMOS tube P2 and PMOS tube P3, so there is electric current to flow through voltage-stabiliser tube Z1 and resistance R4.Such as The voltage of voltage regulation of 6V is produced in G1 points, at this moment NMOS tube N4 is opened, and produces a vdd voltage, this magnitude of voltage is equal to 6V- VGS=5V, when voltage of voltage regulation G1 is equal to 6V, when the circuit of the gate source voltage VGS=1V, Fig. 2 of NMOS tube N4 are exactly to realize VDD is turned off when IN1 and IN2 is zero and does not consume quiescent dissipation, and when IN1 or IN2 is high, low side power stage Unit works normally, and produces a vdd voltage.
As shown in figure 3, the low side driving stage unit includes several phase inverters, several described phase inverters are sequentially connected in series Connection, the input terminal input N_CTRL signals of first phase inverter, the recommending output mode N_DRV signals after several phase inverters.Tool Body, the phase inverter that the low side driving stage unit is become larger by several recommends realization, and input signal is believed for N_CTRL Number, output signal is N_DRV signals.As a height of VDD of N_DRV signal outputs, NMOS power tubes N1 is opened.When N_DRV signals Export it is low for ground when, turn off NMOS power tubes N1.The circuit is simple and reliable, and when vdd voltage is zero, low side driving stage unit is not Consume any quiescent current.
As shown in figure 4, the high-end power stage unit includes NMOS tube N5, NMOS tube N6, PMOS tube P4, resistance R5, electricity R6, resistance R7 and voltage-stabiliser tube Z2 are hindered, wherein：
The grid connection IN1 signals of the NMOS tube N5, it, which drains, connects one end of the resistance R5, its source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N6, it, which drains, connects one end of the resistance R5, its source electrode ground connection；
The one end of the anode of the voltage-stabiliser tube Z2 respectively with the resistance R6 and resistance R7 is connected；
The other end of the resistance R5 other end with the resistance R6, the cathode of the voltage-stabiliser tube Z2 and described respectively The grid connection of PMOS tube P4；
The source electrode of the PMOS tube P4 connects the other end of the resistance R7, its grounded drain.
Specifically, in high-end power stage element circuit figure, when IN1 and IN2 is low, NMOS tube N5 and NMOS Pipe N6 is turned off, and no electric current flows through voltage-stabiliser tube Z2 and resistance R6, and the grid G 2 of PMOS tube P4 moves VIN, PMOS tube to by resistance R6 The source voltage of P4 also moves VIN to by resistance R7.When IN1 or IN2 voltages are high, NMOS tube N5 or NMOS tube N6 are opened, There is electric current to flow through voltage-stabiliser tube Z2 and resistance R6, the voltage of a voltage-stabiliser tube lower than VIN produced in the grid G 2 of PMOS tube P4, Such as 6V.So voltage VIN-VDD of one higher than the G2 voltage PMOS tube P4 gate source voltages of source electrode generation in PMOS tube P4.This A magnitude of voltage is equal to VIN-6V+VGS=VIN-5V, when voltage of voltage regulation G2 is equal to VIN-6V, as the gate source voltage VGS of PMOS tube P4 When=1V, the circuit of Fig. 4 is exactly to realize shut-off VIN-VDD when IN1 and IN2 is zero and do not consume static work( Consumption, and when IN1 or IN2 is high, high-end power stage unit normal work, and produce a VIN-VDD voltages.
As shown in figure 5, the high-side driver level unit includes several phase inverters, several described phase inverters are sequentially connected in series Connection, the input terminal input P_CTRL signals of first phase inverter, the recommending output mode P_DRV signals after several phase inverters.Tool Body, the phase inverter that the high-side driver level unit is become larger by several recommends realization, and input signal is believed for P_CTRL Number, output signal is P_DRV signals.When it is VIN-VDD that P_DRV signal outputs are low, PMOS power tubes P1 is opened.Work as P_DRV During a height of VIN of signal output, PMOS power tubes P1 is turned off.The circuit is simple and reliable, when VIN-VDD voltages are VIN, high-end drive Dynamic level unit does not consume any quiescent current.
In the present embodiment, when input signal IN1 and IN2 are low, low side power stage unit and high-end power stage unit All in off state, VDD and VIN-VDD voltages are not produced, so high-side driver level unit and low side driving stage unit are also all State is off, at this time, PMOS power tube P1 and NMOS power tubes N1 is pulled up and pulled down by resistance R1 and R2 respectively, is also all located In off state.And logic control element is also at off state also because powering without VDD.Because whole system circuit is all State is off, whole circuit does not consume any quiescent current, therefore can realize ultra low quiescent power consumption.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto, Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in, It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims Subject to.

Claims (5)

1. a kind of super-low standby power consumption circuit for motor drive ic, it is characterised in that including logic control element, high-end Power stage unit, low side power stage unit, high-side driver level unit, low side driving stage unit, resistance R1, resistance R2, PMOS work( Rate pipe P1 and NMOS power tube N1, wherein：
The logic control element produces P_CTRL and N_CTRL according to IN1 the and IN2 signals of input after logical process to be believed Number；
The high-end power stage unit produces supply voltage VIN-VDD according to IN1 the and IN2 signals of input, for the height Hold the power supply of driving stage unit；
The low side power stage unit produces supply voltage VDD according to IN1 the and IN2 signals of input, for being driven to the low side Dynamic level unit and logic control element power supply；
The high-side driver level unit is believed according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV become larger Number；
The low side driving stage unit is believed according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV become larger Number；
Described resistance R1 one end is connected with the output terminal of the high-side driver level unit and the grid of the PMOS power tubes P1, separately One end and the source electrode of the input terminal and the PMOS power tubes P1 of the high-side driver level unit and high-end power stage unit connect Connect；
Described resistance R2 one end is connected with the output terminal of the low side driving stage unit and the grid of the NMOS power tubes N1, separately One end is connected and while is grounded with the source electrode of the NMOS power tubes N1；
The drain electrode of the PMOS power tubes P1 is connected with the drain electrode of the NMOS power tubes N1.
A kind of 2. super-low standby power consumption circuit for motor drive ic according to claim 1, it is characterised in that institute Stating low side power stage unit includes NMOS tube N2, NMOS tube N3, NMOS tube N4, PMOS tube P2, PMOS tube P3, resistance R3, resistance R4 and voltage-stabiliser tube Z1, wherein：
The grid connection IN1 signals of the NMOS tube N2, it, which drains, connects one end of the resistance R3, its source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N3, it, which drains, connects one end of the resistance R3, its source electrode ground connection；
The grid of the PMOS tube P2 connects the grid of the PMOS tube P3, its source electrode connects the source electrode of the PMOS tube P3 respectively With the drain electrode of the NMOS tube N4, it, which drains, connects the other end of the resistance R3；
The other end of the resistance R3 is also connected to the grid of the PMOS tube P2 and the grid of the PMOS tube P3 at the same time；
The drain electrode of the PMOS tube P3 connects the anode of the voltage-stabiliser tube Z1, one end of the resistance R4 and the NMOS respectively The grid of pipe N4；
The plus earth of the voltage-stabiliser tube Z1；
The other end ground connection of the resistance R4；
The source electrode connection supply voltage VDD of the NMOS tube N4.
A kind of 3. super-low standby power consumption circuit for motor drive ic according to claim 1, it is characterised in that institute Stating low side driving stage unit includes several phase inverters, several described phase inverters are sequentially connected in series, first phase inverter Input terminal inputs N_CTRL signals, the recommending output mode N_DRV signals after several phase inverters.
A kind of 4. super-low standby power consumption circuit for motor drive ic according to claim 1, it is characterised in that institute Stating high-end power stage unit includes NMOS tube N5, NMOS tube N6, PMOS tube P4, resistance R5, resistance R6, resistance R7 and voltage-stabiliser tube Z2, wherein：
The grid connection IN1 signals of the NMOS tube N5, it, which drains, connects one end of the resistance R5, its source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N6, it, which drains, connects one end of the resistance R5, its source electrode ground connection；
The one end of the anode of the voltage-stabiliser tube Z2 respectively with the resistance R6 and resistance R7 is connected；
The other end of the resistance R5 other end with the resistance R6, the cathode of the voltage-stabiliser tube Z2 and the PMOS respectively The grid connection of pipe P4；
The source electrode of the PMOS tube P4 connects the other end of the resistance R7, its grounded drain.
A kind of 5. super-low standby power consumption circuit for motor drive ic according to claim 1, it is characterised in that institute Stating high-side driver level unit includes several phase inverters, several described phase inverters are sequentially connected in series, first phase inverter Input terminal inputs P_CTRL signals, the recommending output mode P_DRV signals after several phase inverters.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112350552A (en) * 2020-10-29 2021-02-09 西安微电子技术研究所 MOSFET driver with output peak current not affected by power supply voltage change
CN114244148A (en) * 2021-12-06 2022-03-25 无锡市晶源微电子有限公司 Switching power supply output driving device

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