CN108023464B

CN108023464B - Ultralow standby power consumption circuit for motor driving chip

Info

Publication number: CN108023464B
Application number: CN201711441909.0A
Authority: CN
Inventors: 吴国明
Original assignee: Shanghai Sillumin Semiconductor Co ltd
Current assignee: Shanghai Sillumin Semiconductor Co ltd
Priority date: 2017-12-26
Filing date: 2017-12-26
Publication date: 2023-12-19
Anticipated expiration: 2037-12-26
Also published as: CN108023464A

Abstract

The invention discloses an ultralow standby power consumption circuit for a motor driving chip, which comprises a logic control unit, a logic control unit and a control unit, wherein the logic control unit is used for generating P_CTRL and N_CTRL signals through logic processing according to input IN1 and IN2 signals; the high-end power supply stage generates power supply voltage VIN-VDD according to the IN1 and IN2 signals input; the low-side power supply stage unit generates a power supply voltage VDD according to the input IN1 and IN2 signals; the P_CTRL signal input by the high-end driving stage is pushed and pulled by the gradually-enlarged inverter to output a P_DRV signal; the N_CTRL signal input by the low-end driving stage is pushed and pulled by the gradually-enlarged inverter to output an N_DRV signal; one end of the resistor R1 is connected with the output end of the high-end driving stage and the grid electrode of the PMOS power tube P1, and the other end of the resistor R1 is connected with the input ends of the high-end driving stage and the high-end power supply stage and the source electrode of the PMOS power tube P1; one end of the resistor R2 is connected with the output end of the low-end driving stage and the grid electrode of the NMOS power tube N1, and the other end of the resistor R2 is connected with the source electrode of the NMOS power tube N1 and is grounded at the same time; the drain electrode of the PMOS power tube P1 is connected with the drain electrode of the NMOS power tube N1.

Description

Ultralow standby power consumption circuit for motor driving chip

Technical Field

The invention relates to the technical field of electronic products, in particular to an ultralow standby power consumption circuit for a motor driving chip.

Background

At present, the performance requirements of people on portable products are higher and higher, the speed experience is greatly improved, the power consumption problem has a significant effect, and if the power consumption problem is not solved, the convenience of the products and the user experience are greatly affected.

However, as circuit speed increases, power consumption of the circuit will also increase in proportion to theory; in addition, from the current industry development state, the speed of improving the circuit performance is far greater than the speed of increasing the battery capacity. The two factors determine the index of the power consumption of the product, which directly influences the performance of the product and has a decisive influence on the competitiveness of the product.

Green energy conservation is a development direction of the whole electronic industry, and with the application and development of various mobile electronic devices, how to extend the standby time of the devices becomes a more and more interesting subject. The motor driving chip is used as a core chip in various mobile printing devices, and also needs to meet the design concept of ultra-low standby power consumption.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides an ultralow standby power consumption circuit for a motor driving chip, which aims to reduce standby power consumption.

In order to achieve the above object, the technical scheme adopted for solving the technical problems is as follows:

the utility model provides an ultra-low standby power consumption circuit for motor drive chip, includes logic control unit, high-end power supply level unit, low-end power supply level unit, high-end drive level unit, low-end drive level unit, resistance R1, resistance R2, PMOS power tube P1 and NMOS power tube N1, wherein:

the logic control unit generates P_CTRL and N_CTRL signals after logic processing according to the input IN1 and IN2 signals;

the high-end power supply stage unit generates a power supply voltage VIN-VDD according to the input IN1 and IN2 signals and is used for supplying power to the high-end drive stage unit;

the low-end power supply stage unit generates a power supply voltage VDD according to the input IN1 and IN2 signals and is used for supplying power to the low-end driving stage unit and the logic control unit;

the high-end driving stage unit outputs a P_DRV signal in a push-pull way by an inverter which is gradually increased according to the input P_CTRL signal;

the low-end driving stage unit outputs an N_DRV signal in a push-pull way by an inverter which is gradually increased according to the input N_CTRL signal;

one end of the resistor R1 is connected with the output end of the high-end driving stage unit and the grid electrode of the PMOS power tube P1, and the other end of the resistor R1 is connected with the input ends of the high-end driving stage unit and the high-end power supply stage unit and the source electrode of the PMOS power tube P1;

one end of the resistor R2 is connected with the output end of the low-end driving stage unit and the grid electrode of the NMOS power tube N1, and the other end of the resistor R2 is connected with the source electrode of the NMOS power tube N1 and is grounded at the same time;

the drain electrode of the PMOS power tube P1 is connected with the drain electrode of the NMOS power tube N1.

Further, the low-end power supply stage unit comprises an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, a PMOS tube P2, a PMOS tube P3, a resistor R4 and a voltage stabilizing tube Z1, wherein:

the grid electrode of the NMOS tube N2 is connected with an IN1 signal, the drain electrode of the NMOS tube N2 is connected with one end of the resistor R3, and the source electrode of the NMOS tube N2 is grounded;

the grid electrode of the NMOS tube N3 is connected with an IN2 signal, the drain electrode of the NMOS tube N3 is connected with one end of the resistor R3, and the source electrode of the NMOS tube N3 is grounded;

the grid electrode of the PMOS tube P2 is connected with the grid electrode of the PMOS tube P3, the source electrode of the PMOS tube P3 and the drain electrode of the NMOS tube N4 are respectively connected with the source electrode of the PMOS tube P3, and the drain electrode of the NMOS tube N4 is connected with the other end of the resistor R3;

the other end of the resistor R3 is also connected to the grid electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P3 at the same time;

the drain electrode of the PMOS tube P3 is respectively connected with the negative electrode of the voltage stabilizing tube Z1, one end of the resistor R4 and the grid electrode of the NMOS tube N4;

the positive electrode of the voltage stabilizing tube Z1 is grounded;

the other end of the resistor R4 is grounded;

the source electrode of the NMOS tube N4 is connected with a power supply voltage VDD.

Further, the low-end driving stage unit comprises a plurality of inverters, the inverters are sequentially connected in series, the input end of the first inverter inputs an N_CTRL signal, and the N_DRV signal is outputted in a push-pull manner after passing through the inverters.

Further, the high-end power supply stage unit comprises an NMOS tube N5, an NMOS tube N6, a PMOS tube P4, a resistor R5, a resistor R6, a resistor R7 and a voltage stabilizing tube Z2, wherein:

the grid electrode of the NMOS tube N5 is connected with an IN1 signal, the drain electrode of the NMOS tube N5 is connected with one end of the resistor R5, and the source electrode of the NMOS tube N5 is grounded;

the grid electrode of the NMOS tube N6 is connected with an IN2 signal, the drain electrode of the NMOS tube N is connected with one end of the resistor R5, and the source electrode of the NMOS tube N is grounded;

the negative electrode of the voltage stabilizing tube Z2 is connected with one end of the resistor R6 and one end of the resistor R7 respectively;

the other end of the resistor R5 is respectively connected with the other end of the resistor R6, the positive electrode of the voltage stabilizing tube Z2 and the grid electrode of the PMOS tube P4;

and the source electrode of the PMOS tube P4 is connected with the other end of the resistor R7, and the drain electrode of the PMOS tube P is grounded.

Further, the high-end driving stage unit comprises a plurality of inverters, the inverters are sequentially connected in series, the input end of the first inverter inputs the P_CTRL signal, and the P_DRV signal is outputted in a push-pull manner after passing through the inverters.

Compared with the prior art, the invention has the following advantages and positive effects due to the adoption of the technical scheme:

IN the ultralow standby power consumption circuit for the motor driving chip, when input signals IN1 and IN2 are low, the low-end power supply stage unit and the high-end power supply stage unit are IN an off state and do not generate VDD and VIN-VDD voltages, so that the high-end driving stage unit and the low-end driving stage unit are IN the off state, and at the moment, the PMOS power tube P1 and the NMOS power tube N1 are respectively pulled up and pulled down by the resistors R1 and R2 and are also IN the off state. The logic control unit is also in an off state because no VDD is supplied. Because the whole system circuit is in an off state, the whole circuit does not consume any static current, and thus the ultralow static power consumption can be realized.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the invention and that other drawings may be obtained from these drawings by those skilled in the art without inventive effort. In the accompanying drawings:

FIG. 1 is a schematic diagram of an overall circuit of an ultra low standby power circuit for a motor drive chip according to the present invention;

FIG. 2 is a schematic diagram of a low-side power stage unit circuit in an ultra-low standby power circuit for a motor driver chip according to the present invention;

FIG. 3 is a schematic diagram of a low-side driver stage unit in an ultra-low standby power circuit for a motor driver chip according to the present invention;

FIG. 4 is a schematic diagram of a high-side power stage unit circuit in an ultra-low standby power circuit for a motor driver chip according to the present invention;

fig. 5 is a schematic diagram of a high-side driver stage unit in an ultra-low standby power circuit for a motor driver chip according to the present invention.

Detailed Description

The following description and the discussion of the embodiments of the present invention will be made more complete and less in view of the accompanying drawings, in which it is to be understood that the invention is not limited to the embodiments of the invention disclosed and that it is intended to cover all such modifications as fall within the scope of the invention.

As shown in fig. 1, the embodiment discloses an ultralow standby power consumption circuit for a motor driving chip, which comprises a logic control unit, a high-end power supply stage unit, a low-end power supply stage unit, a high-end driving stage unit, a low-end driving stage unit, a resistor R1, a resistor R2, a PMOS power tube P1 and an NMOS power tube N1, wherein:

the logic control unit generates P_CTRL and N_CTRL signals after logic processing according to the input IN1 and IN2 signals; when P_CTRL is high, the PMOS power tube P1 is driven to be turned on by the high-side driving stage unit. When N_CTRL is high, the NMOS power transistor N1 is driven to turn on by the low-side driver stage unit.

one end of the resistor R1 is connected with the output end of the high-end driving stage unit and the grid electrode of the PMOS power tube P1, the other end of the resistor R1 is connected with the input ends of the high-end driving stage unit and the high-end power supply stage unit and the source electrode of the PMOS power tube P1, and the resistor R1 is used for pulling up the grid electrode of the PMOS power tube P1 to VIN when the differential power supply of the high-end driving stage unit is zero, so that the PMOS power tube P1 is ensured to be turned off.

One end of the resistor R2 is connected with the output end of the low-end driving stage unit and the grid electrode of the NMOS power tube N1, and the other end of the resistor R2 is connected with the source electrode of the NMOS power tube N1 and is grounded at the same time, so that when the power supply VDD of the low-end driving stage unit is zero, the grid electrode of the NMOS power tube N1 is pulled down to the ground, and the NMOS power tube N1 is ensured to be turned off.

IN fig. 1, IN1 and IN2 are input control signals, and specific logic is shown IN table 1:

IN1	IN2	PMOS	NMOS
				0	0	OFF	OFF
0	1	OFF	ON
				1	0	ON	OFF
1	1	OFF	OFF

TABLE 1

When IN1 is low and IN2 is low, both PMOS power transistor P1 and NMOS power transistor N1 are turned off. When IN1 is low and IN2 is high, the PMOS power transistor P1 is turned off and the NMOS power transistor N1 is turned on. When IN1 is high and IN2 is low, the PMOS power transistor P1 is turned on and the NMOS power transistor N1 is turned off. When IN1 is high and IN2 is high, the PMOS power transistor P1 is turned off, and the NMOS power transistor N1 is also turned off (logic interlock, preventing the PMOS power transistor P1 and the NMOS power transistor N1 from being turned on at the same time to cause a short circuit, so both are turned off at the same time, and normally the input logic of IN1 and IN2 will not be high at the same time). Since the logic control unit is also powered by VDD, when IN1 or IN2 is high, the VDD voltage is normal and the logic control unit operates normally. When both IN1 and IN2 are low, VDD is turned off to zero, so the logic control unit does not consume any quiescent current.

As shown in fig. 2, the low-end power supply stage unit includes an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, a PMOS tube P2, a PMOS tube P3, a resistor R4, and a regulator tube Z1, where:

the positive electrode of the voltage stabilizing tube Z1 is grounded;

the other end of the resistor R4 is grounded;

Specifically, IN the low-side supply stage unit circuit diagram, when IN1 and IN2 are both low, the NMOS transistor N2 and the NMOS transistor N3 are both IN the off state, so that no current flows through the PMOS transistor P2 and the PMOS transistor P3, and simultaneously, no current flows through the voltage stabilizing transistor Z1, and the gate voltage G1 of the NMOS transistor N4 is pulled to zero by the resistor R4, so that the source voltage VDD of the NMOS transistor N4 is also zero. At this time, the low-side power stage unit does not consume any quiescent current. When either IN1 or IN2 becomes high, the NMOS transistor N2 or N3 is IN an open state, and a current flows through the PMOS transistor P2 and the PMOS transistor P3, so that a current flows through the regulator tube Z1 and the resistor R4. For example, a regulated voltage of 6V is generated at the G1 point, where the NMOS transistor N4 is turned on to generate a VDD voltage, the voltage value is equal to 6V-vgs=5v, when the regulated voltage G1 is equal to 6V, and when the gate-source voltage vgs=1v of the NMOS transistor N4, the circuit of fig. 2 is implemented to turn off VDD when IN1 and IN2 are both zero and not consume static power, and when IN1 or IN2 is high, the low-side power supply stage unit operates normally to generate a VDD voltage.

As shown in fig. 3, the low-end driving stage unit includes a plurality of inverters, the plurality of inverters are sequentially connected in series, the input end of the first inverter inputs the n_ctrl signal, and the n_drv signal is push-pull output after passing through the plurality of inverters. Specifically, the low-end driving stage unit is implemented by a plurality of gradually-enlarged inverters in a push-pull manner, the input signal is an N_CTRL signal, and the output signal is an N_DRV signal. When the n_drv signal output is high at VDD, the NMOS power transistor N1 is turned on. When the n_drv signal output is low to ground, the NMOS power transistor N1 is turned off. The circuit is simple and reliable, and the low-side drive stage unit does not consume any static current when the VDD voltage is zero.

As shown in fig. 4, the high-end power supply stage unit includes an NMOS transistor N5, an NMOS transistor N6, a PMOS transistor P4, a resistor R5, a resistor R6, a resistor R7, and a regulator Z2, where:

Specifically, IN the high-side power supply stage unit circuit diagram, when IN1 and IN2 are both low, the NMOS transistor N5 and the NMOS transistor N6 are turned off, no current flows through the voltage regulator Z2 and the resistor R6, the gate G2 of the PMOS transistor P4 is pulled to VIN by the resistor R6, and the source voltage of the PMOS transistor P4 is also pulled to VIN by the resistor R7. When the voltage IN1 or IN2 is high, the NMOS transistor N5 or N6 is turned on, and a current flows through the regulator Z2 and the resistor R6, and a voltage lower than VIN, for example, 6V is generated at the gate G2 of the PMOS transistor P4. Therefore, a voltage VIN-VDD higher than the G2 voltage of the gate-source voltage of the PMOS transistor P4 is generated at the source of the PMOS transistor P4. The circuit of fig. 4 is implemented to turn off VIN-VDD when IN1 and IN2 are both zero and not consume static power when IN1 or IN2 is high, and the high-side power stage unit operates normally and generates a VIN-VDD voltage when IN1 or IN2 is high, when the regulated voltage G2 is equal to VIN-6V and the gate-source voltage vgs=1v of the PMOS transistor P4.

As shown in fig. 5, the high-end driving stage unit includes a plurality of inverters, the plurality of inverters are sequentially connected in series, the input end of the first inverter inputs the p_ctrl signal, and the p_drv signal is outputted through push-pull after passing through the plurality of inverters. Specifically, the high-end driving stage unit is implemented by a plurality of gradually-enlarged inverters in a push-pull manner, an input signal is a P_CTRL signal, and an output signal is a P_DRV signal. When the P_DRV signal output is low to VIN-VDD, the PMOS power tube P1 is turned on. When the P_DRV signal output is VIN, the PMOS power tube P1 is turned off. The circuit is simple and reliable, and the high-end driving stage unit does not consume any static current when the VIN-VDD voltage is VIN.

IN this embodiment, when the input signals IN1 and IN2 are both low, the low-side power supply stage unit and the high-side power supply stage unit are both IN the off state, and no VDD and VIN-VDD voltages are generated, so that the high-side driving stage unit and the low-side driving stage unit are both IN the off state, and at this time, the PMOS power transistor P1 and the NMOS power transistor N1 are pulled up and pulled down by the resistors R1 and R2, respectively, and are both IN the off state. The logic control unit is also in an off state because no VDD is supplied. Because the whole system circuit is in an off state, the whole circuit does not consume any static current, and thus the ultralow static power consumption can be realized.

The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. The utility model provides an ultra-low standby power consumption circuit for motor drive chip, its characterized in that includes logic control unit, high-end power supply level unit, low-end power supply level unit, high-end drive level unit, low-end drive level unit, resistance R1, resistance R2, PMOS power tube P1 and NMOS power tube N1, wherein:

the high-end power supply stage unit comprises an NMOS tube N5, an NMOS tube N6, a PMOS tube P4, a resistor R5, a resistor R6, a resistor R7 and a voltage stabilizing tube Z2, wherein:

the source electrode of the PMOS tube P4 is connected with the other end of the resistor R7, and the drain electrode of the PMOS tube P is grounded;

the low-end power supply stage unit comprises an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, a PMOS tube P2, a PMOS tube P3, a resistor R4 and a voltage stabilizing tube Z1, wherein:

the positive electrode of the voltage stabilizing tube Z1 is grounded;

the other end of the resistor R4 is grounded;

the source electrode of the NMOS tube N4 is connected with a power supply voltage VDD;

the high-end driving stage unit comprises a plurality of inverters, the inverters are sequentially connected in series, the input end of the first inverter inputs a P_CTRL signal, and the P_DRV signal is output through push-pull after passing through the inverters;

the low-end driving stage unit comprises a plurality of inverters, the inverters are sequentially connected in series, the input end of the first inverter inputs an N_CTRL signal, and the N_DRV signal is output through push-pull after passing through the inverters;