CN207603436U - A kind of super-low standby power consumption circuit for motor drive ic - Google Patents
A kind of super-low standby power consumption circuit for motor drive ic Download PDFInfo
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- CN207603436U CN207603436U CN201721858092.2U CN201721858092U CN207603436U CN 207603436 U CN207603436 U CN 207603436U CN 201721858092 U CN201721858092 U CN 201721858092U CN 207603436 U CN207603436 U CN 207603436U
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Abstract
The utility model discloses a kind of super-low standby power consumption circuits for motor drive ic, P_CTRL and N_CTRL signals are generated through logical process according to IN1 the and IN2 signals of input including logic control element；High-end power stage generates supply voltage VIN VDD according to IN1 the and IN2 signals of input；Low side power stage unit generates supply voltage VDD according to IN1 the and IN2 signals of input；High-side driver grade is according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV signals that become larger；Low side driving stage is according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV signals that become larger；Resistance R1 one end is connect with the output terminal of high-side driver grade and the grid of PMOS power tubes P1, and the other end is connect with the source electrode of the input terminal and PMOS power tubes P1 of high-side driver grade and high-end power stage；Resistance R2 one end is connect with the output terminal of low side driving stage and the grid of NMOS power tubes N1, and the other end connect with the source electrode of NMOS power tubes N1 and is grounded simultaneously；The drain electrode of PMOS power tubes P1 is connect with the drain electrode of NMOS power tubes N1.
Description
Technical field
It is more particularly to a kind of for the ultralow standby of motor drive ic the utility model is related to technical field of electronic products
Power digital circuit.
Background technology
At present, people are higher and higher to the performance requirement of portable product, this is not only shown to body of velocity proved recipe face
It being substantially improved, power problems equally have the function of to hold the balance, if power problems do not solve, the convenience of product and user
Experience will be greatly affected.
However, with the promotion of circuit speed, theoretically the power consumption of circuit also can proportional increase；In addition from mesh
Preceding Industry sees that the speed that circuit performance is promoted is much larger than the increased speed of battery capacity again.Two above factor is determined
The performance that the index of product power consumption will directly affect product is determined, there is decisive influence to the competitiveness of product.
Green energy conservation is the developing direction of entire electronics industry, with the application and development of various mobile electronic devices, such as
The stand-by time what extends equipment increasingly becomes the subject that everybody pays close attention to.Motor drive ic is as various mobile printing devices
In acp chip, it is also desirable to meet the design concept of super-low standby power consumption.
Utility model content
In order to overcome deficiency of the prior art, the utility model provides a kind of for the ultralow standby of motor drive ic
Power digital circuit, it is intended to reduce stand-by power consumption.
In order to reach above-mentioned purpose of utility model, technical solution is as follows used by solving its technical problem：
A kind of super-low standby power consumption circuit for motor drive ic, including logic control element, high-end power stage list
Member, low side power stage unit, high-side driver grade unit, low side driving stage unit, resistance R1, resistance R2, PMOS power tube P1 and
NMOS power tube N1, wherein：
The logic control element generates P_CTRL and N_ according to IN1 the and IN2 signals of input after logical process
CTRL signal；
The high-end power stage unit generates supply voltage VIN-VDD according to IN1 the and IN2 signals of input, for institute
State the power supply of high-side driver grade unit；
The low side power stage unit generates supply voltage VDD according to IN1 the and IN2 signals of input, for described low
Hold driving stage unit and logic control element power supply；
The high-side driver grade unit is according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV that becomes larger
Signal；
The low side driving stage unit is according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV that becomes larger
Signal；
Described resistance R1 one end connects with the output terminal of the high-side driver grade unit and the grid of the PMOS power tubes P1
It connects, the other end and the high-side driver grade unit and the input terminal of high-end power stage unit and the source of the PMOS power tubes P1
Pole connects；
Described resistance R2 one end connects with the output terminal of the low side driving stage unit and the grid of the NMOS power tubes N1
It connects, the other end connect with the source electrode of the NMOS power tubes N1 and is grounded simultaneously；
The drain electrode of the PMOS power tubes P1 is connect with the drain electrode of the NMOS power tubes N1.
Further, the low side power stage unit include NMOS tube N2, NMOS tube N3, NMOS pipe N4, PMOS tube P2,
PMOS tube P3, resistance R3, resistance R4 and voltage-stabiliser tube Z1, wherein：
The grid connection IN1 signals of the NMOS tube N2, drain electrode connect one end of the resistance R3, source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N3, drain electrode connect one end of the resistance R3, source electrode ground connection；
The grid of the PMOS tube P2 connects the grid of the PMOS tube P3, and source electrode connects the PMOS tube P3's respectively
The drain electrode of source electrode and the NMOS tube N4, drain electrode connect the other end of the resistance R3；
The other end of the resistance R3 is also connected to the grid of the PMOS tube P2 and the grid of the PMOS tube P3 simultaneously
Pole；
The drain electrode of the PMOS tube P3 connects the cathode of the voltage-stabiliser tube Z1, one end of the resistance R4 and institute respectively
State the grid of NMOS tube N4；
The plus earth of the voltage-stabiliser tube Z1；
The other end ground connection of the resistance R4；
The source electrode connection supply voltage VDD of the NMOS tube N4.
Further, the low side driving stage unit includes several phase inverters, several described phase inverters are sequentially connected in series
Connection, the input terminal input N_CTRL signals of first phase inverter, the recommending output mode N_DRV signals after several phase inverters.
Further, the high-end power stage unit includes NMOS tube N5, NMOS tube N6, PMOS pipe P4, resistance R5, electricity
R6, resistance R7 and voltage-stabiliser tube Z2 are hindered, wherein：
The grid connection IN1 signals of the NMOS tube N5, drain electrode connect one end of the resistance R5, source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N6, drain electrode connect one end of the resistance R5, source electrode ground connection；
The one end of the cathode of the voltage-stabiliser tube Z2 respectively with the resistance R6 and resistance R7 is connect；
The other end of the resistance R5 respectively with the other end of the resistance R6, the anode of the voltage-stabiliser tube Z2 and described
The grid connection of PMOS tube P4；
The source electrode of the PMOS tube P4 connects the other end of the resistance R7, grounded drain.
Further, the high-side driver grade unit includes several phase inverters, several described phase inverters are sequentially connected in series
Connection, the input terminal input P_CTRL signals of first phase inverter, the recommending output mode P_DRV signals after several phase inverters.
The utility model due to using the technology described above, is allowed to compared with prior art, have the following advantages that and accumulate
Pole effect：
In a kind of super-low standby power consumption circuit for motor drive ic of the utility model, as input signal IN1 and
When IN2 is low, low side power stage unit and high-end power stage unit do not generate VDD and VIN-VDD electricity all in off state
Pressure, so high-side driver grade unit and low side driving stage unit are also in off state, at this point, PMOS power tubes P1 and NMOS
Power tube N1 is pulled up and is pulled down by resistance R1 and R2 respectively, is also in off state.And logic control element is not because have yet
VDD powers, and is also at off state.Because whole system circuit does not consume any static state all in off state, entire circuit
Electric current, therefore can realize ultra low quiescent power consumption.
Description of the drawings
It is required in being described below to embodiment in order to illustrate more clearly of the technical solution of the utility model embodiment
The attached drawing used is briefly described.It is clear that the accompanying drawings in the following description is only some embodiments of the utility model,
For those skilled in the art, without creative efforts, other be can also be obtained according to these attached drawings
Attached drawing.In attached drawing：
Fig. 1 is a kind of integrated circuit signal of super-low standby power consumption circuit for motor drive ic of the utility model
Figure；
Fig. 2 is a kind of super-low standby power consumption circuit low and middle-end power stage unit for motor drive ic of the utility model
Circuit diagram；
Fig. 3 is a kind of super-low standby power consumption circuit low and middle-end driving stage unit for motor drive ic of the utility model
Circuit diagram；
Fig. 4 is a kind of super-low standby power consumption circuit middle and high end power stage unit for motor drive ic of the utility model
Circuit diagram；
Fig. 5 is a kind of super-low standby power consumption circuit middle and high end driving stage unit for motor drive ic of the utility model
Circuit diagram.
Specific embodiment
Below with reference to the attached drawing of the utility model, the technical scheme in the embodiment of the utility model is carried out clear, complete
Whole description and discussion, it is clear that as described herein is only a part of example of the utility model, is not whole realities
Example, based on the embodiment in the utility model, those of ordinary skill in the art institute under the premise of creative work is not made
The every other embodiment obtained, belongs to the scope of protection of the utility model.
As shown in Figure 1, present embodiment discloses a kind of super-low standby power consumption circuit for motor drive ic, including patrolling
Collect control unit, high-end power stage unit, low side power stage unit, high-side driver grade unit, low side driving stage unit, resistance
R1, resistance R2, PMOS power tube P1 and NMOS power tube N1, wherein：
The logic control element generates P_CTRL and N_ according to IN1 the and IN2 signals of input after logical process
CTRL signal；When P_CTRL is high, PMOS power tubes P1 is driven to open by high-side driver grade unit.When N_CTRL is height
When, NMOS power tubes N1 is driven to open by low side driving stage unit.
The high-end power stage unit generates supply voltage VIN-VDD according to IN1 the and IN2 signals of input, for institute
State the power supply of high-side driver grade unit；
The low side power stage unit generates supply voltage VDD according to IN1 the and IN2 signals of input, for described low
Hold driving stage unit and logic control element power supply；
The high-side driver grade unit is according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV that becomes larger
Signal；
The low side driving stage unit is according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV that becomes larger
Signal；
Described resistance R1 one end connects with the output terminal of the high-side driver grade unit and the grid of the PMOS power tubes P1
It connects, the other end and the high-side driver grade unit and the input terminal of high-end power stage unit and the source of the PMOS power tubes P1
Pole connects, for when the power supply of the difference of high-side driver grade unit is zero, the grid of pull-up PMOS power tubes P1 to ensure to VIN
PMOS power tubes P1 is turned off.
Described resistance R2 one end connects with the output terminal of the low side driving stage unit and the grid of the NMOS power tubes N1
It connects, the other end connect with the source electrode of the NMOS power tubes N1 and is grounded simultaneously, in the power vd D of low side driving stage unit
When being zero, the grid of pull-down NMOS power tube N1 ensures NMOS power tubes N1 shutdowns to ground.
The drain electrode of the PMOS power tubes P1 is connect with the drain electrode of the NMOS power tubes N1.
In Fig. 1, IN1 and IN2 are input control signals, and specific logic is shown in Table 1：
| IN1 | IN2 | PMOS | NMOS |
| 0 | 0 | OFF | OFF |
| 0 | 1 | OFF | ON |
| 1 | 0 | ON | OFF |
| 1 | 1 | OFF | OFF |
Table 1
When IN1 is low, IN2 is low, PMOS power tube P1 and NMOS power tubes N1 is turned off.When IN1 for it is low,
When IN2 is high, PMOS power tubes P1 shutdowns, NMOS power tubes N1 is opened.When IN1 is high, IN2 is low, PMOS
Power tube P1 is opened, NMOS power tubes N1 shutdowns.When IN1 is high, IN2 is high, PMOS power tubes P1 shutdowns, NMOS
Power tube N1 is also switched off that (logical interlock, preventing PMOS power tube P1 and NMOS power tubes N1 from opening simultaneously leads to short circuit, so together
When be turned off, the input logic of IN1 and IN2 will not occur simultaneously for height under normal circumstances).Due to logic control element and have
VDD powers, and when IN1 or IN2 is high, vdd voltage is normal, logic control element normal work.When IN1 and IN2 are low
When, it is zero that VDD, which is turned off, so logic control element does not consume any quiescent current.
As shown in Fig. 2, the low side power stage unit include NMOS tube N2, NMOS tube N3, NMOS pipe N4, PMOS tube P2,
PMOS tube P3, resistance R3, resistance R4 and voltage-stabiliser tube Z1, wherein：
The grid connection IN1 signals of the NMOS tube N2, drain electrode connect one end of the resistance R3, source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N3, drain electrode connect one end of the resistance R3, source electrode ground connection；
The grid of the PMOS tube P2 connects the grid of the PMOS tube P3, and source electrode connects the PMOS tube P3's respectively
The drain electrode of source electrode and the NMOS tube N4, drain electrode connect the other end of the resistance R3；
The other end of the resistance R3 is also connected to the grid of the PMOS tube P2 and the grid of the PMOS tube P3 simultaneously
Pole；
The drain electrode of the PMOS tube P3 connects the cathode of the voltage-stabiliser tube Z1, one end of the resistance R4 and institute respectively
State the grid of NMOS tube N4；
The plus earth of the voltage-stabiliser tube Z1；
The other end ground connection of the resistance R4；
The source electrode connection supply voltage VDD of the NMOS tube N4.
Specifically, in low side power stage element circuit figure, when IN1 and IN2 is low, NMOS pipes N2 and
NMOS tube N3 is all in off state, therefore no electric current flows through PMOS tube P2 and PMOS tube P3, meanwhile, there is no electric current stream yet
Voltage-stabiliser tube Z1 is crossed, the grid voltage G1 of NMOS tube N4 moves zero to by resistance R4, so the source voltage VDD of NMOS tube N4 is also
Zero.At this point, low side power stage unit does not consume any quiescent current.When any one IN1 or IN2 are increased, NMOS pipes N2 or
NMOS tube N3 is in opening state, has electric current to flow through PMOS tube P2 and PMOS tube P3, so there is electric current to flow through voltage-stabiliser tube Z1 and electricity
Hinder R4.For example the voltage of voltage regulation of 6V is generated in G1 points, at this moment NMOS tube N4 is opened, and generates a vdd voltage, this voltage value
Equal to 6V-VGS=5V, when voltage of voltage regulation G1 is equal to 6V, when the circuit of the gate source voltage VGS=1V, Fig. 2 of NMOS tube N4 are exactly reality
Show and VDD is turned off when IN1 and IN2 is zero and does not consume quiescent dissipation, and when IN1 or IN2 is high, it is low
Power stage unit normal work is held, generates a vdd voltage.
As shown in figure 3, the low side driving stage unit includes several phase inverters, several described phase inverters are sequentially connected in series
Connection, the input terminal input N_CTRL signals of first phase inverter, the recommending output mode N_DRV signals after several phase inverters.Tool
Body, the low side driving stage unit recommends realization by the phase inverter that several become larger, and input signal is believed for N_CTRL
Number, output signal is N_DRV signals.When N_DRV signals export a height of VDD, NMOS power tubes N1 is opened.When N_DRV signals
Export it is low for ground when, turn off NMOS power tubes N1.The circuit is simple and reliable, and when vdd voltage is zero, low side driving stage unit is not
Consume any quiescent current.
As shown in figure 4, the high-end power stage unit includes NMOS tube N5, NMOS tube N6, PMOS pipe P4, resistance R5, electricity
R6, resistance R7 and voltage-stabiliser tube Z2 are hindered, wherein：
The grid connection IN1 signals of the NMOS tube N5, drain electrode connect one end of the resistance R5, source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N6, drain electrode connect one end of the resistance R5, source electrode ground connection；
The one end of the cathode of the voltage-stabiliser tube Z2 respectively with the resistance R6 and resistance R7 is connect；
The other end of the resistance R5 respectively with the other end of the resistance R6, the anode of the voltage-stabiliser tube Z2 and described
The grid connection of PMOS tube P4；
The source electrode of the PMOS tube P4 connects the other end of the resistance R7, grounded drain.
Specifically, in high-end power stage element circuit figure, when IN1 and IN2 is low, NMOS pipes N5 and
NMOS tube N6 is turned off, and no electric current flows through voltage-stabiliser tube Z2 and resistance R6, and the grid G 2 of PMOS tube P4 moves VIN to by resistance R6,
The source voltage of PMOS tube P4 also moves VIN to by resistance R7.When IN1 or IN2 voltages are high, NMOS tube N5 or NMOS tube N6 quilts
It opens, there is electric current to flow through voltage-stabiliser tube Z2 and resistance R6, a voltage-stabiliser tube lower than VIN is generated in the grid G 2 of PMOS tube P4
Voltage, such as 6V.So voltage of one higher than the G2 voltage PMOS tube P4 gate source voltages of source electrode generation in PMOS tube P4
VIN-VDD.This voltage value be equal to VIN-6V+VGS=VIN-5V, when voltage of voltage regulation G2 be equal to VIN-6V, when PMOS tube P4's
When gate source voltage VGS=1V, the circuit of Fig. 4 be exactly realize when IN1 and IN2 is zero turn off VIN-VDD and
Quiescent dissipation is not consumed, and when IN1 or IN2 is high, high-end power stage unit normal work, and generate a VIN-
Vdd voltage.
As shown in figure 5, the high-side driver grade unit includes several phase inverters, several described phase inverters are sequentially connected in series
Connection, the input terminal input P_CTRL signals of first phase inverter, the recommending output mode P_DRV signals after several phase inverters.Tool
Body, the high-side driver grade unit recommends realization by the phase inverter that several become larger, and input signal is believed for P_CTRL
Number, output signal is P_DRV signals.When it is VIN-VDD that the output of P_DRV signals is low, PMOS power tubes P1 is opened.Work as P_DRV
When signal exports a height of VIN, PMOS power tubes P1 is turned off.The circuit is simple and reliable, high-end when VIN-VDD voltages are VIN
Driving stage unit does not consume any quiescent current.
In the present embodiment, when input signal IN1 and IN2 are low, low side power stage unit and high-end power stage unit
All in off state, VDD and VIN-VDD voltages are not generated, so high-side driver grade unit and low side driving stage unit are also all
State is off, at this point, PMOS power tube P1 and NMOS power tubes N1 is pulled up and pulled down by resistance R1 and R2 respectively, also all
It is off state.And logic control element is also at off state also because powering without VDD.Because whole system circuit
All in off state, entire circuit does not consume any quiescent current, therefore can realize ultra low quiescent power consumption.
The preferable specific embodiment of the above, only the utility model, but the scope of protection of the utility model is not
This is confined to, in the technical scope that any one skilled in the art discloses in the utility model, can be readily occurred in
Change or replacement, should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model should
It is subject to the protection scope in claims.
Claims (5)
1. a kind of super-low standby power consumption circuit for motor drive ic, which is characterized in that including logic control element, high-end
Power stage unit, low side power stage unit, high-side driver grade unit, low side driving stage unit, resistance R1, resistance R2, PMOS work(
Rate pipe P1 and NMOS power tube N1, wherein：
The logic control element generates P_CTRL and N_CTRL according to IN1 the and IN2 signals of input after logical process to be believed
Number；
The high-end power stage unit generates supply voltage VIN-VDD according to IN1 the and IN2 signals of input, for the height
Hold the power supply of driving stage unit；
The low side power stage unit generates supply voltage VDD according to IN1 the and IN2 signals of input, for being driven to the low side
Dynamic grade unit and logic control element power supply；
The high-side driver grade unit is believed according to the P_CTRL signals of input by the phase inverter recommending output mode P_DRV become larger
Number；
The low side driving stage unit is believed according to the N_CTRL signals of input by the phase inverter recommending output mode N_DRV become larger
Number；
Described resistance R1 one end is connect with the output terminal of the high-side driver grade unit and the grid of the PMOS power tubes P1, separately
One end and the source electrode of the input terminal and the PMOS power tubes P1 of the high-side driver grade unit and high-end power stage unit connect
It connects；
Described resistance R2 one end is connect with the output terminal of the low side driving stage unit and the grid of the NMOS power tubes N1, separately
One end connect with the source electrode of the NMOS power tubes N1 and is grounded simultaneously；
The drain electrode of the PMOS power tubes P1 is connect with the drain electrode of the NMOS power tubes N1.
A kind of 2. super-low standby power consumption circuit for motor drive ic according to claim 1, which is characterized in that institute
It states low side power stage unit and includes NMOS tube N2, NMOS tube N3, NMOS tube N4, PMOS tube P2, PMOS tube P3, resistance R3, resistance
R4 and voltage-stabiliser tube Z1, wherein：
The grid connection IN1 signals of the NMOS tube N2, drain electrode connect one end of the resistance R3, source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N3, drain electrode connect one end of the resistance R3, source electrode ground connection；
The grid of the PMOS tube P2 connects the grid of the PMOS tube P3, and source electrode connects the source electrode of the PMOS tube P3 respectively
With the drain electrode of the NMOS tube N4, drain electrode connects the other end of the resistance R3；
The other end of the resistance R3 is also connected to the grid of the PMOS tube P2 and the grid of the PMOS tube P3 simultaneously；
The drain electrode of the PMOS tube P3 connects the cathode of the voltage-stabiliser tube Z1, one end of the resistance R4 and the NMOS respectively
The grid of pipe N4；
The plus earth of the voltage-stabiliser tube Z1；
The other end ground connection of the resistance R4；
The source electrode connection supply voltage VDD of the NMOS tube N4.
A kind of 3. super-low standby power consumption circuit for motor drive ic according to claim 1, which is characterized in that institute
It states low side driving stage unit and includes several phase inverters, several described phase inverters are sequentially connected in series, first phase inverter
Input terminal inputs N_CTRL signals, the recommending output mode N_DRV signals after several phase inverters.
A kind of 4. super-low standby power consumption circuit for motor drive ic according to claim 1, which is characterized in that institute
It states high-end power stage unit and includes NMOS tube N5, NMOS tube N6, PMOS tube P4, resistance R5, resistance R6, resistance R7 and voltage-stabiliser tube
Z2, wherein：
The grid connection IN1 signals of the NMOS tube N5, drain electrode connect one end of the resistance R5, source electrode ground connection；
The grid connection IN2 signals of the NMOS tube N6, drain electrode connect one end of the resistance R5, source electrode ground connection；
The one end of the cathode of the voltage-stabiliser tube Z2 respectively with the resistance R6 and resistance R7 is connect；
The other end of the resistance R5 respectively with the other end of the resistance R6, the anode of the voltage-stabiliser tube Z2 and the PMOS
The grid connection of pipe P4；
The source electrode of the PMOS tube P4 connects the other end of the resistance R7, grounded drain.
A kind of 5. super-low standby power consumption circuit for motor drive ic according to claim 1, which is characterized in that institute
It states high-side driver grade unit and includes several phase inverters, several described phase inverters are sequentially connected in series, first phase inverter
Input terminal inputs P_CTRL signals, the recommending output mode P_DRV signals after several phase inverters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721858092.2U CN207603436U (en) | 2017-12-26 | 2017-12-26 | A kind of super-low standby power consumption circuit for motor drive ic |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721858092.2U CN207603436U (en) | 2017-12-26 | 2017-12-26 | A kind of super-low standby power consumption circuit for motor drive ic |
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| Publication Number | Publication Date |
|---|---|
| CN207603436U true CN207603436U (en) | 2018-07-10 |
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ID=62769162
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108023464A (en) * | 2017-12-26 | 2018-05-11 | 上海数明半导体有限公司 | A kind of super-low standby power consumption circuit for motor drive ic |
-
2017
- 2017-12-26 CN CN201721858092.2U patent/CN207603436U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108023464A (en) * | 2017-12-26 | 2018-05-11 | 上海数明半导体有限公司 | A kind of super-low standby power consumption circuit for motor drive ic |
| CN108023464B (en) * | 2017-12-26 | 2023-12-19 | 上海数明半导体有限公司 | Ultralow standby power consumption circuit for motor driving chip |
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