CN214101345U

CN214101345U - Level conversion structure supporting wide level range high-speed data

Info

Publication number: CN214101345U
Application number: CN202023047929.XU
Authority: CN
Inventors: 万璐绪; 贺凌炜; 高国平
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2020-12-17
Filing date: 2020-12-17
Publication date: 2021-08-31
Anticipated expiration: 2030-12-17

Abstract

The utility model discloses a support level conversion structure of wide level range high rate data belongs to integrated circuit IO port design field. The input end of the inverter INV1 is connected with an input pressure welding point IN, and the output end is connected with the grid end of an NMOS tube N1; the drain end of the NMOS tube N1 is respectively connected with the drain end of the PMOS tube P1 and the gate end of the PMOS tube P2; the drain end of the PMOS tube P2 is connected with the source end of the PMOS tube P3; the grid end of the PMOS pipe P3 and the grid end of the NMOS pipe N2 are both connected with an input pressure welding point IN, and the drain end of the PMOS pipe P3 and the drain end of the NMOS pipe N2 are both connected with an output pressure welding point OUT. The utility model discloses a level conversion structure supports 500 Mbps's level conversion the highest, reduces the competition of level conversion output level PMOS pipe and NMOS pipe when the drop-down, has improved the speed of drop-down in the level conversion process effectively, has solved the unable compatible problem of ordinary level conversion circuit high speed data and wide level range; the structure has the advantages of simple device, higher device reliability and wide application range, and is suitable for the chip design of multiple voltage domains.

Description

Level conversion structure supporting wide level range high-speed data

Technical Field

The utility model relates to an integrated circuit IO port design technical field, in particular to support level transition structure of wide level range high rate data.

Background

With the rapid development of modern integrated circuit technology, more and more electronic products enter our lives. In modern integrated circuit design, a multi-voltage domain design method is often adopted to meet the requirement of signal level conversion between different voltage domains; therefore, it is necessary to insert a level shift unit between the two sets of voltage domain systems. The requirements of different logic units on the level range and the data rate of level conversion are different, a common high-speed level conversion structure can only meet a smaller level range, and wide-range level conversion can only have better performance at a lower speed.

In view of the above technical problem that a wide level range and an invalid data rate cannot be achieved in the level conversion process, no effective solution has been proposed at present.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a support level transition structure of wide level range high rate data to solve ordinary level transition circuit high rate data and the unable compatible problem of wide level range.

IN order to solve the technical problem, the utility model provides a support level conversion structure of wide level range high rate data, including NMOS pipe N1 and N2, PMOS pipe P1~ P3, phase inverter INV1, input pressure welding point IN and output pressure welding point OUT;

the input end of the inverter INV1 is connected with an input pressure welding point IN, and the output end is connected with the grid end of an NMOS tube N1; the drain end of the NMOS tube N1 is respectively connected with the drain end of the PMOS tube P1 and the gate end of the PMOS tube P2; the drain end of the PMOS tube P2 is connected with the source end of the PMOS tube P3;

the grid end of the PMOS pipe P3 and the grid end of the NMOS pipe N2 are both connected with an input pressure welding point IN, and the drain end of the PMOS pipe P3 and the drain end of the NMOS pipe N2 are both connected with an output pressure welding point OUT.

Optionally, the substrate and the source terminal of the NMOS transistor N1, and the substrate and the source terminal of the NMOS transistor N2 are both connected to the lowest potential GND; the source terminal and the substrate of the PMOS transistor P1, the source terminal and the substrate of the PMOS transistor P2, and the substrate of the PMOS transistor P3 are all connected to the output power supply VCCOUT.

Optionally, the gate terminal of the PMOS transistor P1 is connected to the output pad OUT.

Optionally, the highest level of the inverter INV1 is the input power VCCIN.

The utility model provides an among the level transition structure of support wide level range high rate data, including NMOS pipe N1 and N2, PMOS pipe P1~ P3, inverter INV1, input pressure welding point IN and output pressure welding point OUT; the input end of the inverter INV1 is connected with an input pressure welding point IN, and the output end is connected with the grid end of an NMOS tube N1; the drain end of the NMOS tube N1 is respectively connected with the drain end of the PMOS tube P1 and the gate end of the PMOS tube P2; the drain end of the PMOS tube P2 is connected with the source end of the PMOS tube P3; the grid end of the PMOS pipe P3 and the grid end of the NMOS pipe N2 are both connected with an input pressure welding point IN, and the drain end of the PMOS pipe P3 and the drain end of the NMOS pipe N2 are both connected with an output pressure welding point OUT. The utility model discloses a level conversion structure supports 500 Mbps's level conversion the highest, reduces the competition of level conversion output level PMOS pipe and NMOS pipe when the drop-down, has improved the speed of drop-down in the level conversion process effectively, has solved the unable compatible problem of ordinary level conversion circuit high speed data and wide level range; the structure has the advantages of simple device, higher device reliability and wide application range, and is suitable for the chip design of multiple voltage domains.

Drawings

Fig. 1 is a schematic diagram of a level shift structure supporting high-rate data in a wide level range according to the present invention.

Detailed Description

The following describes a level shift structure supporting high-rate data in a wide level range in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

The utility model provides a support level transition structure of wide level range high rate data, its structure is as shown IN FIG. 1, including NMOS pipe N1 and N2, PMOS pipe P1~ P3, phase inverter INV1, input pressure welding point IN (be input signal) and output pressure welding point OUT (be output signal).

The input end of the inverter INV1 is connected with an input pressure welding point IN, and the output end is connected with the grid end of an NMOS tube N1; the drain end of the NMOS tube N1 is respectively connected with the drain end of the PMOS tube P1 and the gate end of the PMOS tube P2; the drain end of the PMOS tube P2 is connected with the source end of the PMOS tube P3; the grid end of the PMOS pipe P3 and the grid end of the NMOS pipe N2 are both connected with an input pressure welding point IN, and the drain end of the PMOS pipe P3 and the drain end of the NMOS pipe N2 are both connected with an output pressure welding point OUT. The substrate and the source end of the NMOS transistor N1 and the substrate and the source end of the NMOS transistor N2 are both connected with the lowest potential GND; the source terminal and the substrate of the PMOS transistor P1, the source terminal and the substrate of the PMOS transistor P2, and the substrate of the PMOS transistor P3 are all connected to the output power supply VCCOUT. The grid end of the PMOS pipe P1 is connected with an output pressure welding point OUT. The highest level of the inverter INV1 is the input power VCCIN.

The utility model discloses a working process and theory of operation: when the input signal of the level conversion unit is high (VCCIN), the PMOS transistor P3 is in a closed or half-open state, the NMOS transistor N2 is used as a medium-threshold NMOS transistor to be opened, and in competition with the PMOS transistor P3, the output signal is pulled down to be low due to large driving capacity; when the input signal is low, the NMOS transistor N1 is turned on as a medium-threshold NMOS transistor, the N2 is turned off, and the PMOS transistor P3 is turned on, because the output signal OUT in the previous state is low, the positive feedback signal is connected to the PMOS transistor P1 at this time, in the competition between the PMOS transistor P1 and the NMOS transistor N1, because the NMOS transistor N1 employs a medium-threshold transistor with a smaller turn-on voltage, the gate terminal of the PMOS transistor P2 can be successfully pulled down to the ground in the competition, the PMOS transistor P2 is turned on, and the PMOS transistor P2 is turned on to pull up the output signal to VCCOUT through the PMOS transistor P3.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims

1. A level conversion structure supporting high-speed data IN a wide level range is characterized by comprising NMOS transistors N1 and N2, PMOS transistors P1-P3, an inverter INV1, an input pressure welding point IN and an output pressure welding point OUT;

2. The level shift structure supporting high rate data of a wide range of levels as claimed in claim 1, wherein the substrate and source terminals of NMOS transistor N1, and the substrate and source terminals of NMOS transistor N2 are all connected to the lowest potential GND; the source terminal and the substrate of the PMOS transistor P1, the source terminal and the substrate of the PMOS transistor P2, and the substrate of the PMOS transistor P3 are all connected to the output power supply VCCOUT.

3. The structure of claim 1, wherein the gate terminal of the PMOS transistor P1 is connected to the output pad OUT.

4. The level shift structure supporting a wide level range high rate data according to claim 1, wherein the highest level of the inverter INV1 is an input power source VCCIN.