CN117424325A - Power supply control circuit for MIPI transceiver circuit and MIPI transceiver circuit - Google Patents

Power supply control circuit for MIPI transceiver circuit and MIPI transceiver circuit Download PDF

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Publication number
CN117424325A
CN117424325A CN202210808258.9A CN202210808258A CN117424325A CN 117424325 A CN117424325 A CN 117424325A CN 202210808258 A CN202210808258 A CN 202210808258A CN 117424325 A CN117424325 A CN 117424325A
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CN
China
Prior art keywords
mipi
unit
electrically connected
mos tube
transceiver circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210808258.9A
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Chinese (zh)
Inventor
刘刚
丁佳佳
江海波
郭天生
赵鹏
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Jiangsu Qianhe Microelectronics Co ltd
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Jiangsu Qianhe Microelectronics Co ltd
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Filing date
Publication date
Application filed by Jiangsu Qianhe Microelectronics Co ltd filed Critical Jiangsu Qianhe Microelectronics Co ltd
Priority to CN202210808258.9A priority Critical patent/CN117424325A/en
Publication of CN117424325A publication Critical patent/CN117424325A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H02M1/0035—Control circuits allowing low power mode operation, e.g. in standby mode using burst mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transceivers (AREA)

Abstract

The invention relates to the technical field of MIPI interfaces, and discloses a power supply control circuit for an MIPI transceiver circuit and the MIPI transceiver circuit, comprising a first switch unit, a second switch unit and a switching unit; the input end of the first switch unit is electrically connected with the input end of the second switch unit, and the output end of the first switch unit is electrically connected with the output end of the second switch unit; the switching unit drives the first switching unit to be turned off when the MIPI transceiver circuit is in a low-power mode, and sends a conduction control signal to the control end of the first switching unit to drive the first switching unit to be conducted when the MIPI transceiver circuit is in a working state.

Description

Power supply control circuit for MIPI transceiver circuit and MIPI transceiver circuit
Technical Field
The invention relates to the technical field of MIPI interfaces, in particular to a power supply control circuit for an MIPI transceiver circuit and the MIPI transceiver circuit.
Background
In addition to the use of radio frequency transceivers in modern mobile communication devices, radio frequency front end devices such as power amplifiers, low noise amplifiers, filters, switches, power management modules, and antenna tuners are also widely used. Most of these rf front-end devices are controlled and mode configured by the master via a digital bus.
The radio frequency front end control interface (MIPI) established by the processor interface alliance in the mobile industry at present is a simple interface for a radio frequency system, and can be integrated by a small number of logic devices so as to reduce the investment of cost. The MIPI interface includes three signal lines, respectively a clock signal line SCLK, a data signal line SDATA, and a power supply line VIO. The interface can realize high-speed data transmission, is simple and easy to use, and is widely applied to radio frequency front-end devices in the mobile industry at present.
The conventional transceiver circuit based on the MIPI interface belongs to a typical digital circuit, and the structural schematic diagram of the typical transceiver circuit is shown in fig. 1, and when the transceiver circuit is in a low power consumption mode in actual use, the digital circuit and the functional circuit in fig. 1 still input a power supply VIO, and the voltage of the power supply VIO is 1.8V, which causes static leakage power consumption. With the strengthening and perfecting of MIPI interface function, the larger the area occupation ratio of the digital circuit is, the more serious the static leakage power consumption problem is in the low power consumption mode, and when the functional circuit is completely closed, the leakage current of the digital circuit can reach more than 60 uA. The existing static leakage reduction method adopts hvt devices in a gate level circuit, but the delay of hvt devices is relatively large, as shown in the figure, path delay needs to be reduced, circuit area needs to be increased, or if a power gating technology is adopted to enable a transceiver circuit to be powered down in a low-power consumption mode, however, the configuration of an MIPI interface bus needs to be carried out again when power is on, so that resource waste is caused.
Disclosure of Invention
In view of the shortcomings of the background art, the invention provides a power control circuit, a method and a MIPI transceiver circuit for the MIPI transceiver circuit, so as to reduce static leakage power consumption of the MIPI transceiver circuit.
To solve the above technical problems, in a first aspect, the present invention provides a power control circuit for an MIPI transceiver circuit, including a first switching unit, a second switching unit with voltage drop, and a switching unit; the input end of the first switch unit is electrically connected with the input end of the second switch unit, and the output end of the first switch unit is electrically connected with the output end of the second switch unit; the switching unit sends a turn-off control signal to the control end of the first switching unit to drive the first switching unit to turn off when the MIPI transceiver circuit is in a low power consumption mode, and sends a turn-on control signal to the control end of the first switching unit to drive the first switching unit to turn on when the MIPI transceiver circuit is in a working state.
In a certain implementation manner of the first aspect, the switching unit includes a trigger unit, a D flip-flop, and a level conversion unit, where an input end of the trigger unit is electrically connected to a SDATA end of the MIPI interface, an output end of the trigger unit is electrically connected to a clock end and a reset end of the D flip-flop, and a pulse signal is sent to the clock end and the reset end of the D flip-flop when a signal at the SDATA end of the MIPI interface undergoes level conversion; the output end of the D trigger is electrically connected with the level conversion unit, the level conversion unit sends a turn-off control signal to the control end of the first switch unit to control the first switch unit to turn off when the output end of the D trigger outputs a high-level signal, and the level conversion unit inputs a turn-on control signal to the control end of the first switch unit to control the first switch unit to turn on when the output end of the D trigger outputs a low-level signal.
In a certain implementation manner of the first aspect, the trigger unit includes an input end, a delay unit and a nand gate, the input end is electrically connected with the input end of the delay unit and the first input end of the nand gate, the output end of the delay unit is electrically connected with the second input end of the nand gate, and the output end of the nand gate is electrically connected with the reset end and the clock end of the D trigger.
In a certain implementation manner of the first aspect, the delay unit includes a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MP3, a MOS transistor MN1, a MOS transistor MN2, a MOS transistor MN3, and a capacitor C1; the source electrode of the MOS tube MP1 is electrically connected with the source electrode of the MOS tube MP2 and the source electrode of the MOS tube MP3, the grid electrode of the MOS tube MP1 is electrically connected with the grid electrode of the MOS tube MN1 and the input end respectively, the drain electrode of the MOS tube MP1 is electrically connected with the drain electrode of the MOS tube MN1, one end of the capacitor C1, the grid electrode of the MOS tube MP2 and the grid electrode of the MOS tube MN2 respectively, the drain electrode of the MOS tube MP2 is electrically connected with the drain electrode of the MOS tube MN2, the grid electrode of the MOS tube MP3 and the grid electrode of the MOS tube MN3 respectively, the drain electrode of the MOS tube MP3 is electrically connected with the drain electrode of the MOS tube MN3 and the second input end of the NAND gate, and the source electrode of the MOS tube MN2, the other end of the capacitor C1 and the source electrode of the MOS tube MN1 are all grounded.
In a certain implementation manner of the first aspect, the first switch unit includes a MOS transistor MP4, the second switch unit includes a MOS transistor MN4, a source of the MOS transistor MP4 is electrically connected to a drain of the MOS transistor MN4 and a gate of the MOS transistor MN4, and a drain of the MOS transistor MP4 is electrically connected to a source of the MOS transistor MN 4.
In a second aspect, the present invention provides an MIPI transceiver circuit comprising a power control circuit as described above for an MIPI transceiver circuit.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, through detecting the working state of the MIPI transceiver circuit, when the MIPI transceiver circuit is in a low-power-consumption mode, an external power supply is input to a digital circuit part of the MIPI transceiver circuit through the second switch unit with voltage drop, so that the power supply voltage of the digital circuit input to the MIPI transceiver circuit is reduced, and the use power consumption is reduced; when the MIPI transceiver circuit enters the working mode from the low-power consumption mode, the first switch unit is conducted, and an external power supply is input into the digital circuit through the first switch unit, so that the normal operation of the MIPI circuit is ensured.
Drawings
Fig. 1 is a schematic diagram of a conventional MIPI transceiver circuit;
FIG. 2 is a schematic diagram of the structure of the present invention;
FIG. 3 is a schematic diagram of a switching unit according to the present invention;
FIG. 4 is a circuit diagram of a trigger unit of the present invention;
fig. 5 is a timing diagram of the use of the conventional MIPI protocol.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
As shown in fig. 1, the conventional MIPI transceiver circuit includes a MIPI interface circuit for receiving and transmitting data, a digital circuit for decoding the number received from the MIPI interface circuit, and a functional circuit for controlling the operation of the following functional circuits. Wherein the digital circuit includes an internal register and an output pin, writing data to the REG1C register of the digital circuit can set an operation mode of the MIPI transceiver circuit according to MIPI protocol, when the MIPI transceiver circuit is in a low power consumption mode, the eighth bit of the REG1C register is written with data "1", and there is a pin representing a state of the eighth bit of the REG1C register in the output pin of the digital circuit, when the pin outputs a high level, the eighth bit of the REG1C register is written with data "1", and when the pin outputs a low level, the eighth bit of the REG1C register is written with data "0".
As shown in fig. 2, the power control circuit for the MIPI transceiver circuit includes a first switching unit 1, a second switching unit 2 with a voltage drop, and a switching unit 3; the input end of the first switch unit 1 is electrically connected with the input end of the second switch unit 2, and the output end of the first switch unit 1 is electrically connected with the output end of the second switch unit 2; the switching unit 3 sends a turn-off control signal to the control end of the first switching unit 1 to drive the first switching unit 1 to turn off when the MIPI transceiver circuit is in a low power consumption mode, and the switching unit 3 sends a turn-on control signal to the control end of the first switching unit 1 to drive the first switching unit 1 to turn on when the MIPI transceiver circuit is in a working state.
Specifically, the first switch unit 1 includes a MOS transistor MP4, the second switch unit 2 includes a MOS transistor MN4, a source electrode of the MOS transistor MP4 is electrically connected to a drain electrode of the MOS transistor MN4 and a gate electrode of the MOS transistor MN4, and a drain electrode of the MOS transistor MP4 is electrically connected to a source electrode of the MOS transistor MN 4. Wherein the voltage drop of the second switching unit 2 is 0.4V.
IN actual use, the connection terminal IN is electrically connected with the power supply VIO, the voltage of the power supply VIO is 1.8V, and the output terminal OUT is electrically connected with the power supply terminal of the digital circuit. The invention enables the digital circuit to input 1.4V voltage in a low power consumption mode by controlling the power supply access mode of the digital circuit in fig. 1, can reduce the static leakage current of the digital circuit when in work, and can reduce the leakage current to 3uA after practical test.
Specifically, as shown in fig. 3, in this embodiment, the switching unit 3 includes a trigger unit 30, a D flip-flop 31, and a level conversion unit 32, where an input end of the trigger unit 30 is electrically connected to the SDATA end of the MIPI interface, an output end of the trigger unit 30 is electrically connected to a reset end of the D flip-flop 31, an output end of the trigger unit 30 is electrically connected to a clock end of the D flip-flop 31 through a rising edge delay unit 34, and a pulse signal is sent to the clock end and a reset end of the D flip-flop 31 when a signal at the SDATA end of the MIPI interface undergoes level conversion; the output end of the D flip-flop 31 is electrically connected to the level shift unit 32, and the level shift unit 32 sends an off control signal to the control end of the first switch unit 1 to control the first switch unit 1 to be turned off when the output end of the D flip-flop 31 outputs a high level signal, and the level shift unit 32 inputs an on control signal to the control end of the first switch unit 1 to control the first switch unit 1 to be turned on when the output end of the D flip-flop outputs a low level signal.
As described in the second section of the content, according to the rule of the MIPI interface protocol, when the MIPI transceiver circuit is in the low power consumption mode and the operation mode, the eighth bit of the REG1C register, that is, the data of REG1C <7>, is "0" and "1", so that the on/off of the first switch unit 1 can be controlled according to the data of REG1C <7 >. In addition, as shown in fig. 5, when the MIPI protocol is in use, its output transmission is divided into an SSC phase, a Slave address phase and a Data phase, each phase having a corresponding high-low level signal change;
when the initial state mode is powered on, the SDATA end of the MIPI interface is always in a low level state, and at the moment, the data of REG1C <7> is "1";
when the MIPI transceiver circuit enters the working mode from the low power consumption mode, the data of REG1C <7> is "0", and when the data interaction is performed through the MIPI interface, the level state of the SDATA end of the MIPI interface will first change to the high level in the SSC stage, at this time, the trigger unit 30 will send a pulse signal to the D trigger 31, the pulse signal makes the output of the D trigger 31 change from the high level to the low level, and the level change unit 32 drives the first switch unit 1 to be turned on when receiving the low level signal, so that the voltage input by the digital circuit is 1.8V;
when the MIPI transceiver circuit enters a low power consumption mode from an operation mode, data '1' is written into REG1C <7 >; according to fig. 5, after the DATA phase of the MIPI protocol is completed, there is a rising edge pulse signal, which resets the output of the D flip-flop 31, and since REG1C <7> is written with DATA "1", the D flip-flop 31 outputs a high level signal after receiving the rising edge pulse signal, and the level converting unit 32 sends an off control signal to the control terminal of the first switching unit 1 to control the first switching unit 1 to be turned off when the output terminal of the D flip-flop 31 outputs the high level signal, so that an external power is input to the digital circuit through the second switching unit 2.
Specifically, as shown in fig. 4, the trigger unit 30 includes an input terminal SDATA, a delay unit 300, and a NAND gate NAND, where the input terminal SDATA is electrically connected to the input terminal of the delay unit 300 and a first input terminal of the NAND gate NAND, respectively, and an output terminal of the delay unit 300 is electrically connected to a second input terminal of the NAND gate NAND, and an output terminal of the NAND gate NAND is electrically connected to a reset terminal and a clock terminal of the D flip-flop 31, respectively.
The delay unit comprises an MOS tube MP1, an MOS tube MP2, an MOS tube MP3, an MOS tube MN1, an MOS tube MN2, an MOS tube MN3 and a capacitor C1; the source electrode of the MOS tube MP1 is electrically connected with the source electrode of the MOS tube MP2 and the source electrode of the MOS tube MP3, the grid electrode of the MOS tube MP1 is electrically connected with the grid electrode of the MOS tube MN1 and the input end respectively, the drain electrode of the MOS tube MP1 is electrically connected with the drain electrode of the MOS tube MN1, one end of the capacitor C1, the grid electrode of the MOS tube MP2 and the grid electrode of the MOS tube MN2 respectively, the drain electrode of the MOS tube MP2 is electrically connected with the drain electrode of the MOS tube MN2, the grid electrode of the MOS tube MP3 and the grid electrode of the MOS tube MN3 respectively, the drain electrode of the MOS tube MP3 is electrically connected with the drain electrode of the MOS tube MN3 and the second input end of the NAND gate, and the source electrode of the MOS tube MN2, the other end of the capacitor C1 and the source electrode of the MOS tube MN1 are all grounded.
In addition, the invention also provides an MIPI transceiver circuit, which comprises the power supply control circuit for the MIPI transceiver circuit.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.

Claims (6)

1. The power supply control circuit for the MIPI transceiver circuit is characterized by comprising a first switch unit, a second switch unit with voltage drop and a switching unit; the input end of the first switch unit is electrically connected with the input end of the second switch unit, and the output end of the first switch unit is electrically connected with the output end of the second switch unit; the switching unit sends a turn-off control signal to the control end of the first switching unit to drive the first switching unit to turn off when the MIPI transceiver circuit is in a low power consumption mode, and sends a turn-on control signal to the control end of the first switching unit to drive the first switching unit to turn on when the MIPI transceiver circuit is in a working state.
2. The power control circuit for the MIPI transceiver circuit according to claim 1, wherein the switching unit comprises a trigger unit, a D flip-flop, and a level conversion unit, wherein an input terminal of the trigger unit is electrically connected to the SDATA terminal of the MIPI interface, an output terminal of the trigger unit is electrically connected to the reset terminal of the D flip-flop, an output terminal of the trigger unit is electrically connected to the clock terminal of the D flip-flop through a rising edge delay unit, and a pulse signal is transmitted to the clock terminal and the reset terminal of the D flip-flop when a signal at the SDATA terminal of the MIPI interface undergoes level conversion; the output end of the D trigger is electrically connected with the level conversion unit, the level conversion unit sends a turn-off control signal to the control end of the first switch unit to control the first switch unit to turn off when the output end of the D trigger outputs a high-level signal, and the level conversion unit inputs a turn-on control signal to the control end of the first switch unit to control the first switch unit to turn on when the output end of the D trigger outputs a low-level signal.
3. The power control circuit for a MIPI transceiver circuit according to claim 2, wherein the trigger unit comprises an input terminal, a delay unit and a nand gate, the input terminal being electrically connected to the input terminal of the delay unit and the first input terminal of the nand gate, respectively, to the reset terminal and the clock terminal of the D flip-flop, respectively.
4. The power control circuit for MIPI transceiver circuit according to claim 3, wherein delay element comprises MOS transistor MP1, MOS transistor MP2, MOS transistor MP3, MOS transistor MN1, MOS transistor MN2, MOS transistor MN3 and capacitor C1; the source electrode of the MOS tube MP1 is electrically connected with the source electrode of the MOS tube MP2 and the source electrode of the MOS tube MP3, the grid electrode of the MOS tube MP1 is electrically connected with the grid electrode of the MOS tube MN1 and the input end respectively, the drain electrode of the MOS tube MP1 is electrically connected with the drain electrode of the MOS tube MN1, one end of the capacitor C1, the grid electrode of the MOS tube MP2 and the grid electrode of the MOS tube MN2 respectively, the drain electrode of the MOS tube MP2 is electrically connected with the drain electrode of the MOS tube MN2, the grid electrode of the MOS tube MP3 and the grid electrode of the MOS tube MN3 respectively, the drain electrode of the MOS tube MP3 is electrically connected with the drain electrode of the MOS tube MN3 and the second input end of the NAND gate, and the source electrode of the MOS tube MN2, the other end of the capacitor C1 and the source electrode of the MOS tube MN1 are all grounded.
5. The power control circuit for the MIPI transceiver circuit of claim 1, wherein the first switching unit comprises a MOS transistor MP4, the second switching unit comprises a MOS transistor MN4, the source of the MOS transistor MP4 is electrically connected to the drain of the MOS transistor MN4 and the gate of the MOS transistor MN4, respectively, and the drain of the MOS transistor MP4 is electrically connected to the source of the MOS transistor MN 4.
MIPI transceiver circuit comprising a power control circuit for MIPI transceiver circuit as claimed in any one of claims 1-5.
CN202210808258.9A 2022-07-11 2022-07-11 Power supply control circuit for MIPI transceiver circuit and MIPI transceiver circuit Pending CN117424325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210808258.9A CN117424325A (en) 2022-07-11 2022-07-11 Power supply control circuit for MIPI transceiver circuit and MIPI transceiver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210808258.9A CN117424325A (en) 2022-07-11 2022-07-11 Power supply control circuit for MIPI transceiver circuit and MIPI transceiver circuit

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Publication Number Publication Date
CN117424325A true CN117424325A (en) 2024-01-19

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CN202210808258.9A Pending CN117424325A (en) 2022-07-11 2022-07-11 Power supply control circuit for MIPI transceiver circuit and MIPI transceiver circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117707028A (en) * 2024-02-06 2024-03-15 芯睿微电子(昆山)有限公司 Radio frequency mode control circuit, radio frequency control chip and radio frequency chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117707028A (en) * 2024-02-06 2024-03-15 芯睿微电子(昆山)有限公司 Radio frequency mode control circuit, radio frequency control chip and radio frequency chip

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