CN106788493A - A kind of low speed transmitter circuit - Google Patents
A kind of low speed transmitter circuit Download PDFInfo
- Publication number
- CN106788493A CN106788493A CN201611191596.3A CN201611191596A CN106788493A CN 106788493 A CN106788493 A CN 106788493A CN 201611191596 A CN201611191596 A CN 201611191596A CN 106788493 A CN106788493 A CN 106788493A
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- nmos pass
- grid
- pass transistor
- pmos transistor
- low speed
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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Abstract
The invention provides a kind of low speed transmitter circuit.The low speed transmitter circuit includes input, first order driver element, second level driver element and output end, wherein, the first order driver element is connected to the input, and it includes the first reverser and the second reverser；The second level driver element is connected to the output end, and it includes the first PMOS transistor and the first nmos pass transistor, wherein the grid of first PMOS transistor and first nmos pass transistor is controlled by first reverser and the second reverser respectively.
Description
【Technical field】
The present invention relates to electronic interface systems technical field, especially, it is related to a kind of high-performance low speed transmitter circuit.
【Background technology】
In electronic interface systems, conventional low speed transmitter circuit is mainly and is made up of even level reverser, and drives
Ability increases step by step.Such as, the low speed transmitter circuit shown in Fig. 1 includes first order reverser and second level reverser, wherein
First order reverser includes the first PMOS transistor PM1 and the first nmos pass transistor NM1, and second level reverser includes the 2nd PMOS
Transistor PM2 and the second nmos pass transistor NM1；After the signal that input D_IN is received is by first order reverser, by
Two grades of reversers remove driving load electric capacity Cload.
Mobile Industry Processor Interface (Mobile Industry Processor Interface abbreviation MIPI) agreement
Rise time tr, fall time tf and voltage conversion efficiency of the low power emitter specification for transmitter circuit
There is specific requirement etc. parameter.According to the structure of the low speed transmitter circuit shown in Fig. 1, if up time tr and fall time
Tf meets above-mentioned specification, then require the second PMOS transistor PM2 and the second nmos pass transistor NM2 of the second level reverser
Size can not be too small, however, when the transistor size of the second level reverser is larger, the electricity of the low speed transmitter circuit
Pressure conversion efficiencyIt is difficult to meet the requirement of above-mentioned specification again., whereas if the size of the second level reverser
Turn down to meet voltage conversion efficiencyParameter request when, the rise time tr of the low speed transmitter circuit and
Fall time tf is difficult to meet the requirement of above-mentioned specification again.In other words, the rise time of the low speed transmitter circuit shown in Fig. 1
Tr and fall time tf and voltage conversion efficiencyThere is contradiction.
And, the low speed transmitter circuit shown in Fig. 1 there is also an issue, the output end of the low speed transmitter circuit
D_OUT cannot export high-impedance state, be unsatisfactory for the requirement of practical application.Also a kind of scheme is added in low speed transmitter circuit
Miller capacitance solves rise time tr and fall time tf and voltage conversion efficiencyContradictory problems, but its
Still the demand of circuit output high-impedance state cannot be solved, and can causes the output of low speed transmitter circuit due to introducing miller capacitance
Hold the output signal of D_OUT to there is very big burr, influence the reliability of circuit.
In view of this, it is necessary to which a kind of high-performance low speed transmitter circuit is provided, with solve prior art presence it is above-mentioned
Problem.
【The content of the invention】
It is an object of the invention to provide a kind of high-performance low speed transmitter circuit that can be solved the above problems.
Present invention firstly provides a kind of low speed transmitter circuit, including input, first order driver element, second level driving
Unit and output end, wherein, the first order driver element is connected to the input, and it includes the first reverser and second
Reverser；The second level driver element is connected to the output end, and it includes that the first PMOS transistor and a NMOS are brilliant
Body pipe, wherein the grid of first PMOS transistor and first nmos pass transistor respectively by first reverser and
Second reverser is controlled.
A kind of as the low speed transmitter circuit provided in the present invention improves, and in an advantageous embodiment, also includes
Electric capacity switch unit, the electric capacity switch unit includes the first switching switch, the second switching switch and miller capacitance；Wherein, institute
State the first switching switch and the described second switching switch is serially connected, and be connected to the output end of first reverser and described
Between the output end of the second reverser；One end of the miller capacitance is connected to the first switching switch and the described second switching
Between switch, and its other end is connected to the output end.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, described the
The on off state of one switching switch and the described second switching switch can be controlled by the input signal of the input, and the two phase
Off status is opposite.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, the rice
Electric capacity is strangled for slowing down the voltage conversion efficiency of the grid of first PMOS transistor and first nmos pass transistor.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, described the
The source electrode of one PMOS transistor is connected to DC voltage, and its drain electrode is connected to the drain electrode of first nmos pass transistor, and
It is connected further to the output end；The source electrode of first nmos pass transistor is connected to earth terminal.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, described the
The grid of one PMOS transistor is also connected to the DC voltage by the first pull-up control element, and a NMOS crystal
The grid of pipe is connected to the earth terminal by the first drop-down control element.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, described the
One reverser includes the second PMOS transistor and the second nmos pass transistor；The grid of second PMOS transistor and described second
The grid of nmos pass transistor is connected with each other, and is connected to the input, the drain electrode of second PMOS transistor and described the
The drain electrode of bi-NMOS transistor is connected with each other, and is connected to the grid of first PMOS transistor；The 2nd PMOS crystal
The source electrode of pipe is connected to DC voltage, and the source electrode of second nmos pass transistor is connected to by the second drop-down control element and connect
Ground terminal.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, described the
Two reversers include the 3rd PMOS transistor and the 3rd nmos pass transistor；The grid and the described 3rd of the 3rd PMOS transistor
The grid of nmos pass transistor is connected with each other, and is connected to the input；The drain electrode of the 3rd PMOS transistor and described
The drain electrode of three nmos pass transistors is connected with each other, and is connected to the grid of first nmos pass transistor；The 3rd PMOS crystal
The source electrode of pipe is also connected to the DC voltage by the second pull-up control element, and the source electrode of second nmos pass transistor connects
It is connected to the earth terminal.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, described the
One pull-up control element is the 4th PMOS transistor, and the first drop-down control element is the 4th nmos pass transistor；Described
The grid of four PMOS transistors is used to receive the first enable signal, and its source electrode is connected to the DC voltage, and its drain electrode connects
It is connected to the grid of first PMOS transistor；The grid of the 4th nmos pass transistor is used to receive the second enable signal, and
Its source electrode is connected to the earth terminal, and its drain electrode is connected to the grid of first nmos pass transistor；Described first enables letter
Number and described second enable signal be mutually opposing enable control signal.
A kind of as the low speed transmitter circuit provided in the present invention improves, in an advantageous embodiment, described the
Two pull-up control elements and the second drop-down control element are respectively the 5th PMOS transistor and the 5th nmos pass transistor；It is described
The grid of the 5th nmos pass transistor is used to receive the first enable signal, and its drain electrode is connected to the source of second nmos pass transistor
Pole, and its source electrode is connected to the earth terminal；The grid of the 5th PMOS transistor is used to receive the second enable signal, and its
Drain electrode is connected to the source electrode of the 3rd PMOS transistor, and its source electrode is connected to the DC voltage；Described first enables letter
Number and described second enable signal be mutually opposing enable control signal.
In the low speed transmitter circuit that the present invention is provided, the PMOS transistor and NMOS of the second level driver element are brilliant
Body pipe by two separate reversers of first order driver element and is controlled respectively, thus can dividually enter
Row is pulled up and drop-down, so that low speed transmitter circuit output high-impedance state is possibly realized；In addition, the low speed transmitter
Circuit also realizes the voltage conversion efficiency when load capacitance is 0pF by the miller capacitanceMeet and require；
Also, the low speed transmitter circuit can also be by using suitable miller capacitance and suitably increasing the first switching switch
With the resistance of the described second switching switch, the output burr that RC retardation ratio reduces the output end to optimize is introduced.
【Brief description of the drawings】
Technical scheme in order to illustrate more clearly the embodiments of the present invention, embodiment will be described below used in
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, can also obtain other attached according to these accompanying drawings
Figure, wherein：
Fig. 1 is a kind of electrical block diagram of traditional low speed transmitter circuit；
A kind of electrical block diagram of embodiment of low speed transmitter circuit that Fig. 2 is provided for the present invention.
【Specific embodiment】
The technical scheme in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
All other embodiment that technical staff is obtained under the premise of creative work is not made, belongs to the model of present invention protection
Enclose.
Fig. 2 is referred to, a kind of its electrical block diagram of embodiment of low speed transmitter circuit provided for the present invention.Institute
Stating low speed transmitter circuit 200 mainly includes input D_IN, first order driver element 210, second level driver element 220, electricity
Hold switch unit 230 and output end D_OUT.
Wherein, the first order driver element 210 is connected to the input D_IN, and it includes the first reverser 211
With the second reverser 212.The second level driver element 220 can be as output driving unit, and it is connected to the output end
D_OUT, and it includes the first PMOS transistor 221 and the first nmos pass transistor 222.The grid of first PMOS transistor 221
Pole is connected to the output end of first reverser 211, and it is anti-that the grid of first nmos pass transistor 222 is connected to described second
To the output end of device 212.In other words, in the present embodiment, the He of PMOS transistor 221 of the second level driver element 220
Nmos pass transistor 222 is to be controlled by two separate reversers 211 and 212 of first order driver element 210 respectively
System, thus can dividually carry out pulling up and drop-down, so that the low speed transmitter circuit 200 output high-impedance state turns into
May.
Specifically, the source electrode of first PMOS transistor 221 is connected to DC voltage VDD, and its drain electrode is connected to institute
The drain electrode of the first nmos pass transistor 222 is stated, the source electrode of first nmos pass transistor 222 is connected to earth terminal VSS.Also, institute
The drain electrode for stating the first nmos pass transistor 222 is further also connected to the output end D_OUT of the low speed transmitter circuit 200, and
The output end D_OUT can be used to connect load capacitance Cload.
In the present embodiment, the grid of first PMOS transistor 221 is also connected by the first pull-up control element 223
To the DC voltage VDD, and the grid of first nmos pass transistor 222 is connected to by the first drop-down control element 224
The earth terminal VSS.
First reverser 211 includes the second PMOS transistor 213 and the second nmos pass transistor 214.Wherein, described
The grid of the grid of two PMOS transistors 213 and second nmos pass transistor 214 is connected with each other, and reverse as described first
The input of device 211 and it is connected to the input D_IN of the low speed transmitter circuit 200.Second PMOS transistor 213
Drain electrode and the drain electrode of second nmos pass transistor 214 be connected with each other, and output end as first reverser 211 and
It is connected further to the grid of first PMOS transistor 221.In addition, the source electrode connection of second PMOS transistor 213
To the DC voltage VDD, and the source electrode of second nmos pass transistor 214 is connected to by the second drop-down control element 218
Earth terminal VSS.
Second reverser 212 includes the 3rd PMOS transistor 215 and the 3rd nmos pass transistor 216.Wherein, described
The grid of the grid of three PMOS transistors 215 and the 3rd nmos pass transistor 216 is connected with each other, and reverse as described second
The input of device 212 and it is connected to the input D_IN of the low speed transmitter circuit 200.3rd PMOS transistor 215
Drain electrode and the drain electrode of the 3rd nmos pass transistor 216 be connected with each other, and output end as second reverser 212 and
It is connected further to the grid of first nmos pass transistor 222.In addition, the source electrode of the 3rd PMOS transistor 215 also leads to
Cross the second pull-up control element 217 and be connected to the DC voltage VDD, and the source electrode of second nmos pass transistor 214 is connected
To earth terminal VSS.
In a particular embodiment, the first pull-up control element 223 and the second pull-up control element 217 can be equal
It is PMOS transistor, and the first drop-down control element 224 and the second pull-up control element 218 can be NMOS crystalline substances
Body pipe.
Such as, in the embodiment shown in Figure 2, the first pull-up control element 223 can be the 4th PMOS transistor,
And the first drop-down control element 224 can be the 4th nmos pass transistor.Wherein, the grid of the 4th PMOS transistor 223
Pole is used to receive the first enable signal EN, and its source electrode is connected to the DC voltage VDD, and its drain electrode is connected to described first
The grid of PMOS transistor 221.The grid of the 4th nmos pass transistor 224 is used to receive the second enable signal ENb, and its source
Pole is connected to the earth terminal VSS, and its drain electrode is connected to the grid of first nmos pass transistor 222.In specific embodiment
In, it can be mutually opposing enable control signal that the first enable signal EN and described second enables signal ENb.
Analogously, the second pull-up control element 217 and the second drop-down control element 218 can be respectively the
Five PMOS transistors and the 5th nmos pass transistor.Wherein, the grid of the 5th PMOS transistor 217 is used to receive described second
Signal ENb is enabled, and its drain electrode is connected to the source electrode of the 3rd PMOS transistor 215, and its source electrode is connected to the direct current
Voltage VDD.The grid of the 5th nmos pass transistor 218 is used to receive the first enable signal EN, and its drain electrode is connected to
The source electrode of second nmos pass transistor 214, and its source electrode is connected to the earth terminal VSS.
When the low speed transmitter circuit 200 does not make, to allow that the output end D_OUT exports high-impedance state, institute
State the first enable signal EN and it is described second enable signal ENb can be respectively set to high level and low level, i.e. EN=L and
ENb=H；Now, the described second drop-down control element 218 is turned off, and the second pull-up control element 217 is turned off, and described the
One pull-up control element 223 and the second drop-down control element 224 are closed, now the first pull-up control element 223
First PMOS transistor 221 can be pulled up, and the first drop-down control element 224 can be brilliant with a drop-down NMOS
Body pipe 222, in this case, the output of the output end D_OUT is changed into high-impedance state.
The electric capacity switch unit 230 includes the first switching switch the 231, second switching switch 232 and miller capacitance 233.
Wherein, the first switching switch 231 and the second switching switch 232 are serially connected, and are connected to first reverser
Between the output end of 211 output end and second reverser 212.One end of the miller capacitance 233 is connected to described
Between one switching switch 231 and the second switching switch 232, and its other end is connected to the low speed transmitter circuit 200
Output end D_OUT.
In the present embodiment, the on off state of the first switching switch 231 and the second switching switch 232 can be received
The input signal control of the input D_IN, and the two correlation behavior is opposite.Such as, when the input of the input D_IN is believed
During number high level, the closure of the first switching switch 231 and the second switching switch 232 disconnects, the now miller capacitance
233 output ends (being attached to the grid of first PMOS transistor 221) for being connected to first reverser 211；And work as
During the input signal low level of the input D_IN, the first switching switch 231 disconnects and the second switching switch 232
Closure, now the miller capacitance 233 be connected to the output end of second reverser 212 and (be attached to a NMOS
The grid of transistor 222).The miller capacitance 233 is mainly used for slowing down first PMOS transistor 221 and described first
The voltage conversion efficiency (Slew Rate) of the grid of nmos pass transistor 222, so as to realize when the load capacitance Cload is 0pF
When, the voltage conversion efficiency of the low speed transmitter circuit 200 Meet and require.
Although it should be noted that use the larger miller capacitance 233 of capacitance for the load capacitance Cload for
0pF improves the voltage conversion efficiencyIt is helpful to, but when the capacitance of the miller capacitance 233 is too big
When, the burr for being coupled to the output end D_OUT by the miller capacitance 233 can also increase.So, on implementing,
To reduce influence of the burr to output signal, the capacitance of the miller capacitance CC can not be too big, furthermore it is also possible to pass through appropriate
Increase the resistance of the first switching switch 231 and the second switching switch 232, introduce resistance capacitance (RC) and postpone to optimize
Reduce the output burr of the output end D_OUT.
Above-described is only embodiments of the present invention, it should be noted here that for one of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to protection model of the invention
Enclose.
Claims (10)
1. a kind of low speed transmitter circuit, it is characterised in that including input, first order driver element, second level driver element
And output end, wherein, the first order driver element is connected to the input, and it includes the first reverser and second reverse
Device；The second level driver element is connected to the output end, and it includes the first PMOS transistor and the first nmos pass transistor,
The grid of wherein described first PMOS transistor and first nmos pass transistor passes through first reverser and second respectively
Reverser is controlled.
2. low speed transmitter circuit according to claim 1, it is characterised in that also including electric capacity switch unit, the electricity
Holding switch unit includes the first switching switch, the second switching switch and miller capacitance；Wherein, first switching is switched and described
Second switching switch is serially connected, and be connected to first reverser output end and second reverser output end it
Between；One end of the miller capacitance is connected between the first switching switch and the second switching switch, and its other end
It is connected to the output end.
3. low speed transmitter circuit according to claim 2, it is characterised in that the first switching switch and described second
Switching the on off state of switch controlled by the input signal of the input, and the two correlation behavior is opposite.
4. low speed transmitter circuit according to claim 3, it is characterised in that the miller capacitance is used to slowing down described the
The voltage conversion efficiency of the grid of one PMOS transistor and first nmos pass transistor.
5. low speed transmitter circuit according to claim 1, it is characterised in that the source electrode of first PMOS transistor connects
DC voltage is connected to, and its drain electrode is connected to the drain electrode of first nmos pass transistor, and it is connected further to the output
End；The source electrode of first nmos pass transistor is connected to earth terminal.
6. low speed transmitter circuit according to claim 5, it is characterised in that the grid of first PMOS transistor is also
The DC voltage is connected to by the first pull-up control element, and the grid of first nmos pass transistor is drop-down by first
Control element is connected to the earth terminal.
7. low speed transmitter circuit according to claim 1, it is characterised in that first reverser includes the 2nd PMOS
Transistor and the second nmos pass transistor；The grid of the grid of second PMOS transistor and second nmos pass transistor is mutual
Connection, and the input is connected to, the drain electrode phase drained with second nmos pass transistor of second PMOS transistor
Connect, and be connected to the grid of first PMOS transistor；The source electrode of second PMOS transistor is connected to direct current
Pressure, and the source electrode of second nmos pass transistor is connected to earth terminal by the second drop-down control element.
8. low speed transmitter circuit according to claim 7, it is characterised in that second reverser includes the 3rd PMOS
Transistor and the 3rd nmos pass transistor；The grid of the 3rd PMOS transistor and the grid of the 3rd nmos pass transistor are mutual
Connection, and it is connected to the input；The drain electrode of the 3rd PMOS transistor and the drain electrode phase of the 3rd nmos pass transistor
Connect, and be connected to the grid of first nmos pass transistor；The source electrode of the 3rd PMOS transistor also passes through on second
Control element is drawn to be connected to the DC voltage, and the source electrode of second nmos pass transistor is connected to the earth terminal.
9. low speed transmitter circuit according to claim 6, it is characterised in that the first pull-up control element is the 4th
PMOS transistor, and the first drop-down control element is the 4th nmos pass transistor；The grid of the 4th PMOS transistor is used
Signal is enabled in receiving first, and its source electrode is connected to the DC voltage, and its drain electrode is connected to a PMOS crystal
The grid of pipe；The grid of the 4th nmos pass transistor is used to receive the second enable signal, and its source electrode is connected to the ground connection
End, and its drain electrode is connected to the grid of first nmos pass transistor；Described first enables signal and described second enables signal
It is mutually opposing enable control signal.
10. low speed transmitter circuit according to claim 8, it is characterised in that the second pull-up control element and the institute
State the second drop-down control element and be respectively the 5th PMOS transistor and the 5th nmos pass transistor；The grid of the 5th nmos pass transistor
Pole is used to receive the first enable signal, and its drain electrode is connected to the source electrode of second nmos pass transistor, and its source electrode is connected to
The earth terminal；The grid of the 5th PMOS transistor is used to receiving second and enables signal, and its drain electrode is connected to described the
The source electrode of three PMOS transistors, and its source electrode is connected to the DC voltage；Described first enables signal and described second enables
Signal is mutually opposing enable control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611191596.3A CN106788493B (en) | 2016-12-21 | 2016-12-21 | Low-speed transmitter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611191596.3A CN106788493B (en) | 2016-12-21 | 2016-12-21 | Low-speed transmitter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106788493A true CN106788493A (en) | 2017-05-31 |
| CN106788493B CN106788493B (en) | 2019-12-10 |
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ID=58896833
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611191596.3A Active CN106788493B (en) | 2016-12-21 | 2016-12-21 | Low-speed transmitter circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134992A (en) * | 2017-06-29 | 2017-09-05 | 合肥灿芯科技有限公司 | Input and output drive circuit |
| CN113054990A (en) * | 2021-03-12 | 2021-06-29 | 湖南国科微电子股份有限公司 | Drive circuit, interface circuit and terminal |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088716A (en) * | 1994-06-20 | 1996-01-12 | Fujitsu Ltd | Gate circuit |
| JPH09326685A (en) * | 1996-06-05 | 1997-12-16 | Fujitsu Ltd | Semiconductor device |
| US20040135597A1 (en) * | 2001-07-16 | 2004-07-15 | Toshimichi Seike | Output buffer circuit |
| CN1215644C (en) * | 1997-11-19 | 2005-08-17 | 爱特梅尔股份有限公司 | Zero-delay slew-rate controlled output buffer |
| US20060017470A1 (en) * | 2004-07-21 | 2006-01-26 | Park Sung K | Low power high performance inverter circuit |
| CN101795132A (en) * | 2010-04-02 | 2010-08-04 | 日银Imp微电子有限公司 | Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit |
-
2016
- 2016-12-21 CN CN201611191596.3A patent/CN106788493B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088716A (en) * | 1994-06-20 | 1996-01-12 | Fujitsu Ltd | Gate circuit |
| JPH09326685A (en) * | 1996-06-05 | 1997-12-16 | Fujitsu Ltd | Semiconductor device |
| CN1215644C (en) * | 1997-11-19 | 2005-08-17 | 爱特梅尔股份有限公司 | Zero-delay slew-rate controlled output buffer |
| US20040135597A1 (en) * | 2001-07-16 | 2004-07-15 | Toshimichi Seike | Output buffer circuit |
| US20060017470A1 (en) * | 2004-07-21 | 2006-01-26 | Park Sung K | Low power high performance inverter circuit |
| CN101795132A (en) * | 2010-04-02 | 2010-08-04 | 日银Imp微电子有限公司 | Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134992A (en) * | 2017-06-29 | 2017-09-05 | 合肥灿芯科技有限公司 | Input and output drive circuit |
| CN113054990A (en) * | 2021-03-12 | 2021-06-29 | 湖南国科微电子股份有限公司 | Drive circuit, interface circuit and terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106788493B (en) | 2019-12-10 |
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Application publication date: 20170531 Assignee: Shandong industry research information and Artificial Intelligence Integration Research Institute Co.,Ltd. Assignor: HUNAN GOKE MICROELECTRONICS Co.,Ltd. Contract record no.: X2021430000001 Denomination of invention: A low speed transmitter circuit Granted publication date: 20191210 License type: Common License Record date: 20210115 |
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