CN113938126A - Voltage latching type level conversion circuit - Google Patents
Voltage latching type level conversion circuit Download PDFInfo
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- CN113938126A CN113938126A CN202111241106.7A CN202111241106A CN113938126A CN 113938126 A CN113938126 A CN 113938126A CN 202111241106 A CN202111241106 A CN 202111241106A CN 113938126 A CN113938126 A CN 113938126A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a voltage latching type level switching circuit, which belongs to the field of integrated circuits and comprises a phase inverter taking a power supply 1 as a voltage source, a level switching unit taking a power supply 2 as a voltage source and an output buffer taking the power supply 2 as a voltage source; the inverter provides a group of reverse signals for the level conversion unit; the level conversion unit receives an input reverse signal and realizes conversion of different voltage domains in a voltage latching mode, and the output buffer realizes shaping for an output signal and improves the driving capability of a lower stage. The invention is suitable for 1.8V-5V bidirectional level conversion under 1Gbps, and can control the voltage latch function of the level conversion circuit through the enable signal, and the transmission delay is less than 200 ps; compared with the conventional level conversion and latch which are connected in series, the invention has the advantages of smaller transmission delay, smaller dynamic power consumption, wider voltage domain range, higher transmission rate and less total amount of MOS (metal oxide semiconductor) transistors.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a voltage latching type level conversion circuit.
Background
The bus interface circuit has large demand and high universality, and no matter the bus interface circuit is a system on chip or a board level circuit, the functions of the circuit are indispensable in order to match the working conditions of the system under various conditions. The level shift circuit is an IO interface circuit with very common application, and generally exists in a system with multiple power supplies. In order to meet the power supply conditions of each functional module, the level conversion circuit can realize the conversion function of different voltage sources to match the power supply requirements of different modules under the condition that the drain electrode is small.
The traditional level conversion circuits are mainly classified into 2 types, one type is the level conversion circuit shown in fig. 1, the level conversion circuit is simple in structure, full-amplitude voltage is output, and the level conversion function is completed on the premise of small electric leakage by controlling the switching sequence of the NMOS transistors N12 and N13 and the PMOS transistors P12 and P13. But the limit frequency of the circuit can only reach about 400Mbps because the design of the structure determines that the edge of the voltage reversal can not be raised or lowered instantly, and the transmission delay of the circuit structure is higher than the sum of the delay of the 3-stage inverters. At present, under the condition that no special requirements and rate limits exist, the full-amplitude level conversion chip mostly adopts the level conversion circuit.
The second type is a level shift circuit of a current mirror load, and fig. 2 shows a level shift circuit of a wilson current mirror, which is characterized in that a differential comparator is implemented through the current mirror load to further implement a level shift function, and the level shift circuit has the disadvantages that the output cannot reach full amplitude, the input power voltage is limited by the working states of NMOS transistors N22 and N23, and when the frequency is high, the input power cannot be too small in order to ensure that the differential circuit works in a large signal mode.
Disclosure of Invention
The present invention is directed to a voltage latch type level shifter circuit to solve the problems of the prior art.
In order to solve the above technical problem, the present invention provides a voltage latch type level shift circuit, which includes an inverter, a level shift unit and an output buffer;
the inverter provides a group of reverse signals for the level conversion unit;
the level conversion unit receives an input reverse signal and realizes the conversion of different voltage domains in a voltage latching mode;
the output buffer shapes the output signal and improves the driving capability of the lower stage.
Optionally, the inverter includes a PMOS transistor P41 and an NMOS transistor N41; wherein the content of the first and second substances,
the grid end of the PMOS pipe P41 is connected with an input voltage welding point IN, the source end is connected with a power supply voltage VDDIN, and the substrate is connected with the power supply voltage VDDIN;
the grid end of the NMOS tube N41 is connected with an input pressure welding point IN, and the source end and the substrate are both connected with GND;
and the drain terminal of the PMOS tube P41 and the drain terminal of the NMOS tube N41 are interconnected to form the output terminal of the phase inverter.
Optionally, the level shift unit includes PMOS transistors P42, P43, P44, P45, P46, P47, P48, NMOS transistors N42, N43, N44, N45, N48; wherein the content of the first and second substances,
the grid end of the PMOS tube P42 is connected with the output end of the phase inverter, and is simultaneously connected with the grid end of the PMOS tube P46 and the grid end of the NMOS tube N42; the source end and the substrate of the PMOS tube P42 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P43 and P48;
the grid end of the PMOS tube P43 is connected with an input pressure welding point IN and is simultaneously connected with the grid ends of the PMOS tubes P45, P47 and an NMOS tube N43; the source end and the substrate of the PMOS tube P43 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P42 and P48;
the grid end of the PMOS pipe P44 is connected with the input end of the output buffer, and is simultaneously connected with the grid end of the NMOS pipe N44, the drain ends of N43 and N45 and the drain end of P47; the source end of a PMOS tube P44 is connected with the drain ends of P42, P43, P48 and the source end of P45, the drain end of a PMOS tube P44 is connected with the source end of P46, and the substrate is connected with VDDOUT;
the gate end of a PMOS tube P45 is connected with the gate end of an NMOS tube N45, the drain end of N42, the drain end of N44 and the drain end of P46, the source end of a PMOS tube P45 is connected with the drain end of P42, the drain end of P43, the drain end of P48 and the source end of P44, the drain end of the PMOS tube P45 is connected with the source end of P47, and the substrate is connected with VDDOUT;
the grid end of a PMOS tube P46 is connected with the output end of the phase inverter and is simultaneously connected with the grid ends of P42 and N42, the source end and the substrate of the PMOS tube P46 are both connected with the drain end of P44, and the drain end of a PMOS tube P46 is connected with the drain end of N42, the drain end of N44, the grid end of P45 and the grid end of N45;
the grid end of the PMOS tube P47 is connected with an input pressure welding point IN and is simultaneously connected with the grid end of P43 and the grid end of N43, and the drain end of the PMOS tube P47 and the substrate are both connected with the drain end of P45; the drain end of the PMOS pipe P47 is connected with the input end of the output buffer and is simultaneously connected with the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44;
the gate end of an NMOS tube N42 is connected with the output end of the input inverter, and is simultaneously connected with the gate end of P42 and the gate end of P46, the source end and the substrate are both connected with GND, the drain end of the NMOS tube N42 is connected with the drain end of N44, the drain end of P46, the gate end of P45 and the gate end of N45;
the gate end of an NMOS tube N43 is connected with an input pressure welding point IN and is also connected with the gate end of P43 and the gate end of P47, the source end and the substrate are both connected with GND, the drain end of the NMOS tube N43 is connected with the input end of an output buffer and is also connected with the drain end of N45, the drain end of P47, the gate end of P44 and the gate end of N44;
the gate end of an NMOS tube N44 is connected with the input end of an output buffer and is simultaneously connected with the drain end of N43, the drain end of N45, the drain end of P47 and the gate end of P4, the source end and the substrate are all connected with GND, and the drain end of an NMOS tube N44 is connected with the drain end of N42, the drain end of P46, the gate end of P45 and the gate end of N45;
the gate end of the NMOS tube N45 is connected with the drain end of N42, the drain end of N44, the drain end of P46 and the gate end of P45, and the source end and the substrate are connected with GND; the drain end of the NMOS tube N45 is connected with the input end of the output buffer and is simultaneously connected with the drain end of N43, the drain end of P47, the gate end of P44 and the gate end of N44;
the gate end of an NMOS tube N48 is connected with a pressure welding point EN and is simultaneously connected with the gate end of P48, the source end and the substrate are both connected with GND, and the drain end of an NMOS tube N48 is connected with the source end of N42 and the source end of N43; the grid end of the PMOS tube P48 is connected with a pressure welding point EN and is connected with the grid end of the N48, the source end and the substrate are connected with VDDOUT, and the drain end of the PMOS tube P48 is connected with the drain end of the P42, the drain end of the P43, the source end of the P44 and the source end of the P45.
Optionally, the output buffer includes a PMOS transistor P49 and an NMOS transistor N49; wherein the content of the first and second substances,
the gate end of the PMOS tube P49 is simultaneously connected with the drain end of P47, the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44; the source end of the PMOS tube P49 is connected with the substrate by the power supply voltage VDDOUT, the drain end is connected with the output pressure welding point OUT and is also connected with the drain end of the N49;
the gate end of the NMOS transistor N49 is simultaneously connected with the drain end of P47, the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44; the source end and the substrate of the NMOS tube N49 are connected with GND, the drain end is connected with an output pressure welding point OUT, and the drain end of the NMOS tube N49 is connected with the drain end of the PMOS tube P49.
The voltage latching type level switching circuit provided by the invention comprises an inverter taking a power supply 1 as a voltage source, a level switching unit taking a power supply 2 as a voltage source and an output buffer taking the power supply 2 as a voltage source; the inverter provides a group of reverse signals for the level conversion unit; the level conversion unit, the output buffer. The invention is suitable for 1.8V-5V bidirectional level conversion under 1Gbps, and can control the voltage latch function of the level conversion circuit through the enable signal, and the transmission delay is less than 200 ps; compared with the conventional level conversion and latch which are connected in series, the invention has the advantages of smaller transmission delay, smaller dynamic power consumption, wider voltage domain range, higher transmission rate and less total amount of MOS (metal oxide semiconductor) transistors.
Drawings
FIG. 1 is a schematic diagram of a conventional full-scale level shift circuit;
FIG. 2 is a schematic diagram of a current mirror based level shift circuit;
FIG. 3 is a schematic block diagram of a voltage latching level shifter circuit according to the present invention;
FIG. 4 is a schematic diagram of a voltage latch type level shifter circuit according to the present invention;
FIG. 5 is a schematic diagram of the input/output and transmission delay of the voltage latch type level shifter circuit provided by the present invention operating at 1 Gbps.
Detailed Description
The present invention provides a voltage latch type level shift circuit, which is described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a voltage latching type level switching circuit, the principle of which is shown in figure 3, comprising an inverter taking a power supply 1 as a voltage source, a level switching unit taking a power supply 2 as a voltage source and an output buffer taking the power supply 2 as a voltage source; the inverter provides a group of reverse signals for the level conversion unit; the level conversion unit receives an input reverse signal and realizes conversion of different voltage domains in a voltage latching mode, and the output buffer realizes shaping for an output signal and improves the driving capability of a lower stage.
Referring to fig. 4, the inverter includes a PMOS transistor P41 and an NMOS transistor N41; the grid end of the PMOS tube P41 is connected with an input voltage welding point IN, the source end is connected with a power supply voltage VDDIN, and the substrate is connected with the power supply voltage VDDIN; the grid end of the NMOS tube N41 is connected with an input pressure welding point IN, and the source end and the substrate are both connected with GND; and the drain terminal of the PMOS tube P41 and the drain terminal of the NMOS tube N41 are interconnected to form the output terminal of the phase inverter.
The level conversion unit comprises PMOS tubes P42, P43, P44, P45, P46, P47 and P48, NMOS tubes N42, N43, N44, N45 and N48; the NMOS tubes N42, N43, N44 and N45 are also medium-threshold tubes, and have smaller starting voltage and larger current driving capability; in the working state, the switching states of the NMOS transistors N2 and N3 are opposite in direction and same in time delay. The grid end of the PMOS tube P42 is connected with the output end of the phase inverter, and is simultaneously connected with the grid end of the PMOS tube P46 and the grid end of the NMOS tube N42; the source end and the substrate of the PMOS tube P42 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P43 and P48; the grid end of the PMOS tube P43 is connected with an input pressure welding point IN and is simultaneously connected with the grid ends of the PMOS tubes P45, P47 and an NMOS tube N43; the source end and the substrate of the PMOS tube P43 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P42 and P48; the grid end of the PMOS pipe P44 is connected with the input end of the output buffer, and is simultaneously connected with the grid end of the NMOS pipe N44, the drain ends of N43 and N45 and the drain end of P47; the source end of a PMOS tube P44 is connected with the drain ends of P42, P43, P48 and the source end of P45, the drain end of a PMOS tube P44 is connected with the source end of P46, and the substrate is connected with VDDOUT; the gate end of a PMOS tube P45 is connected with the gate end of an NMOS tube N45, the drain end of N42, the drain end of N44 and the drain end of P46, the source end of a PMOS tube P45 is connected with the drain end of P42, the drain end of P43, the drain end of P48 and the source end of P44, the drain end of the PMOS tube P45 is connected with the source end of P47, and the substrate is connected with VDDOUT; the grid end of a PMOS tube P46 is connected with the output end of the phase inverter and is simultaneously connected with the grid ends of P42 and N42, the source end and the substrate of the PMOS tube P46 are both connected with the drain end of P44, and the drain end of a PMOS tube P46 is connected with the drain end of N42, the drain end of N44, the grid end of P45 and the grid end of N45; the grid end of the PMOS tube P47 is connected with an input pressure welding point IN and is simultaneously connected with the grid end of P43 and the grid end of N43, and the drain end of the PMOS tube P47 and the substrate are both connected with the drain end of P45; the drain end of the PMOS pipe P47 is connected with the input end of the output buffer and is simultaneously connected with the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44; the gate end of an NMOS tube N42 is connected with the output end of the input inverter, and is simultaneously connected with the gate end of P42 and the gate end of P46, the source end and the substrate are both connected with GND, the drain end of the NMOS tube N42 is connected with the drain end of N44, the drain end of P46, the gate end of P45 and the gate end of N45; the gate end of an NMOS tube N43 is connected with an input pressure welding point IN and is also connected with the gate end of P43 and the gate end of P47, the source end and the substrate are both connected with GND, the drain end of the NMOS tube N43 is connected with the input end of an output buffer and is also connected with the drain end of N45, the drain end of P47, the gate end of P44 and the gate end of N44; the gate end of an NMOS tube N44 is connected with the input end of an output buffer and is simultaneously connected with the drain end of N43, the drain end of N45, the drain end of P47 and the gate end of P4, the source end and the substrate are all connected with GND, and the drain end of an NMOS tube N44 is connected with the drain end of N42, the drain end of P46, the gate end of P45 and the gate end of N45; the gate end of the NMOS tube N45 is connected with the drain end of N42, the drain end of N44, the drain end of P46 and the gate end of P45, and the source end and the substrate are connected with GND; the drain end of the NMOS tube N45 is connected with the input end of the output buffer and is simultaneously connected with the drain end of N43, the drain end of P47, the gate end of P44 and the gate end of N44; the gate end of an NMOS tube N48 is connected with a pressure welding point EN and is simultaneously connected with the gate end of P48, the source end and the substrate are both connected with GND, and the drain end of an NMOS tube N48 is connected with the source end of N42 and the source end of N43; the grid end of the PMOS tube P48 is connected with a pressure welding point EN and is connected with the grid end of the N48, the source end and the substrate are connected with VDDOUT, and the drain end of the PMOS tube P48 is connected with the drain end of the P42, the drain end of the P43, the source end of the P44 and the source end of the P45. The output buffer comprises a PMOS pipe P49 and an NMOS pipe N49; the grid end of the PMOS tube P49 is simultaneously connected with the drain end of P47, the drain end of N43, the drain end of N45, the grid end of P44 and the grid end of N44; the source end of the PMOS tube P49 is connected with the substrate by the power supply voltage VDDOUT, the drain end is connected with the output pressure welding point OUT and is also connected with the drain end of the N49; the gate end of the NMOS transistor N49 is simultaneously connected with the drain end of P47, the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44; the source end and the substrate of the NMOS tube N49 are connected with GND, the drain end is connected with an output pressure welding point OUT, and the drain end of the NMOS tube N49 is connected with the drain end of the PMOS tube P49.
The function of the level conversion unit is to realize the conversion from the power supply 1 to the power supply 2, and the level conversion normally works when the enable is turned on, and outputs the last state when the enable is turned off; the input and output truth table is as follows:
| EN | IN | OUT | status of |
| 0 | 0 | Indefinite article | Maintain the |
| 0 | 1 | Indefinite article | Maintain the last state |
| 1 | 0 | 0 | |
| 1 | 1 | 1 | Level shift output VDDOUT |
Level conversion function: when the input is high voltage, the input signal passes through the inverter of the first stage to output a low voltage to the PMOS transistors P42, P46 and the NMOS transistor N42, so that P42 and P46 are turned on, N42 is turned off, N43 is turned on, the gate terminal voltage of the PMOS transistor P49 in the output buffer is low, and the final output is high, i.e., VDDOUT is output. Meanwhile, the gate terminal of P44 is also in an on state because the last state is pulled down by N43 due to the conduction of P42 and P46, so that the gate terminal voltage of N45 is high, N45 is on, and the gate terminal of P44 is further pulled down, and in this state, the states of P43, N44, P45 and P47 are all determined to be in an off state. Similarly, when the input is low voltage, P42, N43, P44 and P46 are turned off, N42, P43, P45 and P47 are turned on, the gate terminal voltage of P49 in the output buffer is high, and the final output is low, that is, output GND.
The working principle of the synchronous switch is as follows: when the input voltage is inverted from high to low, the middle threshold tube N42 is turned on and turned off by N43, P42 and P46 are turned off simultaneously at the same moment, P43 and P47 are turned on simultaneously, and the on-off states of P44, N44, P45 and N45 are slower than those of P42, P46, P43 and P47, so that the existence of the synchronous switch P46 avoids the transient competition risk of P44 and N42, and the pull-down speed of the edge is increased. Similarly, the presence of the sync switch P47 avoids the short race hazard of P45 with N43 when the voltage is reversed from low to high. By the structure, the duration time of the edge is greatly reduced, the upper limit of the working frequency of the circuit is improved, and the transmission delay is reduced. The substrates of the synchronous switches P46 and P47 are connected with the source ends to reduce the substrate bias effect and improve the current driving capability.
The enable signal controls the latch function: when the enable signal is high, the enable switch tube P48 is cut off, the N48 is conducted, and the level conversion works normally; when enabled to low, the level shift unit has a latch function. If the enable signal is turned off when the input pad IN is high, the initial state of the circuit is P42, N43, P44, N45, P46 is turned on, N42, P43, N44, P5, P7 are turned off, the input of the output buffer is low, the output is high, when the input pad IN changes from high to low, N42, P43, P47 are turned on, P42, N43, P46 are turned off, the gate terminal voltages of P44, P45 are not leaked due to the turning off of N48, the circuit is IN an unstable state, the drain terminal of P46 keeps high potential under no leakage condition, nano-ampere leakage occurs to ground under actual condition, but the voltage loss caused by the leakage can be compensated by the fact that the gate terminal signals of P46, N42 are suddenly increased to couple the voltage generated at the drain terminal of P42, so as to ensure that the gate source voltage of vgn 42 is larger than the saturation voltage of vts 72, thereby driving the vts 72 is larger IN the saturation region (VTH) and the VOD 42 is also expected to be turned on when it is used, the drain of P47 is kept low, and P45 can prevent VCCOUT from going down when P43 and P47 are turned on, so that the output OUT port is still high and the level shifter keeps the output state before enabling to turn off. Similarly, when the input pad IN is low, the enable signal is turned off, the initial state of the circuit is N42, P43, N44, P45 and P47 is turned on, P42, N43, P44, N45 and P46 are turned off, the input of the output buffer is high, the output OUT port is low, when the input pad IN changes from low to high, P42, N43 and P46 are turned on, N42, P43 and P47 are turned off, the gate voltages of P44 and P45 are not discharged due to the turning off of N48, the path is IN an unsteady state, the drain of P47 keeps high potential under the condition of no leakage, actually, due to the influence of the last state, P45 is still opened, and P48 is IN a normally open state due to the pad EN, even if the P47 has leakage, since both ends of the source and the source are IN high potential, it can be determined that the input of the output buffer is high, the output level is still kept low, and the output buffer is still turned off, so that the output unit can be turned on the output source and the output level is switched off before the low.
The invention can realize the fixed output state under the condition of suspended input, and the circuit can not generate the unstable state after the input is disconnected or the input power supply voltage is powered down by switching off the enable; the average power supply leakage does not exceed 2mA at the limiting frequency, the static average leakage current does not exceed 10nA, and the dynamic power consumption is lower than 10mW at the limiting frequency; the power supply voltage can span 1.8V, 3.3V and 5V voltage domains, and 2 modes of high-pass low and low-pass high are supported; the input and the output can be regarded as full-swing power supply voltage; the limit frequency of the level shift unit is limited by the turn-on voltage of the middle threshold transistors N42, N43, N44 and N45. The larger the duty ratio of the edge time in the whole period, the worse the output duty ratio. The circuit can normally work under 1Gbps, the input/output and transmission delay conditions under 1Gbps are shown in fig. 5, the 1.8V wave form in the figure is an input wave form, the 5V wave form is an output wave form, the input wave form is given by excitation, the inflection point is sharp, and the transmission delay of 68.9P seconds marked in the figure can also be provided.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (4)
1. A voltage latching type level switching circuit is characterized by comprising an inverter, a level switching unit and an output buffer;
the inverter provides a group of reverse signals for the level conversion unit;
the level conversion unit receives an input reverse signal and realizes the conversion of different voltage domains in a voltage latching mode;
the output buffer realizes shaping for the output signal and improves the driving capability of the lower stage.
2. The voltage latched level shifter circuit of claim 1, wherein the inverter comprises a PMOS transistor P41 and an NMOS transistor N41; wherein the content of the first and second substances,
the grid end of the PMOS pipe P41 is connected with an input voltage welding point IN, the source end is connected with a power supply voltage VDDIN, and the substrate is connected with the power supply voltage VDDIN;
the grid end of the NMOS tube N41 is connected with an input pressure welding point IN, and the source end and the substrate are both connected with GND;
and the drain terminal of the PMOS tube P41 and the drain terminal of the NMOS tube N41 are interconnected to form the output terminal of the phase inverter.
3. The voltage latched level shifter circuit of claim 2, wherein the level shifter unit comprises PMOS transistors P42, P43, P44, P45, P46, P47, P48, NMOS transistors N42, N43, N44, N45, N48; wherein the content of the first and second substances,
the grid end of the PMOS tube P42 is connected with the output end of the phase inverter, and is simultaneously connected with the grid end of the PMOS tube P46 and the grid end of the NMOS tube N42; the source end and the substrate of the PMOS tube P42 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P43 and P48;
the grid end of the PMOS tube P43 is connected with an input pressure welding point IN and is simultaneously connected with the grid ends of the PMOS tubes P45, P47 and an NMOS tube N43; the source end and the substrate of the PMOS tube P43 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P42 and P48;
the grid end of the PMOS pipe P44 is connected with the input end of the output buffer, and is simultaneously connected with the grid end of the NMOS pipe N44, the drain ends of N43 and N45 and the drain end of P47; the source end of a PMOS tube P44 is connected with the drain ends of P42, P43, P48 and the source end of P45, the drain end of a PMOS tube P44 is connected with the source end of P46, and the substrate is connected with VDDOUT;
the gate end of a PMOS tube P45 is connected with the gate end of an NMOS tube N45, the drain end of N42, the drain end of N44 and the drain end of P46, the source end of a PMOS tube P45 is connected with the drain end of P42, the drain end of P43, the drain end of P48 and the source end of P44, the drain end of the PMOS tube P45 is connected with the source end of P47, and the substrate is connected with VDDOUT;
the grid end of a PMOS tube P46 is connected with the output end of the phase inverter and is simultaneously connected with the grid ends of P42 and N42, the source end and the substrate of the PMOS tube P46 are both connected with the drain end of P44, and the drain end of a PMOS tube P46 is connected with the drain end of N42, the drain end of N44, the grid end of P45 and the grid end of N45;
the grid end of the PMOS tube P47 is connected with an input pressure welding point IN and is simultaneously connected with the grid end of P43 and the grid end of N43, and the drain end of the PMOS tube P47 and the substrate are both connected with the drain end of P45; the drain end of the PMOS pipe P47 is connected with the input end of the output buffer and is simultaneously connected with the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44;
the gate end of an NMOS tube N42 is connected with the output end of the input inverter, and is simultaneously connected with the gate end of P42 and the gate end of P46, the source end and the substrate are both connected with GND, the drain end of the NMOS tube N42 is connected with the drain end of N44, the drain end of P46, the gate end of P45 and the gate end of N45;
the gate end of an NMOS tube N43 is connected with an input pressure welding point IN and is also connected with the gate end of P43 and the gate end of P47, the source end and the substrate are both connected with GND, the drain end of the NMOS tube N43 is connected with the input end of an output buffer and is also connected with the drain end of N45, the drain end of P47, the gate end of P44 and the gate end of N44;
the gate end of an NMOS tube N44 is connected with the input end of an output buffer and is simultaneously connected with the drain end of N43, the drain end of N45, the drain end of P47 and the gate end of P4, the source end and the substrate are all connected with GND, and the drain end of an NMOS tube N44 is connected with the drain end of N42, the drain end of P46, the gate end of P45 and the gate end of N45;
the gate end of the NMOS tube N45 is connected with the drain end of N42, the drain end of N44, the drain end of P46 and the gate end of P45, and the source end and the substrate are connected with GND; the drain end of the NMOS tube N45 is connected with the input end of the output buffer and is simultaneously connected with the drain end of N43, the drain end of P47, the gate end of P44 and the gate end of N44;
the gate end of an NMOS tube N48 is connected with a pressure welding point EN and is simultaneously connected with the gate end of P48, the source end and the substrate are both connected with GND, and the drain end of an NMOS tube N48 is connected with the source end of N42 and the source end of N43; the grid end of the PMOS tube P48 is connected with a pressure welding point EN and is connected with the grid end of the N48, the source end and the substrate are connected with VDDOUT, and the drain end of the PMOS tube P48 is connected with the drain end of the P42, the drain end of the P43, the source end of the P44 and the source end of the P45.
4. The voltage latched level shifter circuit of claim 1, wherein the output buffer comprises a PMOS transistor P49 and an NMOS transistor N49; wherein the content of the first and second substances,
the gate end of the PMOS tube P49 is simultaneously connected with the drain end of P47, the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44; the source end of the PMOS tube P49 is connected with the substrate by the power supply voltage VDDOUT, the drain end is connected with the output pressure welding point OUT and is also connected with the drain end of the N49;
the gate end of the NMOS transistor N49 is simultaneously connected with the drain end of P47, the drain end of N43, the drain end of N45, the gate end of P44 and the gate end of N44; the source end and the substrate of the NMOS tube N49 are connected with GND, the drain end is connected with an output pressure welding point OUT, and the drain end of the NMOS tube N49 is connected with the drain end of the PMOS tube P49.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115208381A (en) * | 2022-09-06 | 2022-10-18 | 中国电子科技集团公司第五十八研究所 | High-speed level conversion structure supporting preset bits |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030179032A1 (en) * | 2002-03-25 | 2003-09-25 | Tomohiro Kaneko | Level shifter circuit and semiconductor device including the same |
| JP2003298408A (en) * | 2002-04-02 | 2003-10-17 | New Japan Radio Co Ltd | Level converting circuit |
| US20080238514A1 (en) * | 2007-04-02 | 2008-10-02 | Min-Su Kim | Level-converted and clock-gated latch and sequential logic circuit having the same |
| CN106899288A (en) * | 2017-02-21 | 2017-06-27 | 珠海市杰理科技股份有限公司 | Level shifting circuit |
| CN110620577A (en) * | 2019-10-12 | 2019-12-27 | 上海华力微电子有限公司 | FDSOI structure-based level conversion unit circuit and layout design method |
| CN110798201A (en) * | 2019-11-29 | 2020-02-14 | 重庆邮电大学 | High-speed withstand voltage level conversion circuit |
| CN214101345U (en) * | 2020-12-17 | 2021-08-31 | 中国电子科技集团公司第五十八研究所 | Level conversion structure supporting wide level range high-speed data |
-
2021
- 2021-10-25 CN CN202111241106.7A patent/CN113938126B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030179032A1 (en) * | 2002-03-25 | 2003-09-25 | Tomohiro Kaneko | Level shifter circuit and semiconductor device including the same |
| JP2003298408A (en) * | 2002-04-02 | 2003-10-17 | New Japan Radio Co Ltd | Level converting circuit |
| US20080238514A1 (en) * | 2007-04-02 | 2008-10-02 | Min-Su Kim | Level-converted and clock-gated latch and sequential logic circuit having the same |
| CN106899288A (en) * | 2017-02-21 | 2017-06-27 | 珠海市杰理科技股份有限公司 | Level shifting circuit |
| CN110620577A (en) * | 2019-10-12 | 2019-12-27 | 上海华力微电子有限公司 | FDSOI structure-based level conversion unit circuit and layout design method |
| CN110798201A (en) * | 2019-11-29 | 2020-02-14 | 重庆邮电大学 | High-speed withstand voltage level conversion circuit |
| CN214101345U (en) * | 2020-12-17 | 2021-08-31 | 中国电子科技集团公司第五十八研究所 | Level conversion structure supporting wide level range high-speed data |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115208381A (en) * | 2022-09-06 | 2022-10-18 | 中国电子科技集团公司第五十八研究所 | High-speed level conversion structure supporting preset bits |
| CN115208381B (en) * | 2022-09-06 | 2022-11-22 | 中国电子科技集团公司第五十八研究所 | High-speed level conversion structure supporting preset bits |
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