CN112564689B - Multi-protocol IO multiplexing circuit - Google Patents
Multi-protocol IO multiplexing circuit Download PDFInfo
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- CN112564689B CN112564689B CN202011458589.1A CN202011458589A CN112564689B CN 112564689 B CN112564689 B CN 112564689B CN 202011458589 A CN202011458589 A CN 202011458589A CN 112564689 B CN112564689 B CN 112564689B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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Abstract
The invention provides a multi-protocol IO multiplexing circuit, wherein an output driving module comprises a pull-up branch and a pull-down branch, the pull-up branch comprises a pull-up transistor, the pull-down branch comprises a pull-down transistor, a first driving output end outputs a first driving signal, and a second driving output end outputs a second driving signal; the bias generation module comprises an output replication circuit, a pull-up negative feedback loop and a pull-down negative feedback loop, wherein the output replication circuit replicates the output driving module in equal proportion and obtains a high direct current working point of a first driving signal and a low direct current working point of a second driving signal. The output driving module provided by the invention meets a low-speed single-ended driving mode and a high-speed differential driving mode, and controls the output polarity of the first driving signal and the second driving signal through digital signals.
Description
Technical Field
The invention relates to the field of chip design, in particular to a multi-protocol IO multiplexing circuit.
Background
IO is an English abbreviation for Output and Output (Input/Output). IO circuits are an important component of electronic circuits, particularly integrated circuits, in which IO circuits connect the integrated circuit core to peripheral circuits, serving as level matching, impedance transformation, power amplification, protection, and the like. In the high-speed serial interface IO circuit, especially in the IO driving circuit of the voltage output mode, in order to guarantee the signal consistency, the size of the capacitive load can influence the rising or falling time of the signal, and then influence the data transmission rate. In addition, for consumer electronic products, in order to compress the cost of the chip, a certain design is required to simultaneously satisfy multiple application scenarios, including the electrical standard of the interface that needs to be adapted to multiple application platforms. The prior art has the practice of connecting IO circuits of various electrical standards in parallel at the output end, but the parallel connection of a plurality of IOs can cause the multiplication of capacitive load.
Typical high-speed serial interface signals generally have differential, low swing characteristics, which can be classified as voltage driven and current driven from drive types. The common current driven IO circuit is provided with constant driving current by a tail current source, the output common mode point of the common mode current source is determined by a common mode feedback circuit, and the LVDS interface generally adopts a current driven IO structure. The IO circuit adopting the voltage driving logic determines the performances of common mode output, differential swing and the like by managing the power supply voltage of an output stage, and the MIPI interface generally adopts the voltage driving logic.
In the high-speed serial interface electrical standard, the dc performance and ac performance of the signal are generally defined, wherein the dc performance includes signal swing, common mode range, etc.; the ac performance includes ripple magnitude, signal transition time, etc. The alternating current performance of the interface of the IO mainly depends on the output equivalent impedance and the load condition, wherein the size of the capacitive load not only affects the signal conversion time, but also affects the ripple size, and the higher the interface speed is, the higher the requirements for reducing the signal conversion time and inhibiting the ripple are. If different electrical standards can be met with one drive configuration, it would be greatly advantageous to control the capacitive load at the output. Therefore, the same circuit structure is adopted to meet different interface electrical standards, and no effective solution is available for the problem.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a multi-protocol IO multiplexing circuit.
To achieve the above object, the present invention provides a multiprotocol IO multiplexing circuit, which is characterized by comprising:
The output driving module is provided with a pull-up input end, a pull-down input end, a first digital input end, a second digital input end, a first driving output end and a second driving output end, the output driving module comprises a pull-up branch and a pull-down branch, the pull-up branch comprises a pull-up transistor, the pull-down branch comprises a pull-down transistor, a grid electrode of the pull-up transistor is connected with the pull-up input end and is connected with a pull-up bias signal, a grid electrode of the pull-down transistor is connected with the pull-down input end and is connected with the pull-down bias signal, the first driving output end outputs a first driving signal, and the second driving output end outputs a second driving signal;
The bias generation module is provided with a pull-up reference input end, a pull-down reference input end, a pull-up feedback output end and a pull-down feedback output end, and comprises an output copying circuit, a pull-up negative feedback loop and a pull-down negative feedback loop, wherein the output copying circuit copies the output driving module in equal proportion and obtains a high direct current working point of a first driving signal and a low direct current working point of a second driving signal; one side of the pull-up negative feedback loop is connected with the pull-up reference input end and is connected with a pull-up analog reference signal, the pull-up analog reference signal and the high direct current working point are compared, a pull-up analog feedback signal is output to a pull-up feedback output end, one side of the pull-down negative feedback loop is connected with the pull-down reference input end and is connected with a pull-down analog reference signal, the pull-down analog reference signal and the low direct current working point are compared, and a pull-down analog feedback signal is output to the pull-down feedback output end;
A first pull-up input end of the pull-up two-way one-out selector is connected with the pull-up feedback output end, a second pull-up input end is connected with a first potential, a pull-up output end is connected with the pull-up input end, and a pull-up control end is connected with a control node;
A first pull-down input end of the pull-down two-way one-out selector is connected with the pull-down feedback output end, a second pull-down input end is connected with a second potential, a pull-down output end is connected with the pull-down input end, and a pull-down control end is connected with the control node;
The mode control module is provided with a control input end, a first input end, a second input end, a third input end, a first output end and a second output end, wherein the control input end is connected with the control node, the control node is connected with a mode control signal, the first input end is connected with a first control signal, the second input end is connected with a second control signal, the third input end is connected with a third control signal, the first output end is connected with the first digital input end, the second output end is connected with the second digital input end, the first control signal and the second control signal are low-speed single-ended bit signals, and the third control signal is a high-speed differential signal.
Preferably, the mode control signal is a low potential, the bias generation module is in a closed state, the pull-up output end outputs a first potential, the pull-down output end outputs a second potential, the gate of the pull-up transistor is set low, the gate of the pull-down transistor is set high, the pull-up transistor and the pull-down transistor are in a linear region to operate, and the potentials of the first driving signal and the second driving signal are full swing signals.
Preferably, the first potential is ground potential, and the second potential is a power point; or, the first potential is a power supply potential, and the second potential is a ground potential.
Preferably, the mode control signal is at a high potential, the bias generation module is in an on state, the pull-up output end outputs the pull-up analog feedback signal, the pull-down output end outputs the pull-down analog feedback signal, the pull-up transistor and the pull-down transistor are in a saturation region to operate, and the potentials of the first driving signal and the second driving signal are low-swing differential signals.
Preferably, the pull-up branch further comprises a first pull-up differential switch and a second pull-up differential switch, and the pull-down branch further comprises a first pull-down differential switch and a second pull-down differential switch; the first control signal controls the on or off of the first pull-up differential switch and the first pull-down differential switch, and the second control signal controls the on or off of the second pull-up differential switch and the second pull-down differential switch.
Preferably, the first pull-up differential switch is a first pull-up differential transistor, the second pull-up differential switch is a second pull-up differential transistor, the first pull-down differential switch is a first pull-down differential transistor, the second pull-up differential switch is a second pull-up differential transistor, a gate of the first pull-up differential transistor and a gate of the first pull-down differential transistor are commonly connected to the first digital input terminal, and a gate of the second pull-up differential transistor and a gate of the second pull-down differential transistor are commonly connected to the second digital input terminal, wherein: the source electrode of the pull-up transistor is connected with a power supply, the grid electrode of the pull-up transistor is connected with the pull-up input end, and the drain electrode of the pull-up transistor is commonly connected with the source electrode of the first pull-up differential transistor and the source electrode of the second pull-up differential transistor; the drain electrode of the first pull-up differential transistor is connected with the first end of a first resistor, the second end of the first resistor is connected with the first driving output end, a first node is arranged between the second end of the first resistor and the first driving output end, the anode of the first diode and the cathode of the second diode are commonly connected to the first node, the cathode of the first diode is connected with the power supply, and the anode of the second diode is grounded; the drain electrode of the second pull-up differential transistor is connected with the first end of a second resistor, the second end of the second resistor is connected with the second driving output end, a second node is arranged between the second end of the second resistor and the second driving output end, the anode of a third diode and the cathode of a fourth diode are commonly connected to the second node, the cathode of the third diode is connected with the power supply, and the anode of the fourth diode is grounded; the source electrode of the pull-down transistor is connected with a power supply, the grid electrode of the pull-down transistor is connected with the pull-down input end, and the drain electrode of the pull-down transistor is commonly connected with the source electrode of the first pull-down differential transistor and the source electrode of the second pull-up differential transistor; the drain of the first pull-down differential transistor and the drain of the first pull-up differential transistor are commonly connected to the first end of the first resistor, and the drain of the second pull-down differential transistor and the drain of the second pull-up differential transistor are commonly connected to the first end of the second resistor.
Preferably, the pull-up transistor, the first pull-up differential transistor and the second pull-up differential transistor are PMOS transistors, and the pull-down transistor, the first pull-down differential transistor and the second pull-up differential transistor are NMOS transistors; or the pull-up transistor, the first pull-up differential transistor and the second pull-up differential transistor are NMOS transistors, and the pull-down transistor, the first pull-down differential transistor and the second pull-up differential transistor are PMOS transistors.
Preferably, the output stage replica circuit includes a first replica transistor, a second replica transistor, a third replica transistor, a fourth replica transistor, a first replica resistor, a second replica resistor, and a third replica resistor, the pull-up negative feedback loop includes a pull-up amplifier, and the pull-down negative feedback loop includes a pull-down amplifier; the source electrode of the first replica transistor is connected with the power supply, the grid electrode of the first replica transistor is connected with the output end of the pull-up amplifier, the drain electrode of the second replica transistor is connected with the source electrode of the second replica transistor, the grid electrode of the second replica transistor is grounded, the drain electrode of the second replica transistor is connected with the first end of the first replica resistor, the second end of the first replica resistor and the first end of the second replica resistor are commonly connected with the reverse input end of the pull-up amplifier, the forward input end of the pull-up amplifier is connected with the pull-up analog reference signal, the output end of the pull-up amplifier outputs a pull-up analog feedback signal to the first replica transistor, the second end of the second replica resistor and the first end of the third replica resistor are commonly connected with the forward input end of the pull-down amplifier, the reverse input end of the pull-down amplifier is connected with the pull-down analog reference signal, the output end of the second replica resistor is commonly connected with the drain electrode of the third replica transistor, the grid electrode of the third replica transistor is connected with the fourth replica transistor, and the drain electrode of the fourth replica transistor is connected with the drain electrode of the fourth replica transistor.
Preferably, the first replica transistor equally replicates the pull-up transistor, the first replica resistor equally replicates the first resistor, the second replica transistor equally replicates the second resistor, and the fourth replica transistor equally replicates the pull-down transistor.
Preferably, the mode control module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first mode selector and a second mode selector, where an input end of the first inverter is connected to the first input end, an output end of the first inverter is connected to a first selection input end of the first mode selector, an input end of the second inverter is connected to the second input end, an output end of the second inverter is connected to a first selection input end of the second mode selector, an input end of the third inverter is connected to the third input end, an output end of the third inverter is connected to an input end of the fourth inverter, and an output end of the fourth inverter is connected to a second selection input end of the second mode selector; the second selection input end of the first mode selector is connected with the output end of the third phase inverter, the control end and the control end of the second mode selector are connected to the control input end together, the output end is connected with the first output end, and the output end of the second mode selector is connected with the second output end.
According to the technical scheme, the multi-protocol IO multiplexing circuit provided by the invention has the advantages that the low-speed single-ended driving mode and the high-speed differential driving mode are realized by one output driving circuit through IO multiplexing, the output polarity of driving signals is controlled by digital signals, the interface circuit with the structure can simultaneously meet the requirements of different application platforms on serial interfaces and parallel interfaces, the parasitic capacitance of an output end is greatly reduced, the guarantee of the interface rate is facilitated, the area of an IO circuit is greatly reduced, and the multi-protocol IO multiplexing circuit is a low-cost, high-speed and high-compatibility IO driving circuit structure and has remarkable significance.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a multiprotocol IO multiplexing circuit according to a preferred embodiment of the present invention.
Fig. 2 is a schematic diagram of an output driving module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the present invention.
Fig. 3 is a schematic diagram of a bias generation output module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the present invention.
Fig. 4 is a schematic diagram of an output mode control module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the present invention.
Detailed Description
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
In the following detailed description of the embodiments of the present invention, the structures of the present invention are not drawn to a general scale, and the structures in the drawings are partially enlarged, deformed, and simplified, so that the present invention should not be construed as being limited thereto.
For the purpose of making the objects, technical solutions and advantages of the present invention more clear, the following description will describe the detailed implementation of the present invention in detail with reference to fig. 1 and 2, fig. 1 is a schematic diagram of a multiprotocol IO multiplexing circuit according to a preferred embodiment of the present invention, and fig. 2 is a schematic diagram of an output driving module of a multiprotocol IO multiplexing circuit according to a preferred embodiment of the present invention.
As shown in fig. 1, a multi-protocol IO multiplexing circuit structure of a preferred embodiment of the present invention includes an output driving module 1, a mode control module 3 and a bias generation module 2, wherein one side of the output driving module 1 is connected to the mode control module 3 and the bias generation module 2, and the other side outputs a driving signal, and the driving signal includes a first driving signal OP and a second driving signal ON. The output driving module 1 is provided with a pull-up input end, a pull-down input end, a first digital input end, a second digital input end, a first driving output end and a second driving output end, wherein the first driving output end outputs the first driving signal OP, and the second driving output end outputs the second driving signal ON.
The bias generation module 2 is connected with the output driving module 1 through a two-way selection circuit, one side of the bias generation module 2 is input with an analog reference signal, the other side of the bias generation module 2 is output with an analog feedback signal to the two-way selection circuit, the two-way selection circuit outputs a bias signal to the output driving module 1 according to the analog feedback signal, the bias signal comprises a pull-up bias signal VBP and a pull-down bias signal VBN, the pull-up input end is input with the pull-up bias signal VBP, and the pull-down input end is input with the pull-down bias signal VBN.
The output driving module 1 switches output modes according to the bias signal, wherein the output modes comprise a differential mode and a single-ended mode. The differential mode is a high-speed differential output mode, and the single-ended mode is a low-speed single-ended output mode. The output driving module 1 comprises a pull-up branch and a pull-down branch, the pull-up branch comprises a pull-up transistor, the pull-down branch comprises a pull-down transistor, a grid electrode of the pull-up transistor is connected with the pull-up input end, and a grid electrode of the pull-down transistor is connected with the pull-down input end.
One side of the mode control module 3 is connected with the control node M, the other side outputs a digital signal to the output driving module 1, the digital signal controls the output polarity of the driving signal, the digital signal comprises a first digital signal INP and a second digital signal INN, the first digital signal INP controls the polarity of the first driving signal OP, the second digital signal INN controls the polarity of the second driving signal ON, the first digital input end is connected to the first digital signal INP, and the second digital input end is connected to the second digital signal INN.
The bias generation module 2 is provided with a pull-up reference input end, a pull-down reference input end, a pull-up feedback output end and a pull-down feedback output end, and the two-way selection circuit comprises a pull-up two-way one-out selector and a pull-down two-way two-out one-out selector. One side of the bias generation module 2 inputs an analog reference signal, and the other side is respectively connected with a pull-up two-way one-out selector and a pull-down two-way two-out selector. The bias generation module 2 outputs an analog feedback signal to the two-way selection circuit according to the analog reference signal. The analog reference signals include a pull-up analog reference signal vref_h and a pull-down analog reference signal vref_l, and the analog feedback signals include a pull-up analog feedback signal vbp_fb and a pull-down analog feedback signal vbn_fb.
The pull-up reference input terminal is connected to the pull-up analog reference signal VREF_H, and the pull-down reference input terminal is connected to the pull-down analog reference signal VREF_L. The first pull-up input end of the pull-up two-way alternative selector is connected with the pull-up feedback output end and is connected with a pull-up analog feedback signal VBP_FB, the second pull-up input end is connected with a first potential FIX_H, the pull-up output end is connected with the pull-up input end and outputs the pull-up bias signal VBP, and the pull-up control end is connected with the control node M. The first pull-down input end of the pull-down two-way alternative selector is connected with the pull-down feedback output end and is connected with a pull-down analog feedback signal VBN_FB, the second pull-down input end is connected with a second potential FIX_L, the pull-down output end is connected with the pull-down input end and outputs the pull-down bias signal VBN, and the pull-down control end is connected with the control node M.
The bias generating module 2 comprises an output copying circuit, a pull-up negative feedback loop and a pull-down negative feedback loop, wherein the output copying circuit copies the output driving module 1 in equal proportion and obtains a high direct current working point of the first driving signal OP and a low direct current working point of the second driving signal ON, wherein the high direct current working point represents a high potential of the first driving signal OP, and the low direct current working point represents a low potential of the second driving signal ON. The pull-up negative feedback loop automatically adjusts the pull-up bias voltage by comparing the high DC operating point with the pull-up analog reference voltage, and the pull-down negative feedback loop automatically adjusts the pull-down bias voltage by comparing the low DC operating point with the pull-down analog reference voltage.
One side of the pull-up negative feedback loop is connected with the pull-up reference input end and is connected with a pull-up analog reference signal VREF_H, the pull-up analog reference signal and the high direct current working point are compared, a pull-up analog feedback signal VBP_FB is output to the pull-up feedback output end, one side of the pull-down negative feedback loop is connected with the pull-down reference input end and is connected with a pull-down analog reference signal VREF_L, and the pull-down analog reference signal and the low direct current working point are compared, and a pull-down analog feedback signal VBN_FB is output to the pull-down feedback output end.
As shown in fig. 1, the control end of the pull-up two-way one-out-of-two selector and the control end of the pull-down two-way one-out-of-two controller are commonly connected to the control node M, the control node M is connected to a MODE control signal mode_ctr, when the MODE control signal mode_ctr is high-potential, the differential MODE is a high-speed signal transmission MODE, the bias generation module 2 is in an ON state, the pull-up two-way one-out-of-two-way selector outputs the pull-up bias signal VBP to the gate of the pull-up transistor, the pull-down two-way one-out-of-two selector outputs the pull-down bias signal VBN to the gate of the pull-down transistor, the pull-up transistor and the pull-down transistor are in saturation region, and the first driving signal OP and the second driving signal ON are low swing differential signals. When the MODE control signal mode_ctr is low, the single-ended MODE is a low-speed signal transmission MODE, the bias generating module 2 is in a closed state, the pull-up output end output by the pull-up two-way one-out-of-the-selector outputs a first potential fix_h, the pull-down output end output by the pull-down two-way two-out-of-the-selector outputs a second potential fix_l, the grid electrode of the pull-up transistor is low, the grid electrode of the pull-down transistor is high, the pull-up transistor and the pull-down transistor are in a linear region and operate, and the potentials of the first driving signal and the second driving signal are full-swing signals.
Wherein the first potential fix_h is a ground potential, and the second potential fix_l is a power point; or, the first potential fix_h is a power supply potential, and the second potential fix_l is a ground potential. In the high-speed interface electrical standard, a differential swing VOD and a common mode voltage VCM are generally defined, with the high potential corresponding to the output voltage being vcm+vod/2 and the low potential being VCM-VOD/2. The voltage of the pull-up bias signal and the voltage of the pull-down bias signal are enabled to meet the electrical standard requirements related to the interface through a pull-up negative feedback loop and a pull-down negative feedback loop in the bias generation circuit 2 as long as the voltage vref_h=vcm+vod/2 of the pull-up analog reference signal vref_h and the voltage vref_l=vcm-VOD/2 of the pull-down analog reference signal vref_l are enabled to be different from each other as defined by different high-speed interface protocols. Meanwhile, in the single-ended mode, the bias generation module 2 is in a sleep state to save power consumption.
The mode control module 3 is provided with a control input end, a first input end, a second input end, a third input end, a first output end and a second output end, wherein the control input end is connected with the control node M, the control node M is connected with a mode control signal, the first input end is connected with a first control signal, the second input end is connected with a second control signal, the third input end is connected with a third control signal, the first output end is connected with the first digital input end, the second output end is connected with the second digital input end, the first control signal and the second control signal are low-speed single-ended bit signals, and the third control signal is a high-speed differential signal.
Fig. 2 is a schematic diagram of an output driving module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention. The output driving module 1 comprises a pull-up branch and a pull-down branch, wherein the pull-up branch further comprises a first pull-up differential switch and a second pull-up differential switch, and the pull-down branch further comprises a first pull-down differential switch and a second pull-down differential switch. The first digital signal controls the on or off of the first pull-up differential switch and the first pull-down differential switch, and the second digital signal controls the on or off of the second pull-up differential switch and the second pull-down differential switch. The first pull-up differential switch and the first pull-down differential switch are PMOS transistors, and the second pull-up differential switch and the second pull-down differential switch are NMOS transistors; or, the first pull-up differential switch and the first pull-down differential switch are NMOS transistors, and the second pull-up differential switch and the second pull-down differential switch are PMOS transistors.
In this embodiment, the first pull-up differential switch is a first pull-up differential transistor sw_p1, the second pull-up differential switch is a second pull-up differential transistor sw_p2, the first pull-down differential switch is a first pull-down differential transistor sw_n1, and the second pull-up differential switch is a second pull-up differential transistor sw_n2; the gate of the first pull-up differential transistor sw_p1 and the gate of the first pull-down differential transistor sw_n1 are commonly connected to the first digital input terminal, and the gate of the second pull-up differential transistor sw_p2 and the gate of the second pull-down differential transistor sw_n2 are commonly connected to the second digital input terminal, wherein: the source electrode of the pull-up transistor PM0 is connected with the power supply VDDA, the grid electrode of the pull-up transistor PM0 is connected with the pull-up input end, the pull-up bias signal VBP is connected with the grid electrode of the pull-up transistor PM0, and the drain electrode of the pull-up bias signal VBP is commonly connected with the source electrode of the first pull-up differential transistor SW_P1 and the source electrode of the second pull-up differential transistor SW_P2; the grid electrode of the first pull-up differential transistor SW_P1 is connected with the first digital input end, the first digital signal INP is connected with the grid electrode of the first pull-up differential transistor SW_P1, the drain electrode of the first pull-up differential transistor SW_P1 is connected with the first end of a first resistor R1, the second end of the first resistor R1 is connected with the first driving output end, the first driving output end is used for outputting a first driving signal OP, a first node is arranged between the second end of the first resistor R1 and the first driving output end, the anode of a first diode and the cathode of a second diode are commonly connected to the first node, the cathode of the first diode is connected with the power supply VDDA, and the anode of the second diode is grounded (VSSA); the grid electrode of the second pull-up differential transistor SW_P2 is connected with the second digital input end, the second digital signal INN is connected with the grid electrode of the second pull-up differential transistor SW_P2, the drain electrode of the second pull-up differential transistor SW_P2 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with the second driving output end, the second driving output end is used for outputting a second driving signal ON, a second node is arranged between the second end of the second resistor R2 and the second driving output end, the anode of the third diode and the cathode of the fourth diode are commonly connected to the second node, the negative electrode of the third diode is connected with the power supply VDDA, and the positive electrode of the fourth diode is grounded (VSSA); the source electrode of the pull-down transistor NM0 is connected with the power supply VDDA, the grid electrode of the pull-down transistor NM0 is connected with the pull-down input end, the second bias signal VBN is connected with the grid electrode of the pull-down transistor NM0, and the drain electrode of the pull-down transistor NM0 is commonly connected with the source electrode of the first pull-down differential transistor SW_N1 and the source electrode of the second pull-up differential transistor SW_N2; the gate of the first pull-down differential transistor sw_n1 is connected to the first digital input terminal, the first digital signal INP is connected to the gate of the first pull-down differential transistor sw_n1, the drain of the first pull-down differential transistor sw_n1 and the drain of the first pull-up differential transistor sw_n2 are commonly connected to the first terminal of the first resistor R1, the gate of the second pull-up differential transistor sw_n2 is connected to the second digital input terminal, the second digital signal INN is connected to the gate of the second pull-down differential transistor sw_n2, and the drain of the second pull-up differential transistor sw_p2 and the drain of the second pull-down differential transistor sw_n2 are commonly connected to the first terminal of the second resistor R2. In an embodiment, the pull-up transistor PM0, the first pull-up differential transistor sw_p1 and the second pull-up differential transistor sw_p2 are NMOS transistors; the pull-down transistor NM0, the first pull-down differential transistor SW_N1 and the second pull-up differential transistor SW_N2 are PMOS transistors; in another embodiment, the pull-up transistor PM0, the first pull-up differential transistor sw_p1 and the second pull-up differential transistor sw_p2 are PMOS transistors; the pull-down transistor NM0, the first pull-down differential transistor sw_n1 and the second pull-up differential transistor sw_n2 are NMOS transistors.
In the high-speed differential output mode, the pull-up two-way one-out selector selects and outputs the pull-up analog feedback signal vbp_fb to the pull-up input end, that is, the pull-up bias signal VBP is the pull-up analog feedback signal vbp_fb, and the pull-down two-way one-out selector selects and outputs the pull-down analog feedback signal vbn_fb to the pull-down input end, that is, the pull-down bias signal VBN is the pull-down analog feedback signal vbn_fb, and the pull-up transistor PM0 and the pull-down transistor NM0 both operate in a saturation region and can be equivalently a tail current source; the first pull-up differential transistor sw_p1, the second pull-up differential transistor sw_p2, the first pull-down differential transistor sw_n1 and the second pull-down differential transistor sw_n2 all operate in a linear region and are equivalent to switching devices, wherein when the gate voltage is low, the first pull-up differential transistor sw_p1 and the second pull-up differential transistor sw_p2 are in an on state; when the gate voltage is at a high potential, the first pull-down differential transistor sw_n1 and the second pull-down differential transistor sw_n2 are turned ON, and otherwise turned off, and the potentials of the first driving signal OP and the second driving signal ON are low swing differential signals.
In the low-speed single-ended mode, the bias generating module 2 is in a closed state, the outputs of the pull-up two-way one-way selector and the pull-down two-way one-way selector are respectively pulled to a fixed value, the pull-up two-way one-way selector selects and outputs the first potential fix_h, and the pull-down two-way one-way selector selects and outputs the second potential fix_l. In an embodiment, the first potential fix_h is a ground potential, the second potential fix_l is a power point, the pull-up bias signal VBP is set to the ground potential, the pull-down bias signal VBN is set to the power point, the pull-up transistor PM0 and the pull-down transistor NM0 both operate in a linear region and may be equivalently turned ON switches, and the potentials of the first driving signal OP and the second driving signal ON are full swing signals. In another embodiment, the first potential fix_h is a power supply potential, the second potential fix_l is a ground potential, the pull-up bias signal VBP is set to a power supply point, the pull-down bias signal VBN is set to a ground potential, the pull-up transistor PM0 and the pull-down transistor NM0 are both in a cut-off region, which is equivalent to a cut-off switch, the pull-up branch and the pull-down branch of the output driving module 1 are both disconnected, and the output is in a high-resistance state, which is equivalent to a buffer circuit with enabling control.
As shown in fig. 3, fig. 3 is a schematic diagram of a bias generation output module 3 of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the present invention. The output stage replica circuit comprises a first replica transistor PM0_cp, a second replica transistor PM1, a third replica transistor NM1, a fourth replica transistor NM0_cp, a first replica resistor r1, a second replica resistor r_term and a third replica resistor r2, the pull-up negative feedback loop comprises a pull-up amplifier, and the pull-down negative feedback loop comprises a pull-down amplifier; the source electrode of the first copying transistor PM0_cp is connected with the power supply VDDA, the grid electrode of the first copying transistor PM1 is connected with the output end of the pull-up amplifier, and the drain electrode of the first copying transistor PM1 is connected with the source electrode of the second copying transistor PM 1; the gate of the second replica transistor PM1 is grounded (VSSA), the drain is connected to the first end of the first replica resistor r1, the second end of the first replica resistor r1 and the first end of the second replica resistor r_term are commonly connected to the inverting input end of the pull-up amplifier, the forward input end of the pull-up amplifier is connected to the pull-up analog reference signal vref_h, the output end outputs a pull-up analog feedback signal to the gate of the first replica transistor pm0_cp, the second end of the second replica resistor r_term and the first end of the third replica resistor r2 are commonly connected to the forward input end of the pull-down amplifier, the inverting input end of the pull-down amplifier is connected to the pull-down analog reference signal vref_l, the output end outputs a pull-down analog feedback signal to the gate of the fourth transistor vdd, the second end of the third replica resistor r2 is connected to the drain of the third replica transistor NM1, the gate of the third replica transistor NM1 is connected to the gate of the fourth replica transistor nm_0, and the drain of the fourth replica transistor nm_0 is connected to the drain of the fourth replica transistor nm_cp. In this embodiment, the first replica transistor pm0_cp and the second replica transistor PM1 are PMOS transistors, and the third replica transistor NM1 and the fourth replica transistor nm0_cp are NMOS transistors; in another embodiment, the first replica transistor pm0_cp and the second replica transistor PM1 are NMOS transistors, and the third replica transistor NM1 and the fourth replica transistor nm0_cp are PMOS transistors.
In the high-speed differential output mode, since the pull-up bias signal is a pull-up analog feedback signal, i.e., vbp=vbp_fb, the first replica transistor pm0_cp is a replica of the pull-up transistor PM0 in the output driving module 1; in the low-speed single-ended mode, the bias generating module 2 is in a closed state, the gate of the second replica transistor PM1 is set low, the first pull-up differential transistor sw_p1 and the second pull-up differential transistor sw_p1 in the output driving module 1 are replicated by the pull-up negative feedback loop, the first replica resistor R1 and the third replica resistor R2 are replicated by the first resistor R1 and the second resistor R2 in the output driving module 2, and the second replica resistor r_term is replicated by the termination resistor of the high-speed differential interface terminal; the gate of the third replica transistor NM1 is high, the pull-down negative feedback loop replicates the first pull-down differential transistor sw_n1 and the second pull-up differential transistor sw_n2 in the output drive module 1, the source of the fourth replica transistor nm0_cp is grounded, and the fourth replica transistor nm0_cp replicates the pull-down transistor in the output drive module 1. In a normal working state, the static working current of the output driving module 1 is in the milliamp level, in order to save the power consumption of the replica circuit, the device size of each transistor in the output stage replica circuit is set according to a certain proportion of the device size of each corresponding transistor in the output driving module 1, wherein the width of the device PM0_cp/PM1/NM0_cp/NM1 respectively takes 1/k of the corresponding replica device in the output driving circuit 1, and correspondingly, the value of r1/r2/r_term is k times of the corresponding replica device in the output driving circuit 1.
Fig. 4 is a schematic diagram of an output mode control module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention. The control signal input end is connected with the control node MODE_CTR, the first control input end is connected with a first control signal SG_IN <0>, the second control input end is connected with a second control signal SG_IN <1>, the third control input end is connected with a third control signal DIF_IN, the first control output end is connected with the first digital input end, the second control output end is connected with the second digital input end, the first control signal SG_IN <0> and the second control signal SG_IN <1> are low-speed single-ended bit signals, and the third control signal DIF_IN is a high-speed differential signal.
The mode control module 3 comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first mode selector and a second mode selector, wherein the input end of the first inverter is connected with the first control input end, the output end of the first inverter is connected with the first selection input end of the first mode selector MUX_0, the input end of the second inverter is connected with the second control input end, the output end of the second inverter is connected with the first selection input end of the second mode selector MUX_1, the input end of the third inverter is connected with the third control input end, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is connected with the second selection input end of the second mode selector MUX_1; the second selection input end of the first mode selector MUX_0 is connected with the input end of the fourth inverter and is connected with the reverse signal of the third control signal, the control end and the control end of the second mode selector MUX_1 are commonly connected to the control node, the output end is connected with the first control output end and outputs a first digital signal INP, and the output end of the second mode selector MUX_1 is connected with the second control output end and outputs a second digital signal INN.
The switching of the digital signals in different MODEs is realized through the MODE control signal MODE_CTR. In the low-speed single-ended mode, the first control output end outputs the first control signal to the first digital input end, the second control output end outputs the second control signal to the second digital input end, and the output driving module 1 is equivalent to a buffer circuit with enabling control. In this mode, INP/INN are two independent signals, which are controlled by the mode selection circuit 3 to satisfyIn the high-speed differential output mode, the third control output end outputs the third control signal,/>INN＝DIFF_IN。
The multi-protocol IO multiplexing circuit prepared by the method realizes a low-speed single-ended driving mode and a high-speed differential driving mode by using the same output driving circuit, and the interface circuit with the structure can simultaneously meet the requirements of different application platforms on a serial interface and a parallel interface. The invention realizes the support of various interface modes and electrical standards under the condition of not additionally connecting with the IO drive circuit in parallel by controlling the mode of the same IO circuit, greatly reduces the parasitic capacitance of the output end, is beneficial to the guarantee of the interface rate, greatly reduces the area of the IO circuit, is an IO drive circuit structure with low cost, high speed and high compatibility, and has remarkable significance.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A multiprotocol IO multiplexing circuit, comprising:
The output driving module is provided with a pull-up input end, a pull-down input end, a first digital input end, a second digital input end, a first driving output end and a second driving output end, the output driving module comprises a pull-up branch and a pull-down branch, the pull-up branch comprises a pull-up transistor, the pull-down branch comprises a pull-down transistor, a grid electrode of the pull-up transistor is connected with the pull-up input end and is connected with a pull-up bias signal, a grid electrode of the pull-down transistor is connected with the pull-down input end and is connected with the pull-down bias signal, the first driving output end outputs a first driving signal, and the second driving output end outputs a second driving signal;
The bias generation module is provided with a pull-up reference input end, a pull-down reference input end, a pull-up feedback output end and a pull-down feedback output end, and comprises an output copying circuit, a pull-up negative feedback loop and a pull-down negative feedback loop, wherein the output copying circuit copies the output driving module in equal proportion and obtains a high direct current working point of a first driving signal and a low direct current working point of a second driving signal; one side of the pull-up negative feedback loop is connected with the pull-up reference input end and is connected with a pull-up analog reference signal, the pull-up analog reference signal and the high direct current working point are compared, a pull-up analog feedback signal is output to a pull-up feedback output end, one side of the pull-down negative feedback loop is connected with the pull-down reference input end and is connected with a pull-down analog reference signal, the pull-down analog reference signal and the low direct current working point are compared, and a pull-down analog feedback signal is output to the pull-down feedback output end;
A first pull-up input end of the pull-up two-way one-out selector is connected with the pull-up feedback output end, a second pull-up input end is connected with a first potential, a pull-up output end is connected with the pull-up input end, and a pull-up control end is connected with a control node;
A first pull-down input end of the pull-down two-way one-out selector is connected with the pull-down feedback output end, a second pull-down input end is connected with a second potential, a pull-down output end is connected with the pull-down input end, and a pull-down control end is connected with the control node;
The mode control module is provided with a control input end, a first input end, a second input end, a third input end, a first output end and a second output end, wherein the control input end is connected with the control node, the control node is connected with a mode control signal, the first input end is connected with a first control signal, the second input end is connected with a second control signal, the third input end is connected with a third control signal, the first output end is connected with the first digital input end, the second output end is connected with the second digital input end, the first control signal and the second control signal are low-speed single-ended bit signals, and the third control signal is a high-speed differential signal.
2. The multi-protocol IO multiplexing circuit of claim 1, wherein the mode control signal is low, the bias generation module is off, the pull-up output outputs a first potential, the pull-down output outputs a second potential, the gate of the pull-up transistor is low, the gate of the pull-down transistor is high, the pull-up transistor and the pull-down transistor are in a linear region, and the potentials of the first drive signal and the second drive signal are full swing signals.
3. The multiprotocol IO multiplexing circuit of claim 2, wherein the first potential is ground potential and the second potential is a power supply point; or, the first potential is a power supply potential, and the second potential is a ground potential.
4. The multi-protocol IO multiplexing circuit of claim 1, wherein the mode control signal is high, the bias generation module is in an on state, the pull-up output outputs the pull-up analog feedback signal, the pull-down output outputs the pull-down analog feedback signal, the pull-up transistor and the pull-down transistor are in saturation region operation, and the first drive signal and the second drive signal are in low swing differential signals.
5. The multi-protocol IO multiplexing circuit of claim 1, wherein the pull-up leg further comprises a first pull-up differential switch and a second pull-up differential switch, the pull-down leg further comprising a first pull-down differential switch and a second pull-down differential switch; the first control signal controls the on or off of the first pull-up differential switch and the first pull-down differential switch, and the second control signal controls the on or off of the second pull-up differential switch and the second pull-down differential switch.
6. The multi-protocol IO multiplexing circuit of claim 5, wherein the first pull-up differential switch is a first pull-up differential transistor, the second pull-up differential switch is a second pull-up differential transistor, the first pull-down differential switch is a first pull-down differential transistor, the second pull-up differential switch is a second pull-up differential transistor, the gate of the first pull-up differential transistor and the gate of the first pull-down differential transistor are commonly connected to the first digital input terminal, the gate of the second pull-up differential transistor and the gate of the second pull-down differential transistor are commonly connected to the second digital input terminal, wherein: the source electrode of the pull-up transistor is connected with a power supply, the grid electrode of the pull-up transistor is connected with the pull-up input end, and the drain electrode of the pull-up transistor is commonly connected with the source electrode of the first pull-up differential transistor and the source electrode of the second pull-up differential transistor; the drain electrode of the first pull-up differential transistor is connected with the first end of a first resistor, the second end of the first resistor is connected with the first driving output end, a first node is arranged between the second end of the first resistor and the first driving output end, the anode of the first diode and the cathode of the second diode are commonly connected to the first node, the cathode of the first diode is connected with the power supply, and the anode of the second diode is grounded; the drain electrode of the second pull-up differential transistor is connected with the first end of a second resistor, the second end of the second resistor is connected with the second driving output end, a second node is arranged between the second end of the second resistor and the second driving output end, the anode of a third diode and the cathode of a fourth diode are commonly connected to the second node, the cathode of the third diode is connected with the power supply, and the anode of the fourth diode is grounded; the source electrode of the pull-down transistor is connected with a power supply, the grid electrode of the pull-down transistor is connected with the pull-down input end, and the drain electrode of the pull-down transistor is commonly connected with the source electrode of the first pull-down differential transistor and the source electrode of the second pull-up differential transistor; the drain of the first pull-down differential transistor and the drain of the first pull-up differential transistor are commonly connected to the first end of the first resistor, and the drain of the second pull-down differential transistor and the drain of the second pull-up differential transistor are commonly connected to the first end of the second resistor.
7. The multi-protocol IO multiplexing circuit of claim 6, wherein the pull-up transistor, the first pull-up differential transistor, and the second pull-up differential transistor are PMOS transistors, and the pull-down transistor, the first pull-down differential transistor, and the second pull-up differential transistor are NMOS transistors; or the pull-up transistor, the first pull-up differential transistor and the second pull-up differential transistor are NMOS transistors, and the pull-down transistor, the first pull-down differential transistor and the second pull-up differential transistor are PMOS transistors.
8. The multi-protocol IO multiplexing circuit of claim 6, wherein the output stage replica circuit comprises a first replica transistor, a second replica transistor, a third replica transistor, a fourth replica transistor, a first replica resistor, a second replica resistor, and a third replica resistor, the pull-up negative feedback loop comprises a pull-up amplifier, and the pull-down negative feedback loop comprises a pull-down amplifier; the source electrode of the first replica transistor is connected with the power supply, the grid electrode of the first replica transistor is connected with the output end of the pull-up amplifier, the drain electrode of the second replica transistor is connected with the source electrode of the second replica transistor, the grid electrode of the second replica transistor is grounded, the drain electrode of the second replica transistor is connected with the first end of the first replica resistor, the second end of the first replica resistor and the first end of the second replica resistor are commonly connected with the reverse input end of the pull-up amplifier, the forward input end of the pull-up amplifier is connected with the pull-up analog reference signal, the output end of the pull-up amplifier outputs a pull-up analog feedback signal to the first replica transistor, the second end of the second replica resistor and the first end of the third replica resistor are commonly connected with the forward input end of the pull-down amplifier, the reverse input end of the pull-down amplifier is connected with the pull-down analog reference signal, the output end of the second replica resistor is commonly connected with the drain electrode of the third replica transistor, the grid electrode of the third replica transistor is connected with the fourth replica transistor, and the drain electrode of the fourth replica transistor is connected with the drain electrode of the fourth replica transistor.
9. The multi-protocol IO multiplexing circuit of claim 8, wherein the first replica transistor equally replicates the pull-up transistor, the first replica resistor equally replicates the first resistor, the second replica transistor equally replicates the second resistor, and the fourth replica transistor equally replicates the pull-down transistor.
10. The multi-protocol IO multiplexing circuit of claim 6, wherein the mode control module comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first mode selector, and a second mode selector, wherein an input of the first inverter is connected to the first input, an output of the first inverter is connected to the first select input of the first mode selector, an input of the second inverter is connected to the second input, an output of the second inverter is connected to the first select input of the second mode selector, an input of the third inverter is connected to the third input, an output of the fourth inverter is connected to the input of the fourth inverter, and an output of the fourth inverter is connected to the second select input of the second mode selector; the second selection input end of the first mode selector is connected with the output end of the third phase inverter, the control end and the control end of the second mode selector are connected to the control input end together, the output end is connected with the first output end, and the output end of the second mode selector is connected with the second output end.
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| CN116561035B (en) * | 2023-07-07 | 2023-10-31 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
| CN117097326B (en) * | 2023-10-19 | 2023-12-22 | 四川艾瑞维尔科技有限公司 | Driving circuit compatible with LVDS and HCSL level standards |
| CN117831590B (en) * | 2024-01-04 | 2024-05-28 | 上海奎芯集成电路设计有限公司 | Multi-mode memory driving circuit and multi-protocol interface compatible PHY chip |
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