CN101267201B - Level regulator - Google Patents
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- CN101267201B CN101267201B CN2008100991691A CN200810099169A CN101267201B CN 101267201 B CN101267201 B CN 101267201B CN 2008100991691 A CN2008100991691 A CN 2008100991691A CN 200810099169 A CN200810099169 A CN 200810099169A CN 101267201 B CN101267201 B CN 101267201B
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Abstract
A level adjuster comprise the following components: a first inverter which is supplied with power by a first voltage and is provided an input end for receiving an input signal and an output end for outputting an inverse phase signal, wherein the level of the input signal is between a second voltage and an earth voltage; a difference amplifying unit which is supplied with power by an input/output electric power voltage higher than the first voltage and is used for generating a corresponding logic signal on a first output node according to the input signal; a second inverter which is supplied with power by an input/output electric power voltage and is provided with an input end coupled to the first output node and is used for generating an output signal; and a pressure releasing unit which is coupled to an electric power end of the first inverter and is used for generating a first voltage according to the input/output electric power voltage.
Description
Technical field
The present invention relates to the level adjustment technology, particularly relate to a kind of level adjuster of being ready for the misoperation that asynchronism(-nization) causes of avoiding supply voltage.
Background technology
At present novel system circuit board can be in order to receive core power supply voltage (for example 1.0V) in order to supply power to a core circuit of an integrated circuit, and can receive an I/O (I/O) supply voltage (for example 3.3V) in order to supply power to multiple driver, for example input buffer of an integrated circuit or output buffer ... or the like.In the system circuit board of power supply more than this kind (multi-power); level adjuster (level shifter) can be powered by core power supply voltage and I/O supply voltage usually, is adjusted to the signal with I/O supply voltage in order to the signal that will have core power supply voltage.
Yet, in the system of this many power supplys, when I/O (I/O) supply voltage is ready for (ready) and core power supply voltage when not being ready for as yet, will make the output signal of level adjuster be in the state an of the unknown, and this situation may cause subsequent conditioning circuit to burn or produce the misoperation of non-response infringement.
Summary of the invention
The invention provides a kind of level adjuster, comprise one first inverter, powered, and have an input and receive an input signal by one first voltage, and one output in order to export an inversion signal, wherein the level of input signal is between one second voltage and an earthed voltage; One differential motion amplifying unit, powered by an I/O supply voltage, and has a first input end and one second input is coupled to input signal and inversion signal respectively, in order to produce a corresponding logical signal according to input signal on one first output node, wherein first voltage is lower than the I/O supply voltage; One second inverter is powered by the I/O supply voltage, and has an input and be coupled to first output node, in order to produce an output signal; And a pressure unit, be coupled between the power end of the I/O supply voltage and first inverter, in order to produce first voltage according to the I/O supply voltage.
The present invention also provides a kind of level adjuster, comprises a pressure unit, and in order to convert an I/O supply voltage to one first voltage, wherein the I/O supply voltage is greater than above-mentioned first voltage; One the first transistor has that one first end is coupled to first voltage and a control end couples an input signal; One transistor seconds has second end, the control end that one first end is coupled to the first transistor and couples input signal, and one second end is coupled to one second voltage, and wherein first voltage is greater than second voltage; One the 3rd transistor has that one first end is coupled to one first output node, a control end is coupled to first, second transistorized control end, and one second end is coupled to second voltage; One the 4th transistor has that one first end is coupled to one second output node, a control end is coupled to input signal, and one second end is coupled to second voltage; One the 5th transistor has that one first end is coupled to the I/O supply voltage, a control end is coupled to second output node, and one second end is coupled to first output node; And one the 6th transistor, have that one first end is coupled to the I/O supply voltage, a control end is coupled to first output node, and one second end is coupled to second output node.
The present invention also provides a kind of level adjuster, comprises a pressure unit, and in order to convert an I/O supply voltage to one first voltage, wherein the I/O supply voltage is greater than above-mentioned first voltage; One the first transistor has that one first end is coupled to first voltage and a control end couples an input signal; One transistor seconds has second end, the control end that one first end is coupled to the first transistor and couples input signal, and one second end is coupled to one second voltage, and wherein first voltage is greater than above-mentioned second voltage; One the 3rd transistor has that one first end is coupled to one first output node, a control end is coupled to first, second transistorized control end, and one second end is coupled to second voltage; One the 4th transistor has that one first end is coupled to one second output node, one second end is coupled to second voltage, and a control end; One the 5th transistor has that one first end is coupled to the I/O supply voltage, a control end is coupled to second output node, and one second end is coupled to first output node; One the 6th transistor has that one first end is coupled to the I/O supply voltage, a control end is coupled to first output node, and one second end is coupled to second output node; One the 7th transistor has that one first end couples first voltage, a control end couples the 3rd transistorized control end, and one second end is coupled to the 4th transistorized control end; And one the 8th transistor, have that one first end couples the 4th transistorized control end, a control end couples the 3rd transistorized control end, and one second end is coupled to second voltage.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows an embodiment of a level adjuster.
Fig. 2 shows another embodiment of a level adjuster.
Fig. 3 shows another embodiment of a level adjuster.
Fig. 4 shows another embodiment of a level adjuster.
Fig. 5 shows another embodiment of a level adjuster.
Fig. 6 shows another embodiment of a level adjuster.
The reference numeral explanation
10: pressure unit; 20: differential motion amplifying unit;
100A-100F: level adjuster; LH: latch units;
DF: differential right; INV1-INV3: inverter;
M00-M10, M00A, M00B: transistor;
D1-DN: diode; ON1, ON2: node;
GNDH: earthed voltage; VDDL ": voltage;
VDDH: I/O supply voltage;
SIN: input signal; SIN ": inversion signal;
SOUT: output signal.
Embodiment
Fig. 1 shows a schematic diagram of a level adjuster.As shown in the figure, level adjuster 100A is powered by an I/O supply voltage VDDH (for example 5.0V), and comprises a pressure unit 10, a differential motion amplifying unit 20 and inverter INV1 and INV2.
Inverter INV1 is in order to receiving an input signal SIN, and produces an inversion signal SIN ".In this embodiment, input signal SIN is the signal with core power supply voltage level, and the core power supply voltage level is lower than the level of I/O supply voltage VDDH.For example, the level of input signal SIN but is not limited thereto between 3.3V and 0V.Inverter INV1 comprises transistor M01 and M02.Transistor M01 has one first end and is coupled to voltage VDDL ", a control end is coupled to input signal SIN and one second end is coupled to transistor M02.Transistor M02 has that second end, a control end that one first end is coupled to transistor M01 are coupled to input signal SIN and one second end is coupled to earthed voltage GNDH.For example, earthed voltage GNDH is 0V, but is not limited to this.
Differential motion amplifying unit 20 comprises that one is differential to a DF and a latch units LH.Differential DF is comprised transistor M03 and M04, and transistor M03 has, and one first end couples node ON1, a control end couples inversion signal SIN " and one second end couple earthed voltage GNDH, transistor M04 has that one first end couples node ON2, a control end couples input signal SIN and one second end couples earthed voltage GNDH.Latch units LH comprises cross-coupled (cross-coupled) transistor M05 and M06.For example, transistor M05 has that one first end is coupled to I/O supply voltage VDDH, a control end is coupled to node ON2 and one second end is coupled to node ON1, and one first end is coupled to I/O supply voltage VDDH, a control end is coupled to node ON1 and one second end is coupled to node ON2 and transistor M06 has.
Inverter INV2 produces an output signal SOUT in order to according to the logic state on the node ON2.Inverter INV2 comprises transistor M07 and M08.Transistor M07 has that one first end is coupled to I/O supply voltage VDDH, a control end is coupled to node ON2 and one second end is coupled to transistor M08.Transistor M08 has that second end, a control end that one first end is coupled to transistor M07 are coupled to node ON2 and one second end is coupled to earthed voltage GNDH.
The action specification of level adjuster 100A is as follows.When the core power supply voltage (for example 3.3V) of I/O supply voltage VDDH (for example 5.0V) and input signal SIN when all being ready for (ready), if input signal SIN is LOW (being 0V), inversion signal SIN then " become voltage VDDL " (being 3.3V), so transistor M03 can conducting and transistor M04 ends.Therefore, the current potential on the node ON1 can be pulled low to earthed voltage GNDH, so transistor M06 can conducting draw high the current potential on the node ON2 to I/O supply voltage VDDH.Because the current potential on the node ON2 is I/O supply voltage VDDH, transistor M07 can end and transistor M08 meeting conducting, is the output signal SOUT of LOW so that produce logic level.
Anti-speech if input signal SIN is HIGH (being 3.3V), then inversion signal SIN " become earthed voltage GNDH (being 0V), transistor M03 ends so transistor M04 understands conducting.Therefore, the current potential on the node ON2 can be pulled low to earthed voltage GNDH, so transistor M05 can conducting draw high the current potential on the node ON1 to I/O supply voltage VDDH.Because the current potential on the node ON2 is earthed voltage GNDH, transistor M08 can end and transistor M07 meeting conducting, is the output signal SOUT of HIGH so that produce logic level.Generally speaking, when the input signal SIN with core power supply voltage level is LOW, output signal SOUT is earthed voltage GNDH (being LOW), and when the input signal SIN with core power supply voltage level was HIGH, output signal SOUT was I/O supply voltage VDDH (being HIGH).
Be noted that voltage VDDL " be to be limited to when the level of input signal SIN is HIGH (for example 3.3V), transistor M01 can end and have only transistor M02, to avoid leakage current generating.
If be ready for the core power supply voltage (for example 3.3V) of (ready) and input signal SIN when not being ready for as yet at I/O supply voltage VDDH (for example 5.0V), because the voltage VDDL on the power end (being first end of transistor M01) of inverter INV1 " be to form by I/O supply voltage VDDH (for example 5.0V) step-down; so if input signal SIN this moment is LOW (being 0V); inversion signal SIN then " become voltage VDDL " (being 3.3V), so transistor M03 can conducting and transistor M04 ends.Therefore, current potential on the node ON1 can be pulled low to earthed voltage GNDH, so transistor M06 can conducting draw high the current potential on the node ON2 to I/O supply voltage VDDH, transistor M07 can end and transistor M08 meeting conducting, is the output signal SOUT of LOW so that produce logic level.In other words, even be ready for (ready) and core power supply voltage (for example 3.3V) when not being ready for as yet at I/O supply voltage VDDH (for example 5.0V), the logic level of output signal SOUT can maintain the state of LOW, but not the state an of the unknown.
Therefore, the level adjuster 100A in the present embodiment can avoid subsequent conditioning circuit since I/O supply voltage VDDH (for example 5.0V) be ready for (ready) and core power supply voltage (for example 3.3V) when not being ready for as yet the unknown state of output signal produce the misoperation of non-response infringement.
Figure 2 shows that another embodiment of level adjuster of the present invention.As shown in the figure, level adjuster 100B is similar to the level adjuster 100A shown in Fig. 1, and its difference is that pressure unit 10 is to be realized so that I/O supply voltage VDDH is reduced to voltage VDDL by diode D1 ".Diode D1 has an anode, and it couples I/O supply voltage VDDH, and a negative electrode, and it is coupled to first end of transistor M01.The action of level adjuster 100B is identical with level adjuster 100A, does not state tired in this.Be noted that voltage VDDL " be limited to when the level of input signal SIN is HIGH (for example 3.3V), transistor M01 can end and have only transistor M02, to avoid leakage current generating.
Figure 3 shows that another embodiment of level adjuster of the present invention.As shown in the figure, level adjuster 100C is similar to the level adjuster 100A shown in Fig. 1, and its difference is that pressure unit 10 is that diode D2-DN by a plurality of serial connections realizes so that I/O supply voltage VDDH is reduced to voltage VDDL ".The anode of diode D2 couples I/O supply voltage VDDH, and the negative electrode of diode DN is coupled to first end of transistor M01.In an embodiment, I/O supply voltage VDDH can be 12V, and the core power supply voltage level of input signal SIN can be 3.3V, and voltage VDDL " can be about 3.3V.The action of level adjuster 100C is identical with level adjuster 100A, does not state tired in this.Be noted that voltage VDDL " be limited to when the level of input signal SIN is HIGH (for example 3.3V), transistor M01 can end and have only transistor M02, to avoid leakage current generating.
Figure 4 shows that another embodiment of level adjuster of the present invention.As shown in the figure, level adjuster 100D is similar to the level adjuster 100A shown in Fig. 1, its difference is that pressure unit 10 is to be realized by the MOS transistor that a diode mode connects, so that I/O supply voltage VDDH is reduced to voltage VDDL ".Transistor M00 has that one first end is coupled to I/O supply voltage VDDH, a control end also is coupled to I/O supply voltage VDDH, and one second end is coupled to first end of transistor M01.The action of level adjuster 100D is identical with level adjuster 100A, does not state tired in this.Be noted that voltage VDDL " be limited to when the level of input signal SIN is HIGH (for example 3.3V), transistor M01 can end and have only transistor M02, to avoid leakage current generating.
Figure 5 shows that another embodiment of level adjuster of the present invention.As shown in the figure, level adjuster 100E is similar to the level adjuster 100D shown in Fig. 4, its difference is that pressure unit 10 is to be formed by the MOS transistor of a plurality of diode types of attachment serial connection, in order to I/O supply voltage VDDH is reduced to voltage VDDL ".In an embodiment, I/O supply voltage VDDH can be 12V, and the core power supply voltage level of input signal SIN can be 3.3V, and voltage VDDL " can be about 3.3V.The action of level adjuster 100E is identical with level adjuster 100A, does not state tired in this.
Figure 6 shows that another embodiment of level adjuster of the present invention.As shown in the figure, level adjuster 100F is similar to the level adjuster 100D shown in Fig. 4, its difference is that an inverter INV3 is coupled between the control end of the output of inverter INV1 and transistor M04, and the power end of inverter INV3 also is coupled to voltage VDDL ".Inverter INV3 comprises transistor M09 and M10, and transistor M09 has one first end (as power end) and is coupled to voltage VDDL ", a control end is coupled to the control end of transistor M03, and one second end is coupled to the control end of transistor M04.Transistor M10 has that one first end is coupled to the control end of transistor M04, control end and one second end that a control end is coupled to transistor M03 is coupled to earthed voltage GNDH.In other words, the control end of transistor M03 and M04 is coupled to the output of inverter INV1 and INV3 respectively.Inversion signal SIN " be the inversion signal of input signal SIN, and signal on the control end of transistor M04 and input signal homophase.
When the core power supply voltage (for example 3.3V) of I/O supply voltage VDDH (for example 5.0V) and input signal SIN when all being ready for (ready), if input signal SIN is LOW (being 0V), inversion signal SIN then " become voltage VDDL " (being 3.3V), so transistor M03 meeting conducting, and transistor M04 can be owing to transistor M10 conducting is cut off.Therefore, the current potential on the node ON1 can be pulled low to earthed voltage GNDH, so transistor M06 can conducting draw high the current potential on the node ON2 to I/O supply voltage VDDH.Because the current potential on the node ON2 is I/O supply voltage VDDH, transistor M07 can end and transistor M08 meeting conducting, is the output signal SOUT of LOW so that produce logic level.
Anti-speech if input signal SIN is HIGH (being 3.3V), then inversion signal SIN " become earthed voltage GNDH (being 0V), so transistor M03 can end, and transistor M04 understands and be switched on because of transistor M09 conducting.Therefore, the current potential on the node ON2 can be pulled low to earthed voltage GNDH, so transistor M05 can conducting draw high the current potential on the node ON1 to I/O supply voltage VDDH.Because the current potential on the node ON2 is earthed voltage GNDH, transistor M08 can end and transistor M07 meeting conducting, is the output signal SOUT of HIGH so that produce logic level.Generally speaking, when the input signal SIN with core power supply voltage level is LOW, output signal SOUT is earthed voltage GNDH (being LOW), and when the input signal SIN with core power supply voltage level was HIGH, output signal SOUT was I/O supply voltage VDDH (being HIGH).
If be ready for the core power supply voltage (for example 3.3V) of (ready) and input signal SIN when not being ready for as yet at I/O supply voltage VDDH (for example 5.0V), because the voltage VDDL on the power end (being first end of transistor M01) of inverter INV1 " be to form by I/O supply voltage VDDH (for example 5.0V) step-down; so if input signal SIN this moment is LOW (being 0V); inversion signal SIN then " become voltage VDDL " (being 3.3V); so transistor M03 can conducting, and transistor M04 can be owing to transistor M10 conducting is cut off.Therefore, current potential on the node ON1 can be pulled low to earthed voltage GNDH, so transistor M06 can conducting draw high the current potential on the node ON2 to I/O supply voltage VDDH, transistor M07 can end and transistor M08 meeting conducting, is the output signal SOUT of LOW so that produce logic level.In other words, even be ready for (ready) and core power supply voltage (for example 3.3V) when not being ready for as yet at I/O supply voltage VDDH (for example 5.0V), the logic level of output signal SOUT can maintain the state of LOW, but not the state an of the unknown.
Be noted that voltage VDDL " be to be limited to when the level of input signal SIN is HIGH (for example 3.3V), transistor M01 can end and have only transistor M02, to avoid leakage current generating.Because the power end of inverter INV1 and INV3 (first end that is transistor M01 and M09 all is coupled to voltage VDDL "); so the highest voltage level on the control end of transistor M03 and M04 all can be voltage VDDL ", have for 50% to 50% work period (duty cycle) so can guarantee level adjuster 100E.
Therefore, in the power initiation process or in the battery saving mode, when higher operating voltage (being I/O supply voltage VDDH) has been ready for and lower operating voltage (being core power supply voltage) when not being ready for as yet, the logic output level of level adjuster is controllable, but not is in the condition attitude an of the unknown.In other words, the power initiation leakage current that is caused owing to power supply sequence problem (power sequence issue) in multi-power system can be eliminated.In addition, level adjuster of the present invention only needs a kind of supply voltage and does not need two kinds of supply voltages, and this will alleviate the circuit arrangement degree of difficulty of level adjuster, and reduces the required coiling area of power supply signal line.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (19)
1. level adjuster comprises:
One first inverter, powered by one first voltage, and have an input and receive an input signal, and an output is in order to export an inversion signal, wherein the level of above-mentioned input signal is between one second voltage and an earthed voltage, and above-mentioned second voltage is higher than above-mentioned earthed voltage;
One differential motion amplifying unit, powered by an I/O supply voltage, and have a first input end and one second input, in order to produce a corresponding logical signal according to above-mentioned input signal on one first output node, wherein above-mentioned first voltage is lower than above-mentioned I/O supply voltage;
One second inverter is powered by above-mentioned I/O supply voltage, and has an input and be coupled to above-mentioned first output node, in order to produce an output signal; And
One pressure unit is coupled between the power end of above-mentioned I/O supply voltage and above-mentioned first inverter, in order to produce above-mentioned first voltage according to above-mentioned I/O supply voltage.
2. level adjuster as claimed in claim 1, wherein above-mentioned first inverter comprises:
One the first transistor has first input end, the control end that one first end is coupled to above-mentioned differential motion amplifying unit and is coupled to above-mentioned input signal, and one second end as above-mentioned power end in order to be coupled to above-mentioned first voltage; And
One transistor seconds has above-mentioned first input end, the control end that one first end is coupled to above-mentioned differential motion amplifying unit and be coupled to above-mentioned input signal, and one second end is coupled to above-mentioned earthed voltage.
3. level adjuster as claimed in claim 2, wherein when the level of above-mentioned input signal was above-mentioned second voltage, the voltage difference of above-mentioned first voltage and above-mentioned second voltage can make above-mentioned the first transistor end.
4. level adjuster as claimed in claim 1, wherein the first input end of above-mentioned differential motion amplifying unit and second input are coupled to the input and the output of above-mentioned first inverter respectively.
5. level adjuster as claimed in claim 1, comprise that also one the 3rd inverter is powered by above-mentioned first voltage, and has an output that an input couples above-mentioned first inverter, and one output be coupled to the first input end of above-mentioned differential motion amplifying unit, the output of wherein above-mentioned first inverter is coupled to second input of above-mentioned differential motion amplifying unit.
6. level adjuster as claimed in claim 1, wherein above-mentioned pressure unit comprise that at least one diode is coupled between the above-mentioned power end of above-mentioned I/O supply voltage and above-mentioned first inverter.
7. level adjuster as claimed in claim 1, wherein above-mentioned pressure unit comprise that a first transistor has one first end and couples above-mentioned I/O supply voltage, a control end and couple the above-mentioned power end that above-mentioned I/O supply voltage and one second end couple above-mentioned first inverter.
8. level adjuster as claimed in claim 1, wherein above-mentioned differential motion amplifying unit comprises:
One latch units is coupled between above-mentioned I/O supply voltage and above-mentioned first output node; And
One is differential right, is coupled between an above-mentioned latch units and the earthed voltage, and couples the output and the above-mentioned input signal of above-mentioned first inverter.
9. level adjuster as claimed in claim 8, wherein above-mentioned latch units comprises:
One the first transistor, have one first end be coupled to above-mentioned I/O supply voltage, a control end be coupled to above-mentioned second output node and one second end be coupled to above-mentioned differential right; And
One transistor seconds, have one first end be coupled to above-mentioned I/O supply voltage, a control end be coupled to one first output node and one second end be coupled to above-mentioned differential right.
10. level adjuster as claimed in claim 8, wherein above-mentioned differential to comprising:
One the first transistor has that one first end is coupled to one second output node, one second end is coupled to above-mentioned earthed voltage, and a control end is as second input of above-mentioned differential motion amplifying unit and be coupled to the output of above-mentioned first inverter; And
One transistor seconds has that one first end is coupled to above-mentioned first output node, one second end is coupled to above-mentioned earthed voltage, and a control end is as the first input end of above-mentioned differential motion amplifying unit.
11. a level adjuster comprises:
One pressure unit, in order to convert an I/O supply voltage to one first voltage, wherein above-mentioned I/O supply voltage is greater than above-mentioned first voltage;
One the first transistor has that one first end is coupled to above-mentioned first voltage, a control end couples an input signal, and one second end;
One transistor seconds has second end, the control end that one first end is coupled to above-mentioned the first transistor and couples above-mentioned input signal, and one second end is coupled to one second voltage, and wherein above-mentioned first voltage is greater than above-mentioned second voltage;
One the 3rd transistor has that one first end is coupled to one first output node, one second end is coupled to above-mentioned second voltage, and a control end is coupled to second end of above-mentioned the first transistor and first end of above-mentioned transistor seconds;
One the 4th transistor has that one first end is coupled to one second output node, a control end is coupled to above-mentioned input signal, and one second end is coupled to above-mentioned second voltage;
One the 5th transistor has that one first end is coupled to above-mentioned I/O supply voltage, a control end is coupled to above-mentioned second output node, and one second end is coupled to above-mentioned first output node; And
One the 6th transistor has that one first end is coupled to above-mentioned I/O supply voltage, a control end is coupled to above-mentioned first output node, and one second end is coupled to above-mentioned second output node.
12. level adjuster as claimed in claim 11, wherein the level of above-mentioned input signal is between a tertiary voltage and above-mentioned second voltage, and above-mentioned tertiary voltage is greater than above-mentioned second voltage, when the level of above-mentioned input signal was above-mentioned tertiary voltage, the voltage difference of above-mentioned first voltage and above-mentioned tertiary voltage can make above-mentioned the first transistor end.
13. level adjuster as claimed in claim 12 also comprises:
One the 7th transistor has that one first end couples above-mentioned I/O supply voltage, a control end couples above-mentioned second output node, and one second end;
One the 8th transistor has one first end coupling the above-mentioned the 7th transistorized second end, a control end couples above-mentioned second output node, and one second end is coupled to above-mentioned second voltage.
14. level adjuster as claimed in claim 13, wherein above-mentioned pressure unit comprise that a diode has an anode and couples first end that above-mentioned I/O supply voltage and a negative electrode couple above-mentioned the first transistor.
15. level adjuster as claimed in claim 13, wherein above-mentioned pressure unit comprise that a plurality of diodes in series are coupled between first end of above-mentioned I/O supply voltage and above-mentioned the first transistor.
16. level adjuster as claimed in claim 13, wherein above-mentioned pressure unit comprise that one the 9th transistor has one first end and couples above-mentioned I/O supply voltage, a control end and couple first end that above-mentioned I/O supply voltage and one second end couple above-mentioned the first transistor.
17. level adjuster as claimed in claim 13, wherein above-mentioned pressure unit comprises:
One the 9th transistor has that one first end couples above-mentioned first voltage, a control end couples the above-mentioned the 3rd transistorized control end, and one second end; And
The tenth transistor has that one first end couples the above-mentioned the 9th transistorized second end, a control end couples the 3rd transistorized control end, and one second end couples above-mentioned second voltage.
18. a level adjuster comprises:
One pressure unit, in order to convert an I/O supply voltage to one first voltage, wherein above-mentioned I/O supply voltage is greater than above-mentioned first voltage;
One the first transistor has that one first end is coupled to above-mentioned first voltage, a control end couples an input signal, and one second end;
One transistor seconds has second end, the control end that one first end is coupled to above-mentioned the first transistor and couples above-mentioned input signal, and one second end is coupled to one second voltage, and wherein above-mentioned first voltage is greater than above-mentioned second voltage;
One the 3rd transistor has that one first end is coupled to one first output node, one second end is coupled to above-mentioned second voltage, and a control end is coupled to second end of above-mentioned the first transistor and first end of above-mentioned transistor seconds;
One the 4th transistor has that one first end is coupled to one second output node, one second end is coupled to above-mentioned second voltage, and a control end is coupled to above-mentioned input signal;
One the 5th transistor has that one first end is coupled to above-mentioned I/O supply voltage, a control end is coupled to above-mentioned second output node, and one second end is coupled to above-mentioned first output node;
One the 6th transistor has that one first end is coupled to above-mentioned I/O supply voltage, a control end is coupled to above-mentioned first output node, and one second end is coupled to above-mentioned second output node;
One the 7th transistor has that one first end couples above-mentioned first voltage, a control end couples the above-mentioned the 3rd transistorized control end, and one second end is coupled to the above-mentioned the 4th transistorized control end; And
One the 8th transistor has that one first end couples the above-mentioned the 4th transistorized control end, a control end couples the above-mentioned the 3rd transistorized control end, and one second end is coupled to above-mentioned second voltage.
19. level adjuster as claimed in claim 18 also comprises:
One the 9th transistor has that one first end couples above-mentioned I/O supply voltage, a control end couples above-mentioned second output node, and one second end;
The tenth transistor has one first end coupling the above-mentioned the 9th transistorized second end, a control end couples above-mentioned second output node, and one second end is coupled to above-mentioned second voltage.
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| CN2008100991691A CN101267201B (en) | 2008-05-14 | 2008-05-14 | Level regulator |
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| CN2008100991691A CN101267201B (en) | 2008-05-14 | 2008-05-14 | Level regulator |
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| CN101267201A CN101267201A (en) | 2008-09-17 |
| CN101267201B true CN101267201B (en) | 2010-06-02 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099437B (en) * | 2014-05-16 | 2018-07-24 | 华邦电子股份有限公司 | Logic circuit |
| CN104714320B (en) * | 2015-03-30 | 2017-09-19 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN106899288B (en) * | 2017-02-21 | 2020-05-22 | 珠海市杰理科技股份有限公司 | Level conversion circuit |
| CN110445479A (en) * | 2019-08-26 | 2019-11-12 | 无锡天极芯科技有限公司 | It is a kind of for stablizing the circuit of buzzer driving tube grid voltage |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760606A (en) * | 1995-04-17 | 1998-06-02 | Matsushita Electric Industrial, Co. | High voltage withstanding circuit and voltage level shifter |
| CN1293488A (en) * | 1999-10-15 | 2001-05-02 | 威盛电子股份有限公司 | Single-terminal input voltage level converter controlled by grid voltage |
-
2008
- 2008-05-14 CN CN2008100991691A patent/CN101267201B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760606A (en) * | 1995-04-17 | 1998-06-02 | Matsushita Electric Industrial, Co. | High voltage withstanding circuit and voltage level shifter |
| CN1293488A (en) * | 1999-10-15 | 2001-05-02 | 威盛电子股份有限公司 | Single-terminal input voltage level converter controlled by grid voltage |
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| CN101267201A (en) | 2008-09-17 |
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