1359340 九、發明說明： 【發明所屬之技術領域】 本發明有關於準位調整技術，特別係士 系有關於一種可避 免電源電壓之備妥時間不同所造成之誤^ & <戎動作的準位調整 【先前技術】 目前新型的系統電路板係可用以挺,ΙΑ_ Α Α楼收核心電源電壓 (例如1.0V)用以供電至一積體電路之—奸 核心電路，並可接 收一輸入/輸出（I/O)電源電壓（例如3 v)用以供電至多種 驅動器，例如一積體電路之輸入緩衝哭洗认 Λ 出緩衝器…等 等。在此種多電源（multi-power)之系統雷 电踢^反中，準位'^周 整器（level shifter)通常會由核心電源電懕 °° % η 电爱與輪入/輸出電源 電壓所供電’用以將具有核心電源電壓 I之彳δ號調整成具有 輸入/輸出電源電壓之信號。 、’ 然而，在這種多電源之系統中，當蚣 田輸入/輸出（I/O)電源 電壓已備妥(ready)而核心電源電壓尚未備妥時， 準位調整H的輸出信號處於-未知⑽態，並且此情況將 可能導致後續電路燒毀或產生不可回復的_之誤動作。 【發明内容】 本發明係提供一種準位調整器，包括H相哭， 由-第-電壓所供電，並具有—輸，錢—輸入信號， 以及-輸出端用以輸出—反相信號，其中輪入信號的準位 VIT08-0002/0608-A41518-TW/Final 1359340 係於一第二電壓與一接地電壓之間；一差動放大單元，由 一輸入/輸出電源電壓所供電，並具有一第一、第二輸入端 分別耦接至輸入信號以及反相信號，用以根據輸入信號於 一第一輸出節點上產生一對應邏輯信號，其中第一電壓係 低於輸入/輸出電源電壓；一第二反相器，由輸入/輸出電源 電壓所供電，並具有一輸入端耦接至第一輸出節點，用以 產生一輸出信號；以及一降壓單元，耦接於輸入/輸出電源 電壓與第一反相器之一電源端之間，用以根據輸入/輸出電 源電壓產生第一電壓。 本發明亦提供一種準位調整器，包括一降壓單元，用 以將一輸入/輸出電源電壓轉換成一第一電壓，其中輸入/ 輸出電源電壓大於上述第一電壓；一第一電晶體，具有一 第一端耦接至第一電壓以及一控制端耦接一輸入信號；一 第二電晶體，具有一第一端耦接至第一電晶體之第二端、 一控制端耦接輸入信號，以及一第二端耦接至一第二電 壓，其中第一電壓大於第二電壓；一第三電晶體，具有一 第一端耦接至一第一輸出節點、一控制端耦接至第一、第 二電晶體之控制端，以及一第二端耦接至第二電壓；一第 四電晶體，具有一第一端耦接至一第二輸出節點、一控制 端耦接至輸入信號，以及一第二端耦接至第二電壓；一第 五電晶體，具有一第一端耦接至輸入/輸出電源電壓、一控 制端耦接至第二輸出節點，以及一第二端耦接至第一輸出 節點；以及一第六電晶體，具有一第一端耦接至輸入/輸出 電源電壓、一控制端耦接至第一輸出節點，以及一第二端 VIT08-0002/0608-A41518-TW/Final ^59340 耦接至第二輸出節點。 本發明亦提供-種準位調整器，… 以將-輸入/輸出電帽轉換成—/早:’用 輸出電源電屢大於上述第一電愿；中輸〜 第二電晶體，具有一第—_ = = =輸入信號；一 -控制端耦接輸入信號，以及一第二端：體之第二端、 其中第-電壓大於上述第二電壓-;—耦接日【二: -第第; :體接^ 第二端I:: 端輕接至-第二輸出節點、- 且有-第一：一電壓，以及一控制端；一第五電晶體， 第-輪接至輸入/輸出電源電壓、—控制端耦接至 即點’以及一第二辦至第-輸出節點一第 !j物妾至第-輸出節點，以及-第二端 即點，一第七電晶體，具有一第一端耦接第一 電曰制端，以及—第二端轉接至第四 二及一第八電晶體，具有-第，接 端，IT : 、一控制端麵接第三電晶體之控制 ^ 以及一第二端耦接至第二電壓。 明顯2讓本發明之上述和其他目的、特徵、和優點能更 詳細說=二例’並配合所附圖示，作 VIT〇8-〇〇〇2/〇6〇8-A41518-TW/Final 1359340 [實施方式】 第1圖係顯示一準位調整器之一示意圖。如圖所示， 準位調整器100A係由一輸入/輸出電源電壓VDDH(例如 5.0V)所供電，並且包括一降壓單元10、一差動放大單元 ' 20以及反相器INV1與INV2。 降壓單元10係用以將輸入/輸出電源電壓VDDH降低 成電壓VDDL”，用以作為反相器INV1之電源電壓。舉例 而言，降壓單元10係用以將輸入/輸出電源電壓VDDH降 φ 低成3.3V的電壓VDDL”，但不限定於此。 反相器INV1係用以接收一輸入信號SIN，並產生一反 相信號SIN”。在此實施例中，輸入信號SIN係為具有核心 - 電源電壓準位的信號，並且核心電源電壓準位低於輸入/ . 輸出電源電壓VDDH的準位。舉例而言，輸入信號SIN的 準位係位於3.3V與0V之間，但不限於此。反相器INV1 係包括電晶體M01與M02。電晶體M01係具有一第一端 耦接至電壓VDDL”、一控制端耦接至輸入信號SIN以及一 • 第二端耦接至電晶體M02。電晶體M02係具有一第一端麵 接至電晶體M01之第二端、一控制端耦接至輸入信號SIN 以及一第二端搞接至接地電壓GNDH。舉例而言，接地電 壓GNDH係為0V，但不限定於此。 差動放大單元20係包括一差動對DF以及一栓鎖單元 LH。差動對DF係包括電晶體M03與]V[〇4，並且電晶體 M03係具有一第一端耦接節點ON 1、一控制端耦接反相信 號SIN”以及一第二端耦接接地電壓GNDH,電晶體M04 VIT08-0002/0608-A41518-TW/Final 1359340 係具有一第一端耦接節點ON2、一控制端耦接輸入信號 SIN以及一第二端耦接接地電壓GNDH。栓鎖單元LH包 括交叉耦接的(cross-coupled)電晶體M05與M06。舉例而 言，電晶體M05具有一第一端耦接至輸入/輸出電源電壓 .VDDH、一控制端耦接至節點〇N2以及一第二端耦接至節 點0N1，而電晶體M06具有一第一端耦接至輸入/輸出電 源電壓VDDH、一控制端搞接至節點on 1以及一第二端輕 接至節點0N2。 # 反相器係用以根據節點〇n2上的邏輯狀態，產 生一輸出信號S0UT。反相器INV2係包括電晶體M〇7與 M08。電晶體M07係具有一第一端耦接至輸入/輸出電源電 壓VDDH、一控制端耦接至節點〇N2以及一第二端耦接至 .電晶體画。電晶體画係具有一第一端搞接至電晶體 M07之第一端、一控制端耦接至節點〇N2以及一第二端耦 接至接地電壓GNDH。 準位調整器100A之動作係說明如下。當輸入/輸出電 • 源電壓VDDH(例如5.0V)與輪入信號SIN之核心電源電壓 (例如3.3V)皆備妥(ready)時，若輸入信號SIN為L〇w(即 0V)，則反相信號SIN”係變為電壓VDDL，，（即3.3V)，所以 電晶體M03會導通而電晶體刚4截止。因此，節點⑽ 上的電位會被拉低至接地電壓GNDH，故電晶體M〇6會導 通將節點0N2上的電位杈高至輸入/輸出電源電壓 VDDH。由於節點0N2上的電位為輸入/輸出電源電壓 VDDH，電晶體M07會截止而電晶體M〇8會導通，以便產 VIT08-0002/0608-A41518-TW/Final 1359340 生邏輯準位為LOW的輸出信號SOUT。 反言之，若輸入信號SIN為HIGH(即3.3V)，則反相 信號SIN”係變為接地電壓GNDH(即0V)，所以電晶體M〇4 會導通而電晶體M03截止。因此，節點〇n2上的電位會 被拉低至接地電壓GNDH，故電晶體m〇5會導通將節點 ON 1上的電位拉高至輸入/輸出電源電壓VDDH。由於節點 ON2上的電位為接地電壓GNDH，電晶體m〇8會截止而電 晶體M07會導通，以便產生邏輯準位為HIGH的輸出信號 SOUT。總而言之，當具有核心電源電壓準位的輸入信號 SIN為LOW時，輸出信號SOUT為接地電壓GNDH(即 LOW)，而當具有核心電源電壓準位的輸入信號SIN為 HIGH時，輸出信號SOUT為輸入/輸出電源電壓VDDh(即 HIGH)。 要注意的是，電壓VDDL”係限制於當輸入信號sin之 準位為HIGH(例如3.3V)時，電晶體M〇1會截止而只有電 晶體M02，以避免漏電流產生。 如果在輸入/輸出電源電壓VDDH(例如5.0V)已備妥 (ready)而輸入信號SIN之核心電源電壓（例如3 3v)尚未備 妥時’由於反相器INV1之電源端（即電晶體M〇1之第一端） 上的電壓VDDL係由輸入/輸出電源電壓VDDH(例如5 降壓而成，所以若此時輸入信號SIN為LOW(即0V)，則 反相信號SIN”係變為電壓VDDL’，（即3.3v)，所以電晶體 M03會導通而電晶體M04截止。因此，節點〇N1上的電 位會被拉低至接地電壓GNDH，故電晶體M〇6會導通將節 VIT08-0002/0608-A41518-TW/Final 1359340 ON2上的電位拉咼至輸入/輸出電源電壓vddh，電晶 、- 〇7會截止而電晶體M08會導通，以便產生邏輯準位 為L〇W的輸出信號s〇UT。換言之，即使在輸入/輸出電 源電壓VDDH(例如5·0V)已備妥(ready)而核心電源電壓(例 如3.3V)尚未備妥時，輸出信號s〇ut的邏輯準位可以維 持在LOW的狀態，而非—個未知的狀態。1359340 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a level adjustment technique, and in particular, the system relates to an error caused by a difference in the preparation time of the power supply voltage. Level adjustment [Prior Art] At present, the new system board can be used to support the core power supply voltage (for example, 1.0V) to supply power to an integrated circuit and receive an input. The /output (I/O) supply voltage (for example, 3 v) is used to power a variety of drivers, such as the input buffer of an integrated circuit, the buffer, the buffer, and so on. In this multi-power system lightning strike, the level shifter is usually powered by the core power supply ° ° % η electric love and wheel / output power supply voltage The power supply 'is used to adjust the 彳δ number with the core supply voltage I to a signal having an input/output supply voltage. ' However, in this multi-power system, when the input/output (I/O) supply voltage of the Putian is ready and the core supply voltage is not ready, the output signal of the level adjustment H is - Unknown (10) state, and this situation may lead to subsequent circuit burnout or unsuccessful _ malfunction. SUMMARY OF THE INVENTION The present invention provides a level adjuster, including H phase crying, powered by a - first voltage, and having a - input, money - input signal, and - an output for outputting - an inverted signal, wherein The level of the wheeled signal VIT08-0002/0608-A41518-TW/Final 1359340 is between a second voltage and a ground voltage; a differential amplifying unit is powered by an input/output supply voltage and has a The first input and the second input are respectively coupled to the input signal and the inverted signal, for generating a corresponding logic signal on the first output node according to the input signal, wherein the first voltage is lower than the input/output power voltage; a second inverter, powered by an input/output supply voltage, having an input coupled to the first output node for generating an output signal; and a buck unit coupled to the input/output supply voltage and Between one of the power terminals of the first inverter, a first voltage is generated according to the input/output power voltage. The present invention also provides a level adjuster comprising a step-down unit for converting an input/output power supply voltage into a first voltage, wherein the input/output power supply voltage is greater than the first voltage; a first transistor having The first end is coupled to the first voltage and the control end is coupled to the input signal; the second transistor has a first end coupled to the second end of the first transistor, and a control end coupled to the input signal And a second end coupled to a second voltage, wherein the first voltage is greater than the second voltage; a third transistor having a first end coupled to a first output node and a control end coupled to the first a control terminal of the second transistor, and a second terminal coupled to the second voltage; a fourth transistor having a first end coupled to a second output node and a control terminal coupled to the input signal And a second end coupled to the second voltage; a fifth transistor having a first end coupled to the input/output supply voltage, a control end coupled to the second output node, and a second end coupling Connected to the first output node; The sixth transistor has a first end coupled to the input/output supply voltage, a control end coupled to the first output node, and a second end VIT08-0002/0608-A41518-TW/Final ^59340 coupled to The second output node. The invention also provides a kind of level adjuster, ... to convert the - input/output electric cap into - / early: 'the output power supply is repeatedly greater than the first electric wish; the middle input ~ the second transistor has a first -_ = = = input signal; a - control terminal coupled to the input signal, and a second terminal: the second end of the body, wherein the first voltage is greater than the second voltage -; - coupling day [2: - first ; : body connection ^ second end I:: end lightly connected to - second output node, - and - first: a voltage, and a control terminal; a fifth transistor, the first wheel is connected to the input / output The power supply voltage, the control terminal is coupled to the point and the second to the output node, the first to the output node, and the second terminal, the seventh transistor, having a The first end is coupled to the first electrical terminal, and the second end is coupled to the fourth and eighth transistors, having a - terminal, a terminal, IT: a control end surface connected to the third transistor The control ^ and a second end are coupled to the second voltage. It is obvious that the above and other objects, features, and advantages of the present invention can be described in more detail in the two examples, and in conjunction with the accompanying drawings, as VIT〇8-〇〇〇2/〇6〇8-A41518-TW/Final 1359340 [Embodiment] FIG. 1 is a schematic diagram showing one of the level adjusters. As shown, the level adjuster 100A is powered by an input/output supply voltage VDDH (e.g., 5.0V) and includes a buck unit 10, a differential amplifying unit '20, and inverters INV1 and INV2. The buck unit 10 is configured to reduce the input/output supply voltage VDDH to a voltage VDDL" as a power supply voltage of the inverter INV1. For example, the buck unit 10 is used to drop the input/output supply voltage VDDH. φ is reduced to a voltage of VDDL of 3.3 V, but is not limited thereto. The inverter INV1 is configured to receive an input signal SIN and generate an inverted signal SIN". In this embodiment, the input signal SIN is a signal having a core-supply voltage level, and the core power supply voltage level is low. For example, the level of the input signal SIN is between 3.3V and 0V, but is not limited thereto. The inverter INV1 includes transistors M01 and M02. The M01 has a first end coupled to the voltage VDDL", a control end coupled to the input signal SIN, and a second end coupled to the transistor M02. The transistor M02 has a first end connected to the second end of the transistor M01, a control end coupled to the input signal SIN and a second end coupled to the ground voltage GNDH. For example, the ground voltage GNDH is 0V, but is not limited thereto. The differential amplifying unit 20 includes a differential pair DF and a latch unit LH. The differential pair DF system includes transistors M03 and ]V[〇4, and the transistor M03 has a first terminal coupled to the node ON1, a control terminal coupled to the inverted signal SIN, and a second terminal coupled to the ground. The voltage GNDH, the transistor M04 VIT08-0002/0608-A41518-TW/Final 1359340 has a first end coupling node ON2, a control terminal coupled to the input signal SIN, and a second terminal coupled to the ground voltage GNDH. The unit LH includes cross-coupled transistors M05 and M06. For example, the transistor M05 has a first end coupled to the input/output supply voltage. VDDH and a control end coupled to the node 〇N2. The second terminal is coupled to the node 0N1, and the transistor M06 has a first end coupled to the input/output supply voltage VDDH, a control terminal coupled to the node on 1 and a second end coupled to the node ON2. The inverter is used to generate an output signal SOUT according to the logic state on the node 2n2. The inverter INV2 includes transistors M〇7 and M08. The transistor M07 has a first end coupled to the input/ The output power voltage VDDH, a control end coupled to the node 〇N2, and a second end coupled to the . The transistor has a first end connected to the first end of the transistor M07, a control end coupled to the node 〇N2, and a second end coupled to the ground voltage GNDH. The level adjuster 100A The operation is as follows. When the input/output power supply source voltage VDDH (for example, 5.0V) and the core power supply voltage (for example, 3.3V) of the turn-in signal SIN are ready, if the input signal SIN is L〇w (ie, 0V), the inverted signal SIN" becomes the voltage VDDL, (ie, 3.3V), so the transistor M03 is turned on and the transistor is just turned off. Therefore, the potential on node (10) is pulled low to ground GNDH, so transistor M〇6 turns on to raise the potential on node 0N2 to the input/output supply voltage VDDH. Since the potential on node 0N2 is the input/output supply voltage VDDH, transistor M07 will be turned off and transistor M〇8 will be turned on to produce VIT08-0002/0608-A41518-TW/Final 1359340 output with logic level LOW. Signal SOUT. Conversely, if the input signal SIN is HIGH (ie, 3.3V), the inverted signal SIN" becomes the ground voltage GNDH (ie, 0V), so the transistor M〇4 is turned on and the transistor M03 is turned off. The potential on 〇n2 will be pulled down to the ground voltage GNDH, so the transistor m〇5 will turn on and pull the potential on node ON 1 to the input/output supply voltage VDDH. Since the potential on node ON2 is the ground voltage GNDH, The transistor m〇8 will be turned off and the transistor M07 will be turned on to generate the output signal SOUT with the logic level HIGH. In summary, when the input signal SIN having the core supply voltage level is LOW, the output signal SOUT is the ground voltage GNDH. (ie LOW), and when the input signal SIN with the core supply voltage level is HIGH, the output signal SOUT is the input/output supply voltage VDDh (ie, HIGH). It should be noted that the voltage VDDL" is limited to the input signal. When the level of sin is HIGH (for example, 3.3V), the transistor M〇1 will be turned off and only the transistor M02 will be used to avoid leakage current. If the input/output supply voltage VDDH (for example, 5.0V) is ready and the core supply voltage of the input signal SIN (for example, 3 3v) is not ready, 'because the power supply terminal of the inverter INV1 (ie, the transistor M) The voltage VDDL on the first end of 〇1 is formed by the input/output supply voltage VDDH (for example, 5 step-down, so if the input signal SIN is LOW (ie, 0V), the inverted signal SIN" becomes The voltage VDDL', (ie 3.3v), so the transistor M03 will be turned on and the transistor M04 will be turned off. Therefore, the potential on the node 〇N1 will be pulled down to the ground voltage GNDH, so the transistor M〇6 will turn on the section VIT08 -0002/0608-A41518-TW/Final 1359340 The potential on ON2 is pulled to the input/output supply voltage vddh, the crystal, -7 will be turned off and the transistor M08 will be turned on to generate the logic level L〇W. Output signal s〇UT. In other words, even if the input/output supply voltage VDDH (for example, 5·0V) is ready and the core power supply voltage (for example, 3.3V) is not ready, the logic of the output signal s〇ut The bit can be maintained in the LOW state instead of the unknown state.
因此’本實施例中之準位調整器l〇〇A將可避免後續電 路由於輸入/輸出電源電壓VDDH(例如5 〇v)已備妥(ready) ，核％電源電壓(例如33V)尚未備妥時輸出信號的未知狀 態產產生不可回復的損害之誤動作。 第2圖所示係為本發明之準位調整器之另一實施例。 2所示’準位調整器1(K)B係與第i圖中所示之準位調 整器100A相似，其差異在於降壓單元1〇係由一二極體 D1來實現以便將輸入/輸出電源電壓vddh降低至電壓 ^DDL。一極體D1係具有一陽極係輕接輸入/輸出電源電 壓VDDH，以及-陰極輕接至電晶n M〇 j之第一端。準位 調整器100B之動作係與準位調整器1〇〇A相同，於此不在 累述。要注意的是，電壓VDDL”係限制於當輸入信號_ 之準位為mGH(例如3.3V)時，電晶體M〇1會截止而只有 電晶體M02，以避免漏電流產生。 第3圖所示係為本發明之準位調整器之另一實施例。 如圖所示，準位調整器係與第丨圖中所示之準位調 整器100A相似，其差異在於降壓單元1〇係由多個串接的 一極體D2〜DN來貫現以便將輸入/輸出電源電壓ν〇ϋΗ降 VIT08-0002/0608-A41518-TW/Final 12 ⑴ 9340 低至電麼VDDL，，。二極體D2之陪搞总4 & 12 V，而輸=ί例中’輸人/輪出電源電壓VDDH係可為 ^入“唬SIN之核心電源電壓準位 並且電壓VDDL”係可為 3-3V左右。準位調敕J為3.3V 作係與準位轉器丨相同，於=調f C之動 L，，係限制於當輸人信號_之準位為Therefore, the level adjuster l〇〇A in this embodiment will prevent the subsequent circuit from being ready due to the input/output supply voltage VDDH (for example, 5 〇v), and the core % power supply voltage (for example, 33V) has not been prepared. The unknown state of the output signal at the right time produces a malfunction that is unrecoverable damage. Figure 2 is a diagram showing another embodiment of the level adjuster of the present invention. The 'level adjuster 1 (K) B shown in Fig. 2 is similar to the level adjuster 100A shown in the figure i, except that the step-down unit 1 is implemented by a diode D1 to input/ The output supply voltage vddh is reduced to the voltage ^DDL. The one-pole D1 has an anode-based light input/output power supply voltage VDDH, and the cathode is lightly connected to the first end of the electric crystal n M〇 j . The operation of the level adjuster 100B is the same as that of the level adjuster 1A, and is not described here. It should be noted that the voltage VDDL" is limited to when the level of the input signal _ is mGH (for example, 3.3V), the transistor M〇1 is turned off and only the transistor M02 is used to avoid leakage current generation. The embodiment is another embodiment of the level adjuster of the present invention. As shown in the figure, the level adjuster is similar to the level adjuster 100A shown in the figure, and the difference is that the step-down unit 1 is It is realized by a plurality of serially connected ones D2 to DN to lower the input/output power supply voltage ν〇ϋΗVIT08-0002/0608-A41518-TW/Final 12 (1) 9340 to low power VDDL,. Body D2 is engaged in total 4 & 12 V, and in the case of input = 'input/round power supply voltage VDDH can be ^ 唬 SIN core power supply voltage level and voltage VDDL" can be 3- 3V or so. The level adjustment J is 3.3V and the same as the level converter ,, the adjustment of f C movement L, is limited to when the input signal _ the level is
'·3ν)時，電晶體M〇1會截止而曰n _2，以避免漏電流產生。 〃有電曰曰體 第4圖所示係為本發明之準位調整器之另一實施 2所示’準位調整器賺係與第！圖中所示之準位調 U 10GA相似，其差異在於降壓單元1()係由—個二極體 =式連接之MOS電晶體來實現，以便將輸入/輸出電源電 壓VDDH降低至電壓VDDL”。電晶體副〇係具有一第一 端耗接至輸入/輸出電源電M VDDH、一控制端亦搞接至輸 入/輸出，源電廛VDDH，以及一第二輪接至電晶體画 之第一端。準位調整器WOD之動作係與準位調整器1〇〇A 相同，於此不在累述。要注意的是，電壓VDDL，，係限制於 當輸入信號SIN之準位為HIGH(例如3·3ν)時，電晶體M01 會截止而只有電晶體M02，以避免漏電流產生。 第5圖所示係為本發明之準位調整器之另一實施例。 如圖所示’準位調整器100E係與第4圖中所示之準位調整 器100D相似’其差異在於降壓單元1〇係由多個二極體連 接形式的MOS電晶體串接而成，用以將輸入/輸出電源電 <s VIT08-0002/0608-A41518-TW/Final 13 1359340 壓VDDH降低至電壓Vddl，，。在實施例中，輸入/輸出電 ，電壓VDDH係可為12v，而輸入信號SIN之核心電源電 壓準位係可為3.3V，並且電壓VDDL”係可為3.3V左右。 準位調整器100E之動作係與準位調整器i〇〇A相同，於此 不在累述。 第6圖所示係為本發明之準位調整器之另一實施例。 如圖所示’準位調整器100F係與第4圖中所示之準位調整 器100D相似’其差異在於一反相器inv3耦接於反相器 INV1之輸出端與電晶體m〇4之控制端之間，並且反相器 INV3之一電源端亦耦接至電壓VDDL”。反相器INV3係 包括電晶體M09與M10，電晶體M09係具有一第一端(作 為電源端）耦接至電壓VDDL”、一控制端耦接至電晶體M03 之控制端，以及一第二端耦接至電晶體M04之控制端。電 晶體M10係具有一第一端耦接至電晶體M04之控制端、 一控制端耦接至電晶體M03之控制端以及一第二端耦接至 接地電壓GNDH。換言之，電晶體M03與M04之控制端 係分別耦接至反相器INV1與INV3之輸出端。反相信號 SIN”係為輸入信號SIN之反相信號，而電晶體]VI04之控制 端上的信號係與輪入信號同相。 當輸入/輸出電源電壓VDDH(例如5.0V)與輸入信號 SIN之核心電源電壓（例如3.3V)皆備妥(ready)時，若輸入 信號SIN為LOW(即0V)，則反相信號SIN”係變為電壓 VDDL”（即3.3V)’所以電晶體M03會導通，而電晶體M〇4 會由於電晶體Ml0導通而被截止。因此，節點ON1上的 <.s VIT08-0002/0608-A41518-TW/Final 14 1359340 電位會被拉低至接地電壓GNDH，故電晶體M06會導通將 節點ON2上的電位拉高至輸入/輸出電源電壓VDDH。由 於節點ON2上的電位為輸入/輸出電源電壓VDDH，電晶 體M07會截止而電晶體m〇8會導通，以便產生邏輯準位 為LOW的輸出信號SOUT。 反言之’若輸入信號SIN為HIGH(即3.3V)，則反相 信號SIN”係變為接地電壓GNDH(即0V)，所以電晶體M03 會截止，而電晶體M04會因為電晶體M09導通而被導通。 因此’節點ON2上的電位會被拉低至接地電壓GNDH，故 電晶體M05會導通將節點ON1上的電位拉高至輸入/輸出 電源電壓VDDH。由於節點ON2上的電位為接地電壓 GNDH，電晶體M08會截止而電晶體M07會導通，以便產 生邏輯準位為HIGH的輸出信號SOUT。總而言之，當具 有核心電源電壓準位的輸入信號SIN為LOW時，輸出信 號SOUT為接地電壓GNDH(即LOW)，而當具有核心電源 電壓準位的輸入信號SIN為HIGH時，輸出信號SOUT為 輸入/輸出電源電壓VDDH(即HIGH)。 如果在輸入/輸出電源電壓VDDH(例如5.0V)已備妥 (ready)而輸入信號SIN之核心電源電壓（例如3.3V)尚未備 妥時，由於反相器INV1之電源端（即電晶體M01之第一端） 上的電壓VDDL”係由輸入/輸出電源電壓VDDH(例如5 〇v) 降壓而成’所以若此時輸入信號SIN為LOW(即〇V)，則 反相信號SIN”係變為電壓VDDL”(即3.3 V)，所以電晶體 M03會導通’而電晶體M04會由於電晶體M10導通而被 VIT08-0002/0608-A41518-TW/Final 15 1359340 截止。因此，節點ON1上的電位會被拉低至接地電壓 GNDH ’故電晶體M06會導通將節點〇n2上的電位拉高至 . 輸入/輸出電源電壓VDDH，電晶體m〇7會截止而電晶體 M08會導通，以便產生邏輯準位為LOW的輸出信號 SOUT。換言之，即使在輸入/輸出電源電壓VDDH(例如 5.0V)已備妥（ready)而核心電源電壓（例如3.3V)尚未備妥 時，輸出信號SOUT的邏輯準位可以維持在LOW的狀態， 而非一個未知的狀態。 • 要注意的是’電壓VDDL”係限制於當輪入信號SIN之 準位為HIGH(例如3.3V)時，電晶體M01會截止而只有電 晶體M02，以避免漏電流產生。由於反相器INV1與INV3 之電源端（即電晶體M01與M09之第一端皆耦接至電壓 . VDDL”），所以電晶體M03與M04之控制端上的最高電壓 準位都會是電壓VDDL” ’故可確保準位調整器ιοοΕ具有 50%比50%的工作周期（duty cycle)。 因此，在電源啟動過程中或省電模式中，當較高的操 • 作電壓（即輸入/輸出電源電壓VDDH)已備妥而較低的操作 電壓（即核心電源電壓）尚未備妥時，準位調整器之邏輯輸 出準位是可控制的，而非處於一未知的況態。換言之，在 多電源系統中由於電源時序問題(power sequence issue)所 造成之電源啟動漏電流將可以被消除。除此之外，本發明 之準位調整器只需要一種電源電壓而不需要兩種電源電 壓，這將減輕準位調整器的電路配置困難度，以及降低電 源信號線所需的繞線面積。 VIT08-0002/0608-A41518-TW/Final 16 1359340 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟知技藝者，在不脫離本發明之精神和 範圍内，當可作些許更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係顯示一準位調整器之一實施例。 第2圖係顯示一準位調整器之另一實施例。 第3圖係顯示一準位調整器之另一實施例。 第4圖係顯示一準位調整器之另一實施例。 第5圖係顯示一準位調整器之另一實施例。 第6圖係顯示一準位調整器之另一實施例。 【主要元件符號說明】 10 :降壓單元； 20 :差動放大單元； 100A〜100F :準位調整器；LH :栓鎖單元； DF :差動對； INV1〜INV3 :反相器； M00〜M10、Μ00Α、Μ00Β :電晶體； D1 〜DN :二極體； ONI、ON2 :節點； GNDH :接地電壓； VDDL” ：電壓； VDDH :輸入/輸出電源電壓； SIN :輸入信號； SIN” ：反相信號； SOUT :輸出信號。 VIT08-0002/0608-A41518-TW/Final 17When '·3ν', the transistor M〇1 is turned off and 曰n _2 to avoid leakage current. 〃Electrical 第 Body Figure 4 shows another implementation of the level adjuster of the present invention. The level shown in the figure is similar to U 10GA, the difference is that the buck unit 1 () is implemented by a diode-connected MOS transistor to reduce the input/output supply voltage VDDH to the voltage VDDL. The transistor subsystem has a first terminal that is connected to the input/output power supply M VDDH, a control terminal that is also connected to the input/output, a source voltage VDDH, and a second wheel to the transistor. The first end. The action of the level adjuster WOD is the same as the level adjuster 1A, which is not described here. It should be noted that the voltage VDDL is limited to when the input signal SIN is at the level HIGH. (For example, 3·3ν), the transistor M01 will be turned off and only the transistor M02 will be used to avoid leakage current. Fig. 5 is another embodiment of the level adjuster of the present invention. The level adjuster 100E is similar to the level adjuster 100D shown in FIG. 4, the difference being that the step-down unit 1 is formed by serially connecting a plurality of MOS transistors in the form of a diode connection for Input/output power supply <s VIT08-0002/0608-A41518-TW/Final 13 1359340 Voltage VDDH reduced to voltage Vddl , In an embodiment, the input / output, may be a line voltage VDDH 12v, the core power supply voltage and the input level of the line signal SIN may be 3.3V, and the voltage VDDL "line may be about 3.3V. The operation of the level adjuster 100E is the same as that of the level adjuster i〇〇A, and is not described here. Figure 6 is a diagram showing another embodiment of the level adjuster of the present invention. As shown in the figure, the 'level adjuster 100F is similar to the level adjuster 100D shown in FIG. 4'. The difference is that an inverter inv3 is coupled to the output of the inverter INV1 and the transistor m〇4. Between the control terminals, and one of the inverters INV3 is also coupled to the voltage VDDL. The inverter INV3 includes transistors M09 and M10, and the transistor M09 has a first end (as a power supply) coupled. Connected to the voltage VDDL", a control terminal is coupled to the control terminal of the transistor M03, and a second terminal is coupled to the control terminal of the transistor M04. The transistor M10 has a first terminal coupled to the control terminal of the transistor M04, a control terminal coupled to the control terminal of the transistor M03, and a second terminal coupled to the ground voltage GNDH. In other words, the control terminals of the transistors M03 and M04 are coupled to the outputs of the inverters INV1 and INV3, respectively. The inverted signal SIN" is the inverted signal of the input signal SIN, and the signal on the control terminal of the transistor] VI04 is in phase with the wheeled signal. When the input/output supply voltage VDDH (for example, 5.0V) and the input signal SIN When the core power supply voltage (for example, 3.3V) is ready, if the input signal SIN is LOW (ie, 0V), the inverted signal SIN" becomes the voltage VDDL" (ie, 3.3V)', so the transistor M03 will Turned on, and the transistor M〇4 is turned off due to the transistor M10 being turned on. Therefore, the potential of the <.s VIT08-0002/0608-A41518-TW/Final 14 1359340 on the node ON1 is pulled down to the ground voltage GNDH. Therefore, the transistor M06 will turn on the potential on the node ON2 to the input/output supply voltage VDDH. Since the potential on the node ON2 is the input/output supply voltage VDDH, the transistor M07 will be turned off and the transistor m〇8 will be turned on. In order to generate the output signal SOUT whose logic level is LOW. Conversely, if the input signal SIN is HIGH (ie, 3.3V), the inverted signal SIN" becomes the ground voltage GNDH (ie, 0V), so the transistor M03 It will be turned off, and the transistor M04 will be turned on because the transistor M09 is turned on. Therefore, the potential at the node ON2 is pulled down to the ground voltage GNDH, so the transistor M05 turns on to pull the potential on the node ON1 to the input/output supply voltage VDDH. Since the potential on the node ON2 is the ground voltage GNDH, the transistor M08 is turned off and the transistor M07 is turned on to generate the output signal SOUT whose logic level is HIGH. In summary, when the input signal SIN having the core power supply voltage level is LOW, the output signal SOUT is the ground voltage GNDH (ie, LOW), and when the input signal SIN having the core power supply voltage level is HIGH, the output signal SOUT is the input. / Output power supply voltage VDDH (ie HIGH). If the input/output supply voltage VDDH (for example, 5.0V) is ready and the core supply voltage (for example, 3.3V) of the input signal SIN is not ready, due to the power supply terminal of the inverter INV1 (ie, the transistor M01) The voltage VDDL on the first terminal) is stepped down by the input/output supply voltage VDDH (for example, 5 〇v). Therefore, if the input signal SIN is LOW (ie, 〇V), the inverted signal SIN" It becomes the voltage VDDL" (ie 3.3 V), so the transistor M03 will be turned on' and the transistor M04 will be turned off by the VIT08-0002/0608-A41518-TW/Final 15 1359340 due to the transistor M10 being turned on. Therefore, the node ON1 The upper potential will be pulled down to the ground voltage GNDH ', so the transistor M06 will turn on the potential on the node 〇n2 to the input/output supply voltage VDDH, the transistor m〇7 will be turned off and the transistor M08 will be turned on. In order to generate the output signal SOUT whose logic level is LOW. In other words, the output signal SOUT is output even when the input/output supply voltage VDDH (for example, 5.0V) is ready and the core power supply voltage (for example, 3.3V) is not ready. The logic level can be maintained in the LOW state instead of one Known state. • It is noted that 'voltage VDDL "based on restriction when the wheel of the level signal SIN is HIGH (e.g. 3.3V), the transistor M01 will be turned off and transistor M02, in order to avoid leakage current. Since the power terminals of the inverters INV1 and INV3 (that is, the first terminals of the transistors M01 and M09 are coupled to the voltage. VDDL"), the highest voltage level on the control terminals of the transistors M03 and M04 will be the voltage VDDL. "It is ensured that the level adjuster ιοοΕ has a 50% duty cycle of 50%. Therefore, during the power-on or power-saving mode, when the higher operating voltage (ie, the input/output supply voltage VDDH) is ready and the lower operating voltage (ie, the core supply voltage) is not ready, The logic output level of the level adjuster is controllable, not in an unknown state. In other words, power-on leakage currents due to power sequence issues in multiple power systems can be eliminated. In addition, the level adjuster of the present invention requires only one supply voltage and does not require two supply voltages, which will alleviate the circuit configuration difficulty of the level adjuster and reduce the winding area required for the power signal line. VIT08-0002/0608-A41518-TW/Final 16 1359340 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the scope of the invention, The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an embodiment of a level adjuster. Figure 2 shows another embodiment of a level adjuster. Figure 3 shows another embodiment of a level adjuster. Figure 4 shows another embodiment of a level adjuster. Figure 5 shows another embodiment of a level adjuster. Figure 6 shows another embodiment of a level adjuster. [Main component symbol description] 10 : Buck unit; 20 : Differential amplifier unit; 100A to 100F: Level adjuster; LH: latch unit; DF: Differential pair; INV1 to INV3: Inverter; M00~ M10, Μ00Α, Μ00Β: transistor; D1 ~ DN: diode; ONI, ON2: node; GNDH: ground voltage; VDDL": voltage; VDDH: input/output supply voltage; SIN: input signal; SIN": reverse Phase signal; SOUT: output signal. VIT08-0002/0608-A41518-TW/Final 17