TW472451B - Multi-stage voltage level shifter - Google Patents

Abstract

The present invention relates to a multi-stage voltage level shifter. For a multi-stage low-voltage level shifter, at least two lever shifters are connected in series. Each stage of the level shifter is connected and biased with a medium rank voltage source except the last stage of level shifter that is biased with a high rank voltage source, in which each stage of medium rank voltage source is composed of active devices such as diodes and so on. Input signal is fed to the first stage of level shifter after it is processed by the inverter, and the switch of voltage level is conducted in the differential pair of each stage level shifter. Output signal with high voltage level is generated by the last stage level shifter, and is sent to the external chip or cable through the input/output interface chip.

Description

47245t

FIELD OF THE INVENTION The present invention relates to a voltage shifter, and more particularly to a multi-level input signal that is converted to a high-level shifter. = Quasi-Transfer (Voltage levei segmented circuit structure used to lower the low voltage level of the output signal at low voltage level) BACKGROUND OF THE INVENTION: With the development of deep sub-micron semiconductor technology, in addition to the increasing function of electronic components' The area required for each element is also gradually reduced, so the operating voltage of the mother element is also lower. For example, the operating voltage required for CMOS in the 018 micron process is only 18 V415V, while in 015 micron ^ privately The CMOS only requires an operating voltage of 1 · 5V or 1.2 V. In addition, because the operating signals of the two external chips are still running when the cable (cab 1 e) is passed, the voltage is 3, ·, 3, or 5 It works under 0V, so when the signal needs to be transmitted through the wire or sent to an external chip for further processing, it needs to pass a level shifter to convert the voltage level of the signal. ^ The moon dagger is used for the I / O interface chip. 2. Refer to the first figure 'It depicts the circuit structure diagram of the first level shifter applied to the conventional technology.' The level shifter is mainly By an inverter (Inverter) 1 and Differential pair. The above-mentioned inverter is a CMOS inverter and includes a low-voltage M0s transistor MN3 and a low-voltage PM0S transistor mp3 '# 中 电 晶 MN3 and transistor MP3 between

472451 V. Description of the invention (2) The gates are connected to input the low-voltage input signal π; and the transistor MN3 and the drain of the transistor MP3 are connected to each other to output the input signal The inverted signal VI B of VI. The above transistors are all 1 (Metabu Oxide-Semiconductor 'MOS) transistors. In addition, the source of the transistor MN3 and the transistor MP3 are connected to the reference voltage sources VSS and VDDL, respectively. In general applications, the reference voltage source Mg may be connected to the ground terminal, and the reference voltage source VDDL is a low-order voltage source and used as a bias (Bias). It may have a fixed output voltage level (Eg 1.2V) reference voltage source. As for the differential pair, two high-voltage switching transistors MN1 and MN2 are used in combination with two high-voltage PM0S transistors MP1 and MP2. The sources of the transistors MN1 and MN2 are also connected to the reference voltage source v. § s phase connection 'and the gates of transistors MN1 and MN2 are respectively input VI and ^ 〖^. In addition, the drain of transistor MN1 and transistor MP1 and the gate of transistor Mp2 are connected to form node v0B; the drain of transistor MN2 and transistor MM is connected to the transistor The gates of Μρι are connected to form a round-out U V0 and the source and base of the still voltage PM0S transistors MPi and MP2 are connected to the high-order voltage #VDDH. In addition, since both high-voltage and low-voltage transistors are formed on the substrate, in most integrated circuit applications, the substrate of the NMOS transistor is connected to a maximum negative current. The substrate of the PM0s transistor is connected to a maximum positive voltage, for example, the substrate of the voltage PM0s transistor Mρι and Mp2 is connected to VDDH 'to maintain the reverse bias of the pn junction between the substrate and the channel. Because the above-mentioned technology belongs to the category of conventional technology, it will not be described in detail in the future. The gate thickness of the above-mentioned voltage-transistor is relatively low.

472451

It has a higher threshold voltage and breakdown voltage, so it can withstand higher voltages during voltage level conversion, and can avoid the gate oxide junction of the transistor. Overstress occurs. As for the high-voltage and high-voltage transistors, the diagram is drawn to the right of the first figure for reference. Although the structure of the voltage level shifter shown in the first figure is quite simple and easy to implement, it has the disadvantage that it cannot work normally in the application of converting extremely low voltage to high voltage. For example, when the input (K can be the level of VSS, generally the heart rate, VIB will be (the voltage level of ^ to VDDL). So transistor MN1 will be turned off (0FF), and the power Crystal MN2 will be turned on, so node V0 will be logic 0, and node ν〇β will be logic 1. Therefore, under the static state (VI) where VI is logic 0, 'transistor MN1 and MP2 will be turned off. , And transistor MN2 and] ^! Are in a conducting state. Next, when VI is gradually charged from logic 0 to the level of logic 1, when the level of VI exceeds the initial voltage of transistor pin 1, the transistor · 丄 is turned on immediately, but the transistor MN2 at this time is turned off because the node νΐβ is logic 0. Because the original node V0B is at the voltage level of logic i 'and begins to discharge after the transistor MN1 is turned on. However, During the process of the node ν〇β starting to discharge, the transistor MP2-remains in the off state, so that V0 is still maintained at the logic 0 level, and the transistor Μρι is still in the on state. Obviously, because the VI switches the bit At the moment of switching from logic 0 to logic 丨, ΜN1 MP1 and the body simultaneously in the ON state, the drive power capability of transistor ΜΝ1 (Drive strength) must be relatively large transistor Μρι, only the right node V0B discharge, thereby enabling the correct output v〇

4724TS1

Gure t Γ is large. Therefore, if you want to achieve the above requirements, ask for the layout area of the MNMOS transistor printed with AA & snowy PMOC with B (13 〇〇1 ^ 3 ^ 3) higher voltage level (logic)), The channel width of the transistor MN1 needs to be larger than that of the transistor Μρι and the MP MP. The same situation also occurs in the transistor MN2, and this must be increased. The structure of the component area is completely different

Meet the needs of economic benefits. T #, Furthermore, 'Because the high-voltage question 0S transistor MN1 and MN2 are working at a high voltage level (such as 3.3 V or 50 V, ί τ & ^ 乂. Υν), so its start The voltage is relatively high (about u / v left,), but when the transistor 0 and M2 are turned on, the gate voltage difference between them is maintained at only about I 2V. Therefore, when the transistors MN1 and MN2 are turned on, their gate-to-source voltage (Vgs) is only about 0.4V (that is, 0 '8 0.4), so the noise tolerance of the first level shifter is (Noise margin) is also quite low, and because transistor MN1 is only turned on slightly (because Vgs is only 0.4V more than the starting voltage), the layout required for transistor MN1 is larger. Similarly, the same situation occurs when the input signal VI is switched from logic 0 to logic 1, except that the roles of the transistors MN1 and 02 are reversed. The circuit structure of another low-voltage level shifter is as shown in the second figure ', which is disclosed in CUpp III et al. Obviously, although the level shifters disclosed in c 1 app III all use low-voltage transistors MNΓ, MN2 ', MPΓ, and MP2 to build differential pairs, an additional voltage source VDDM, two Low voltage PM0S transistors MP7 and MP8, two diodes D1 and D2, of which the transistor

Page 7 472451 V. Description of the invention (5) MP7 is connected between transistor MNΓ and MP1, and transistor Mp8 is connected between transistor MN2 'and MP2'. Both of the above two transistors Mp7 and Mp8 are It is connected to and biased by the middle-order voltage source VDDM, and the middle-order voltage ^ voltage level VDDM is between VDDL and VDDH. In addition, diode 02 is connected between the gate and source of transistor MP7, and diode D2 is connected between the gate and source of transistor MP8 (that is, the output node v0). Although the upper level shifter can avoid the effect of excessive stress on the gate oxide interface, it requires an additional intermediate voltage source VDDM, and the noise = sees an increase, even the potential of the architecture logic 0 The voltage drop in the Yangguan minus the pole a is not the potential of the ground view, so this type of quasi-transfer benefit voltage swing is not a full transition state (FuU swing), so it cannot be used in a state that requires a full transition Level shift application. Purpose of the Invention The present invention when the hair swings, and does not carry out the multi-level shifter based on the origin of the hair, its main body used above has a high order and a clear master needs to be re-connected in addition. The purpose of J is to expose a low-voltage level transition that is easy to implement and is in a full voltage transition state. The second purpose is to expose a low-voltage level shifter with an automotive voltage source. Two: Two is to disclose a low-voltage level shifter that can be used according to actual applications. :: 'Low voltage level rotation device (Active devirp, Binghuai 々 * · 丄 ----------------- 丄 e) disclosed in the present invention. What is the order voltage-a… one source bias voltage to generate. Middle-level voltage level. Ί .. · string Ϊ-472451 V. Description of the invention (6) ^ The level shifter is stricter than the intermediate-level voltage source , Used to transfer the low voltage signal to two high voltage jt. In the first embodiment of the present invention, the "input Ϊ = human to ㈣s inverter" is used to generate an input signal, and the input signal and its inverted signal are input to the first-level level shifter. The first level shifter is composed of a differential pair, and the differential pair 2 is composed of two high-voltage NMOS transistors and two PMos: high-voltage pseudo-transistor systems. The output of the differential pair in the soil is transferred to the second level level J 'to feed in the signal output by the differential pair, and: The input level is converted. The second level level is turned into a special one. It is further carried out that the voltage is located at its output terminal. Does the output have high power: biased by the quasi-source, and in the second preferred embodiment of the present invention '; ^ --- ~ serially connected, except for the last one ..隹 ω Man-Apocalypse Resuscitation-quasi-Ail inverse > bad '1 level 2 per stage-Manifold: It is a dual high-order voltage source first-level level IM multiplier, Chinese and Chinese, The processing * then the voltage level during the feed and the difference between the level shifters at the mother level-the differential pair of the level ΐ: η,! Of the differential pair out of 4 =., The out of the class will be the wheel Out to: The color is free, and each stage of the China Post is connected to a medium-level voltage source and is affected by the voltage source. In this embodiment, the voltage source is also transformed. Feed immediately after processing Work to. ~ Zhu Xia, the differential pair of each silk level turns into 4 士, and 屮 Λ A ，, and finally the voltage signal of the entrance and exit of the interface chip is 472451.

Detailed description of the invention: Please refer to the third figure, which depicts the first and the preferred embodiment of the present invention and the crying machine. The input signal νι is fed from the car to the vehicle, and the input signal νι is: In 302 ', the inverting signal νVIβ of VI is generated by the inverter 3Q2, until VDDL Ϊ IT V ^ ^ ^ ^ ^ ^ ^ # ^ VSS VDDL bias. The input signal VI and its inversion signal vib are both input to the stage level shifter 306 to generate a reference level VM (V: 2 for the differential pair. The output of the differential pair (including VM and the VM VMB) k in the opposite phase is fed to the input terminal of the second-level level shifter 308, and finally the level-level level shifter 308 outputs the level-converted output signal v0. The first stage level shifter 306 and the second stage level shifter 308 are biased to a medium-level voltage source (the output voltage level is ° VDDM) 304 and a high-level voltage source VDDH, respectively. Among them, the level of VDDM is between vddl and VDDH. In addition, due to the internal structure of the first-level level shifter 306 and the second-level level shifter 308 in the preferred embodiment of the present invention It is exactly the same (more details will be described later), so it is quite convenient in implementation and the required power consumption is not large. The middle-order voltage source 304 in the preferred embodiment of the present invention is constructed by an active device. Its main function is to generate intermediate-level voltage level (VDDm) between VDDL and high-order voltage source. Figures 4a to 4f respectively Describes several internal circuit structures of the intermediate-order voltage source 304. Figures 4A and 4C show the structure using a high-voltage pMOS transistor to generate a medium-level voltage level. It should be noted Yes, the above-mentioned PMOS transistor system provides a partial voltage in the form of a diode, and the structure shown in Figure 4C is a series connection of two diodes.

Page 10 472451 V. Description of the invention (8) The way to generate VDDM is shown in Figure 4. Therefore, the VDM generated in the fourth C diagram is smaller than the VDDM generated in the fourth A diagram. Similarly, the fourth β diagram and the fourth β diagram show the structure using a high voltage NMOS transistor to generate VDDM, and the VDDM generated by the fourth D diagram is smaller than the VDM generated by the first diagram. As for the structure shown in Figures 4E and 4F, the structure of VDDM is generated by using diodes in series, and the VD generated by Figure 4F]) M is also higher than that generated by Figure 4 VDDM is small. For the diodes connected in series as shown in the figure, except that the anode terminal of the first stage is connected to a high-order voltage source, the anode terminals of the other diodes are connected to the diode of the upper stage. Extremely pure, and the cathode terminal of the next stage diode outputs the required intermediate voltage level. It should be noted that the above is in the fourth C diagram, the fourth ㈣, or the fourth? What is connected in series in the diagram :, piece = 罝, or which kind of active element is used in the medium-level voltage source 304: It can be adjusted according to the actual application. Those skilled in this case can change it according to the spirit. < The fifth figure depicts the detailed circuit address of the preferred embodiment shown in the third figure: wherein the intermediate-order electric source 304 is generated with the fourth figure structure and the level (VDDM). Obviously, in the first stage level shifter 3206 and the second shifter 3 08, except for the axes and views:,:,:, ST and the figure = The structure of the differential pair in the first known technology is the same, so Easy in implementation 2. Moreover, in the preferred embodiment of the present invention, = from brittle to full M, and then from VDDM ㈣ to _ ^: The disclosed circuit structure also has a greater complexity than the conventional technology: :: 发 472451 V. Description of the invention (9) In the operation of the fifth figure, since the gate of the transistor MP6 is connected to the drain, the transistor MP 6 will be turned on and the DC current (]) C current) will flow from VDDH to VDDM, and VDDM is used to bias the differential pair in the first-stage level shifter 306. When the voltage level of the input signal changes, an instantaneous alternating current (AC current) will be caused by the conduction of the transistor and it will flow from VDDH to VDDM, so the current flowing through the active device will increase, and VDDM will be reduced at this instant, so The output terminal (VM or VMB) of the differential pair is charged and discharged more quickly, so that the switching of the level is completed more quickly. For example, suppose VDDH = 3.3V, VDDL = 1.2V, and the starting voltage of transistor MP6 | vthp 丨 = 0, 7V, so VDDM S VDDH- | Vthp | = 2.6V, and 2.6V is Between 1.2V and 3.3V. When the input signal vi switches the level, the induced AC current will make VDDM less than 2. 6V, and after the input signal VI is switched, the VDDM is maintained at a stable state of 2. 6V. Similarly, the VDDM is generated by using the circuit structures of the fourth B diagram to the fourth ρ diagram, and there are similar operation situations as described above. The skilled artisan can adopt an appropriate circuit structure according to the actual application. The sixth diagram depicts the waveform changes of each node level during the operation of the circuit structure of the fifth diagram, where VDDH = 3, 3V, VDDL = 1. 2v, and the starting voltage of transistor MP6 | vthp | = 0.7V , And VDDMS VDDH- I Vthp | = 2.6V. Obviously, the input signal VI is initially maintained at the logic 0 level, and VDDM is maintained at around 2.6V. Because the transistor MN2 is in the on state, VM and "] 8 are maintained at logic 1 and Logic 1 level. Furthermore, because transistor MN5 is in the on state, the output signal vo will maintain the logic 0 level. Next, when the turn-on signal v I turns on

472451 5. Description of the invention; ^ When the level of logic 1 is switched, the ac current generated will make M · instantaneous, and Lian Gong will also reduce the level of node VM, so that the node νΜβ will be quickly discharged, then After the input signal ¥ 1 is switched, the position of VDDM '; Ik slowly rises to the level of 2. 6 V, and the node vm is also charged to 2. 6 V. In addition, as the voltage level of the node ν μ increases, the transistor MN4 is turned on and the transistor MN5 is turned on, so the output signal is switched to the VDDH (ie, 3.3V) level. Similarly, when the input signal VI is switched from logic j back to logic 0 ', VDDM drops instantaneously, and the node " is discharged more quickly, so transistor MN4 will be turned off and transistor mn5 will be turned on, so that The output signal is switched back to a logic zero level. The seventh figure depicts a second preferred embodiment of the present invention, which connects the level shifters 306 to 306N, 306L in series, except for the last level shifter 3 0 6 L. 'Each level shifter is connected to and biased by a corresponding intermediate voltage source 304 ~ 304N, and each level shifter is composed of the differential pair structure depicted in the fifth figure And feed the output of the differential pair, such as VM1 and VMB1, VMn and VMBn into the level shifter of the next stage. It should be noted that the intermediate-stage voltage source 3 0 4 to 3 0 4 N of each stage gradually increases depending on the situation. For example, in a four-stage _connected level shifter, the intermediate-stage voltage source 3 04 ~ 3 0 4N of the first to third stage level shifters can be generated to 1. 8V and 2. 4V, respectively. , 3. 0V level, and the above-mentioned first-stage to third-stage intermediate-level voltage sources 304 to 304N can be connected in series with 3, 2, and 1 diodes to align the level shifters 306 to 306N, respectively. Bias. In addition, since the voltage level converted by each level shifter 304 ~ 304N is not large, the noise tolerance of the second preferred embodiment of the present invention is even more

Page 13 472451 V. Description of Invention (11) has been enlarged. In addition, the intermediate-level voltage source levels used in the two embodiments disclosed in the present invention may vary according to actual applications, and may be applicable to even smaller VDDL or larger VDDH. To sum up, the multi-stage low-voltage level shifter disclosed in the present invention can use the active device as a mid-level electric migration source to bias each stage of the shifter to The low-voltage signal performs level conversion, and the advantages of the present invention are as follows: (1) the noise tolerance is increased, especially when multi-level serial connection is used; (2) the required product of the NMOS transistor is reduced; ( 3) The structure is simple and easy to implement; (4) It can be used in advanced semiconductor processes, such as in applications with lower VDDL. 0-The above is only a preferred embodiment of the present invention, and is not intended to be limited. : The scope of the patent application of the present invention; & Others without departing from the disclosure of the present invention :; Equivalent changes or modifications completed by the application, for example, the intermediate-order voltage source is repeated: a pole is connected in series to form 帛, Should be included in the patent application

Page 14 rst 4724

Simple description of the circle: Simple illustration of the diagram:. The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: The first figure is the first low voltage level shifter in the conventional technology; the second figure is the conventional The second low-voltage level shifter in the art is the level shifter disclosed in Clapp III in US Patent No. 5, 53 9, 3 34; the third figure depicts the first preferred embodiment of the present invention. The block diagram of the structure of the embodiment; FIG. 4A is the first implementation of the middle-order voltage source in the preferred embodiment of the present invention; FIG. 4B is the two implementations of the middle-order voltage source in the preferred embodiment of the present invention Modes;-The fourth diagram C is two implementations of the intermediate-order voltage source in the preferred embodiment of the present invention;-The fourth diagram D is one of the examples of the present invention in which the target is removed The fourth embodiment of the middle-order voltage source; TJ and the fourth E diagrams are five embodiments of the present invention;-The fourth F diagram of the middle-order electric dust source in the embodiment is a comparison of the present invention.伟 银 # 汉 乂 1 The sixth embodiment of the middle-order voltage source in the example of the known shellfish; the fifth diagram of the structure depicts the present invention The first block diagram of the preferred embodiment of the circuit, the sixth diagram depicts the use of the low voltage level clock disclosed by the present invention, the input signal, the rotation signal, the transfer% and some nodes Waveform switching block

472451 on page 15 is a simple explanatory diagram of the drawing; and the seventh drawing depicts a block diagram of the architecture of the second preferred embodiment of the present invention; the drawing number part is:-3 0 2: inverter; 3 0 4: middle-order voltage source ; 3 044N: the middle-order voltage source connected to the N-th level shifter; 3 06: the first-level level shifter; 3 06N: the N-th level shifter; 3 06L: the final level Transfer device; 308: second level transfer device;

Dl, D2: diodes; MN1, MN2, MN4, MN5: high voltage NMOS transistors; MN1 ', MN2', MN3: low voltage NMOS transistors; MP1, MP2: high voltage PMOS transistors; MP1, MP2 ' MP3: Low voltage PMOS transistor; MP4, MP5, MP6: High voltage PMOS transistor; MP7, MP8: Low voltage PMOS transistor; VDDH: High-order voltage source; VDDM: Middle-order voltage source; VDDL: Low-order voltage source ; VI: input signal; V IB: inverted signal of input signal; VM: one reference level output by the differential pair;

Page 472451 Brief description of VMB: Inverted signal of VM; VM1: First reference level of first-level level shifter; VMB 1: Second reference level of first-level level shifter; VMn : The first reference level of the N-th level shifter; VMBn: the second reference level of the N-th level shifter; V0: the output signal; VOB: the internal node of the differential pair, whose voltage level is The inverted signal of the output signal; and VSS: ground.

Page 17

Claims (1)

472451 shi fter) for the signal, the voltage level 1. A voltage level shifter (V〇ltage Uvel converts low voltage level signal to high voltage level level shifter at least: a plurality of middle-order to a high-order The plurality of electrical series are connected with a plurality of the intermediate-level series before the quasi-transition device level transfer and the level-transition of the intermediate-level electrical signal are used for the final level-level transfer to generate an output phase. The voltage generating voltage source is used to transfer the reference level of the intermediate-level electric voltage device to the reference device. The voltage device generates the signal in the first transfer device device due to the voltage level. For each handle, the reference voltage of the middle-order voltage is connected to the middle-order and the phase device generated by the step-voltage of the device to generate the level of the mobile device generated by the voltage source of the mobile device, which should be the same. Enter the first-order bit, corresponding to each of the middle-order in the last one, and one of them is related to the signal in which the series is coupled and the quasi-transfer The signal level produced by the senior level; the level is used to input the letter to the tea test source based on the level, level, and voltage of the voltage source. The reference device and the wheel source should be connected to the device as well as the transfer device. The inverse phase alignment between the number of bits generated and the number generated in the first position of the set; and the voltage level shifter input of the '^ application patent scope item 1 used by the cross alignment to input signals The device is used to generate the round-phase signal in response to the input signal. The device further includes a voltage-level shifter of the round-in signal, which is the inverse of the patent application scope item 2, wherein the above-mentioned Page 18 472451 1 '1 —— One-One 6. Patent application scope The input device is an inverter. 4. The voltage level shifter according to item 1 of the scope of patent application, wherein each of the above-mentioned intermediate-level voltage generating devices includes at least a metal-oxide semiconductor (MOS) transistor having a gate, a An electrode and a source, wherein the gate of the transistor and the drain coincide. 5. If the voltage level shifter of item 4 of the patent application range, wherein the above M ^ S transistor system-a PM0S transistor 'let the source of the PM0s transistor be coupled to the first-order voltage source, The gate and the drain are coupled to output the intermediate voltage level. 6. The voltage level shifter according to item 4 of the scope of patent application, wherein the above-mentioned intermediate voltage source further includes a plurality of PMOS transistors connected in series, wherein each PMOS transistor has a gate and a drain. And a source, the gate of each of the PM0S electrical μ-body is coupled to the non-polar, and the transistor, the source and the idler of the pM0s transistor connected in series to the next stage With this drain:. Among them, the pM0s transistor in the first stage of the series connected PM0s transistor :: the: pole is connected with the high-order voltage source, and the pM0s transistor connected in series: The gate and the drain coupled to the 忒 PM0S transistor are the voltage level shifter of item 6 in the scope of patent application, the above mentioned in # Page 19, 472451 VI. In the patent-applied series-connected level transfer device, the number of the series-connected PMOS transistors included in the intermediate-stage voltage source coupled to the level-transfer device in each stage is higher than that in the previous stage. The number of the series-connected PMOS transistors included in the intermediate-order voltage source coupled by the quasi-transfer device is small. 8. If the voltage level shifter of item 4 of the patent application scope, wherein the above MOS transistor system is an NMOS transistor, the gate coupled to the NMOS transistor and the drain are coupled to a high-order voltage source, and The source outputs the intermediate voltage level. 9. For example, the voltage level shifter of the fourth patent application range, wherein the above-mentioned intermediate voltage source further includes a plurality of NMOS transistors connected in series, each of which has a gate, a drain, And a source, the gate of each NMOS transistor is coupled to the drain, and the source of the NMOS transistor is in phase with the drain of the NMOS transistor in series with the next stage Coupling, among the NMOS transistors connected in series, the gate and the drain coupled to the high-order voltage source in the first-stage NMOS transistor are coupled, and in the NMOS transistor connected in series, the The source of the NMOS transistor outputs the intermediate voltage level. 10. The voltage level shifter according to item 9 of the scope of patent application, wherein in the above-mentioned serial level shifting device, the series connection included in the intermediate-stage voltage source coupled to the level shifting device of each stage The number of NMOS transistors is greater than the series connection included in the intermediate-voltage source coupled to the level-transfer device of the previous stage Page 20 472451 6. Scope of patent application The number of NMOS transistors is small Π · If the scope of patent application is the first! The voltage level of each item is: to the middle-level electric dust generation device: to: once: the above;-cathode terminal 'where the anode terminal of the diode: = =; anode terminal σ' and the diode The cathode terminal turns out this intermediate voltage level. The source shift level shifter of item 12 of the source coupling range, wherein the cutting generating device further includes a plurality of diodes connected in series :: if :: body has an anode end and a cathode end, each body ::: In the diodes connected in series, the rear-stage diode Π; the source phase is combined, and the intermediate-level voltage level. , _Choose this with the cathode end ^ If you apply for the application:] The voltage level shifter in the 12th range, where the previous series connection level is transferred to the center, # 一 的 之 行, Zhong Shang Sui should The number of the diodes included in the intermediate-order voltage source is smaller than the number of bits in the intermediate-stage voltage source stage that are turned on by the light-weight quasi-transfer device. 1 G 3 of this series diode Page 21 1 4. If the voltage level of the first patent application range is 2 and the reference level 3 and-the second reference level generated by the level transfer device, "the first reference level and six, The phase of the patent application level is reversed and the phase is shifted to the level of the piezoelectric item. 4 11 Fan Li specially requested to apply the above-mentioned one, the standard, and the standard should be applied; The source includes the first set of the first set, the first set of the first set, the second set of test sets, the second set of the set of crystals, and the second set of the set of the second set of the set. Differentiate a body to connect a first shifting crystal string, the electric transformer mobile pole string to the rotation level, and each device to be connected to the first in the above description: a quasi-paired crystal containing pole position electric package The one-to-one difference between the source level difference pair and the previous one is the same as the one before. The difference between the pair and the pair is the second difference. The pole is due to the gate and the gate. The production of the life, the production of the source, the installation of the source, the transfer of the crystal, the source of piezoelectricity, In the test, the quasi-aligned pole position power supply level difference is one-to-two and the first difference. The second one is connected to the first pole string and the other should be used. The source body and the crystal are electrically and counter-polarized, the gate electrode and the pole have a drain electrode, and the body crystal electrode is negative and negative, and the electrode is negative. The pole should be paired with the ground, the pole, the pole, the pole, the pole, the pole, the pole, the pole, the pole, the pole, the pole, and the body. A pole crystal and a drain current. With the load, the first phase of the crystal body, the second phase, the crystal phase, the current phase, and the second phase of the negative and negative coupling. The phase of the phase and the pole position of the source are transferred to the quasi-corresponding position of the source. The crystal and the electricity are used to load, and the first phase is coupled to the phase phase. The two pairs of body pairs of the negative electrode in the compacted coupler phase crystal Page 22 472451 6. Scope of patent application and biased by the intermediate voltage level generated by the intermediate voltage level voltage device (Biased). 1 The voltage level transfer device according to item 15 of the scope of patent application, wherein the first differential pair transistor and the second differential pair transistor system nm os transistor: 'and the first load transistor and the The second load transistor system pM0s transistor 1 7. The voltage level shifter as claimed in item 15 of the patent scope, wherein in the first level level transfer device connected to the quasi transfer device, the first The gate of the differential circuit is based on the input signal and is used to generate the second reference level of the first stage and quasi-transfer device. The inverted signal of the input signal is used to generate the first reference level of the first-stage level transfer device. The first-level differential pair transistor has a gate,-Chinese eclipse, and the second one. The gate of the first-level differential pair transistor should be the final one in the series transfer county. The first reference level generated by the first level is used to generate the final level level before the drain of the first differential pair transistor and the second reference level 1 The source of the first differential pair transistor in the final stage is coupled to a reference voltage source; the first and second stages—the differential pair transistor, has a gate, a drain, and a 8. The voltage level transfer device of 15 items, wherein the above-mentioned final level transfer device includes at least: > and poles, and On page 23, the source range of the patent application, the 5th quasi-transfer device reads the source of the final-stage shift device and the first-stage final pole of the reference 'the final $ pairs of transistors and the closed-pole 1 final stage second pole 'the final g pair transistor remote gate and the + read final stage transistor of the 4 high-order voltage final stage second differential pair final set of two differential pair transistors A first reference level, the gate of the voltage test crystal corresponding to the second reference level, using the drain to generate the final stage and the final second differential coupling to the transistor source; the load transistor, The gate with the first load transistor coupled to the drain terminal and the second stage to which the non-polar phase is connected. The pump terminal is connected to the final, a light pole and the most connected to the quasi-rotation. One source and one differential body; and-source-differential body, its load and receiving, and the final first-stage first load transistor phase, and the second-stage second differential pair transistor's drain Crystal, with the drain transistor of the load transistor The first differential pair transistor is a combination of the source of a load transistor and the biased load transistor of the high-source phase source, which is used to press the (Biased) electrode and the second-most negative transistor. And the second-phase coupled crystal of the final-stage voltage source current-carrying phase-conversion stage, such as the voltage level transfer of the eighteenth item of the patent scope, where ^ the first differential pair of the final stage and the final stage The second stage of the second differential pair is a two-MOS transistor, and the first-stage load transistor of the final stage and the outermost edge are: a load transistor system PMOS transistor. "'Brother If the voltage level shifter in the first patent application range, i * β Y The above output signal is sent to the cable or chip for further operations. Page 24 472451 6. Scope of Patent Application 21 · —A kind of voltage level shifter (V〇ltage level shifte converts the signal of low voltage level to high voltage level Γ 'used to quasi-shifter includes at least: seven breaks, the voltage level intermediate-level voltage generating device, corresponding At a high-level voltage source voltage level; π 乂 生 生 一 中 中 中 中 中 intermediate-level first-level level shift Pei set, corresponding to the intermediate-level voltage level, ^ ^, and the inverted signal of the input signal to produce 4: Enter t and-the second reference level, where the first reference level is two parameters: the phase of the standard is opposite; and flat one is the second reference level shifting device of the first reference level, corresponding to the higher-level electric test position Level, and the second reference level, the following is generated: the phase of the output detection number of the younger-reference A is the same as the phase of the input signal. A. If the voltage level shifter of item 21 of the patent application scope, more The human input device is used to generate the input-inverted-phase signal in response to the input signal. 就 ° The above-mentioned 23. The input device whose voltage level is transferred as in item 22 of the scope of patent application is an inverting phase器。 24. Such as applying for a patent Around the second voltage level shifter Paragraph Shu, and in order voltage generating means comprises at least one metal oxide and a half above the guide ,, Page 25 472451 VI. Patent application scope (Metal-Ox i de-Semi conductor, MOS) transistor has _ idler-drain, and a source, where the gate of the MOS transistor and the, and, The perfect match. 25. If the voltage level shifter of the 24th scope of the patent application is applied, the above-mentioned M0S transistor system is a pMOS transistor, and the source of the PM0S transistor eats the high-order voltage source phase. 'Coupled' and the gate and the drain coupled are at an intermediate voltage level of ° Λ. Differentiate the 2 6 · If the voltage level shifter of the 24th item of the patent application scope, the upper intermediate voltage source further includes a plurality of PM0s transistors connected in series / its PM0S transistor has a gate ,-The pole, and-the source, the gate of each and the PMOS transistor is coupled to the drain, and the source and the next one are from Toshizaki. Rain α Α ύ electricity day, ^ ^ Gan, 'exPM0S serially connected the gate and the drain phase j stone, where the PM0S transistor in series, the first level of the pM 〇s The source plate of the crystal is older than Lei Mao, JS scholars said that the I5 is coupled from the voltage source, and the PM0S voltage in the series is connected to the PM0S. The intermediate voltage level of the gate and the gate of the transistor is light. The voltage level shifter of the 24th range, in which the above-mentioned pole spot #t M0S transistor, the gate of the NMOS transistor combined with the voltage source of the voltage stage are light-on ', and the intermediate stage is output by the source. Page 26 472451 6. Application for patent scope 28. For example, please apply for the voltage level shifter of the patent scope item 24, wherein the above-mentioned intermediate-level voltage source further includes a plurality of NMOS transistors connected in series, each of which is a NMOS transistor The crystal has a gate, a drain, and a source. Each gate of the gate aB body is coupled to the drain, and the gate of the gate is connected to the gate. The source and the drain of the gate transistor connected in series to the next stage are connected to the drain electrode, of which the cascaded gate transistor is connected to the first stage of the NM transistor. The coupled gate and the drain are coupled to the high-order voltage source, and among the two tN: OS transistors, the source of the NMOS transistor of the last stage outputs the intermediate-voltage level. 29. As for the voltage level transfer device of the scope of application for patent No. 21, the middle-upper-middle-stage voltage generating device includes at least a diode with an anode terminal, wherein the anode terminal of the diode and the high-order voltage source phase α, And the cathode terminal of a pole body outputs the intermediate voltage level. 30. If the voltage level shifter in the scope of patent application No. 21, the wide-range voltage generation of the bean set includes a plurality of diodes connected in series, and each of the diodes has an anode terminal and a cathode terminal. It is connected with the cathode terminal of the pre-stage diode, and the mother = = yang; body * = the anode terminal of the stage diode and the high-order electricity. J is combined, and among the diodes connected in series, the intermediate voltage level is at the last stage. Carcass α-Hai cathode end wheel 31. The voltage level shifter according to item 21 of the patent application, wherein the above 472451 VI. The phase of the -reference level of the scope of patent application is opposite to the phase of the second reference level 3 2 ★ The electric level shifter of item 2i of the patent scope is declared, in which the above-mentioned first-level level shifting device It includes at least: the first-stage first differential pair transistor, which has ^ a pole, a drain, and a 1¾ first-stage first-stage differential gastrotransistor. The reference level is generated at the drain of the first-stage first differential pair transistor, and the source of the first-stage first differential pair transistor is coupled to a reference voltage source; the first-stage first differential The dynamic pair transistor has a gate, a drain, and an f 4 first-stage second differential pair transistor. The gate is corresponding to the 忒 inversion 彳 g 'of the input ^ number for the The first reference level of the second differential pair transistor generates the second reference level, and the source of the first second differential pair transistor is coupled to the reference voltage source; A load transistor having a gate, a drain, and a source 'the drain of the first-stage first load transistor Is coupled to the drain of the first stage first differential pair transistor, the idler of the first stage first load transistor is coupled to the drain of the first stage second differential pair transistor ; And a first-stage second load transistor having a gate, a drain, and a source, the drain of the first-stage second load transistor and the first-stage second differential pair transistor The drain is coupled to the first load transistor of the first stage, the pole is coupled to the drain of the first differential transistor of the third stage, and the first load transistor of the first stage is The source is coupled to the source of the second load transistor, and is used to couple with the middle-order voltage generating device to Page 28 472451 6. Scope of patent application Biased by this intermediate voltage level. 33. For example, the voltage level shifter in the scope of application for patent No. 32, wherein the first 'first differential pair transistor and the first-stage second differential pair system NMOS transistor: and the first stage The first load transistor and the first-stage second load transistor PMOS transistor. 34. If the voltage level shifter in the scope of application for the patent No. 21, the first-level level-shifting device includes at least: the second-level: the differential pair transistor has a gate, a drain, and a :: Jin: f: The gate of the first differential pair transistor corresponds to the first reference level generated by the -th position, and is used for the second -th body of the- The second-stage level transfer device is coupled to a reference voltage source; the source of the electric sun-solar body :: level]; difference: r ;;: has a gate, -an pole, and- Level level transfer: The free electrode of the f pair of transistors corresponds to the source of the second differential pair transistor and the source of the second differential pair transistor. = Transistor 'has-interpole, 1 And the drain of the second-stage first-loaded transistor are in contact with the drain of the second-staged-differential circuit and the second-stage first-loaded transistor Page 29, 472451 VI. The patent application Fan Yuan selects the first-stage second load transistor with a free pole and the drain of the first-stage second differential pair transistor, which has a gate and a drain. The drain of the second-stage second load transistor is coupled to the drain of the second-stage moving pair transistor, and the second-stage second-load transistor is coupled to the second The source of the first-stage first differential pair transistor is coupled to the source of the first-stage first load transistor and the source of the second-stage first and second-body are coupled to connect to the higher-order voltage. The source is biased by the high-order voltage source. Μ. * If the voltage level shifter in the scope of the patent application is No. 34, the second-stage first differential pair transistor of t and the second-stage second differential pair are N Μ 0 S electric body, And the second-stage first load transistor and the second load transistor PMOS transistor. 3 6. A voltage level transfer method is used to change the signal of the low voltage level to the signal of the south voltage level. The voltage level transfer method is a small series of steps: > Generate a middle-order voltage level; ― 帛 —reference level and ― 帛: reference ^ earth reference level or second reference level in response to an input signal, the inverted signal of the input signal, and the voltage level The voltage level of the input signal or the inverted signal of the input signal is stable > the response depends on the first reference level, the second reference level, and the combination; and a source The combination of two differential crystals, the second load of which is subject to the above-mentioned transistor two-level: the number of transitions includes the middle order, where the state value is higher order Page 30 4/24 :) 丄 This level is used to generate an output signal with a thunder-•. ^?, And the two electric fortress swings are in a full transition state (Ful 1 swing). & " 3 7 · The method of voltage level transfer of the output signal as described in the scope of patent application No. 36], wherein the upper quasi-steady state value is equal to the higher-order voltage level. 3 #lL E The voltage level transfer method of item 36, in which the voltage level in the above mentioned ^ voltage level will be reduced immediately after the signal switching of the round. 39. The voltage level transfer method according to item 36 of the declared patent range, wherein the above-mentioned intermediate-level voltage level is generated by at least one PMOS transistor connected in series, wherein the PMOS transistor has a question pole, And the source, the gate of each PMOS transistor connected in series is coupled to the drain, and the source of the PMOS transistor is connected to the gate of the pMOS transistor connected in series to the next stage And the drain are coupled, wherein in the pMOS transistor connected in series, the source of the first-stage PMOS transistor is coupled with the high-order voltage source, and in the series connected PMOS transistor, The gate and the drain coupled to the pMOS transistor in the last stage output the intermediate voltage level. 40 · The voltage level transfer method according to item 36 of the Shenyan patent scope, wherein the above-mentioned intermediate voltage level is generated by at least one NMOS transistor connected in series, wherein each NMOS transistor has A gate, a drain, and a source, the gate of each NMOS transistor connected in series is coupled to the drain, and the source of the NMOS transistor is connected to the NM connected in series to the next stage 〇s transistor Page 31 472451 6. The 5H gate of the patent application body is coupled to the drain, in which the gate and the drain and the high-order voltage of the Ronglong transistor of the first order in the series-connected NMOS transistor are coupled. The source is coupled, and the source of the NMOS transistor in the last stage outputs the intermediate voltage level in the NMOS transistor that is connected. 41. The voltage level transfer method according to item 36 of the scope of patent application, wherein the upper 2: 1: voltage level is generated by at least one diode connected in series, and each diode has an anode terminal and a diode. The cathode terminal, each of the two poles =% pole, is coupled to the cathode terminal of the previous stage diode, where the anode terminal of the first stage electrode in the string i is exposed to the high-order voltage source And the serially connected two plum _ φ, different # terminals output the cathode of the intermediate-level m quasi -... The two reference levels are generated by the -first-level level transfer to the second young flute. '1 The first-level level transfer device contains at least: J: level: differential pair transistor' has a pole, a drain And a source 'the first differential pair of the first stage Γ 夫: ΓΓ the first differential pair of the first body: the reference of the body; the first source of the first differential pair of the differential crystal And-the first-stage second differential pair transistor, and the source, the first-stage second differential pair; the brake gate, the -drain, and the anti-belief of the signal No. is used for “c” corresponding to this input. Page 32 VI: The scope of the patent application The source and the first-stage first load transistor are generated, and the -5th gate of the first-stage dynamic load transistor and the- Second negative second reference voltage The second differential pair potential of the first stage is lightly closed; if the gate electrode has a gate transistor, the second differential pair of the first stage, a drain, and the drain and The first-stage and second-pole-carrying transistor has the gate of the first-stage moving pair transistor coupled to the first-stage and the first-stage source and is coupled to a middle-order voltage level. The first stage and the first stage are connected for the bias voltage (the coupling of the B transistor, the source of the second differential pair of crystal and the intermediate stage i ased) ° the sum of the first stage negative pole , A drain pole and the pole and the first and second negative body of the sum pole and the second voltage device are coupled with a load-carrying crystal and a first-stage load-carrying crystal are coupled with the load and are electrically connected, and a crystal is a source and a Differential; and one-source two-differential, the crystal is subject to the second-stage first differential pair transistor, with the right 43. If the application of the scope of patent application No. 42 electric level transfer method, and the first difference The moving pair transistor and the first-stage second differential ~ bulk ir, _S transistor, and the first stage Load electrical system PM0S said said said said said said electrical body. The carrier signal and the I 44. The output signal as described in the 36th scope of the patent application _ Zhuan Yi output signal is produced by a second-level level transfer and even a level-level transfer device including at least ... The J.7T? Power-on crystal-on-level 472451 Sixth, the level and the source level and the first pole movement The first pole movement The CLP The patent scope level transfer device The first differential to the electricity A first reference bit, a reference voltage source, a first level, a second differential pole, the second level level shifting device, a second differential pair, the second reference position, a reference voltage source, a second level, a first load, and a second level pair. The gate of the transistor and the second-stage second load are generated by the gate of the second-stage second transistor and the source of the second-stage first-crystal high-voltage source. The second stage of the second crystal is coupled to the second stage; the second stage is coupled to the transistor, and the second stage is coupled to the transistor; the second stage is coupled to the transistor; A load transistor is coupled to the drain, and the second differential pair The body has two load transistor drain-phase couplings. The first stage differential is coupled to the load transistor to bias (reference) a reference level to produce the second stage first differential pair. Gate, the reference level of the gate of the crystal, which produces the second-stage first differential pair '~~ open pole, one $ and the drain-pole and the second-stage first transistor The; and a gate, one; and the drain and the second-stage second transistor, the source, the first, and the high-order voltage used for the second level transfer device crystal The source pole is coupled to a source corresponding to the first used in the second quasi-transfer device crystal, and a source first-stage differential load transistor pole is coupled; and And the pole phase of the first-stage second-differential load transistor of the source is closed, and the second-stage second-load source of the second phase is combined and subject to the 4 5 · If the voltage level transfer method of the 44th item in the scope of patent application, beans Τ described in p. The first differential-transistor pair and the second differential pair 472451 The current-carrying crystal and the second-stage NMOS transistor, and the second-stage second-loading transistor PMOS transistor. 46. — A voltage level shifter changes the signal to a high voltage level, and the steps are as follows: Method 'is used to transfer a low voltage level signal to the electrical level shift method. The method includes at least the following response to a voltage level Quasi-examination level, voltage level, stable voltage level, the second reference reference level corresponding to the most-test level, full transition level voltage level to generate an input signal, and the input signal to generate at least one first- The first reference state value is greater than the quasi-steady state value of the input signal, and the voltage level of each test level is stable or the first reference and the higher-order voltage level one level after the second reference level At least one medium-sized anti-wheel of the state of Ful 1 swing believes the reference level and level or the forgiveness of the first or the previous input level, compared with each voltage level level, and finally produces a The voltage swing is a finished signal. Order voltage level; number, and the first reference level of the inverting signal of the mid-order at least one second parametric reference level or the first steady-state value of the subsequent stage is small; the level of the Second reference 4 7. If the voltage level transfer party & of item 46 of the patent scope is declared, among which the above mentioned output € 1¾ voltage level is steady state and the value is equal to the high-level voltage level 4 8. The voltage level transfer method of the 46th item of the patent, wherein the h voltage level among the above will be lowered immediately after the input signal is switched. 472451 VI. Application for patent scope 4 9. The voltage level transfer method according to item 46 of the patent application scope, wherein each of the intermediate-level electric migration levels described is generated by at least one simple power supply connected in series, wherein the PMOS power The crystal has a closed pole, a non-polar pole, a body pole, and the gate of each PMOS transistor connected in series is coupled to the drain: and the source of the PMOS transistor is connected in series to the next stage The pM0s transistor, the closed pole, and the non-polar plane meet, # in the serially connected ρ_transistor, the source of the 4PM0S f crystal in the first stage is in phase with the first-order voltage source_ 合 曰In the body, the gate and the drain of the last stage of the simple transistor output the intermediate voltage level. 50. According to the voltage level transfer method of the 46th scope of the patent application, the intermediate level is described by at least one serially connected transistor, each of which has an electrode , A drain, and a pole: each of the gate of the delete transistor and the drain -5 in series, and the source of the NMOS transistor and the next level "combined with the device, where the string The gate and the pole connected to the two crystal i-electrodes are lightly connected, and the high-white power is [originally coupled 'and the NMOS transistor is connected in series. Finally, the “output” of the NMOS transistor is 51. For example, the voltage level of the 46th scope of the patent application is generated by at least one diode connected in series. Each pole has an anode end and a cathode end, and the anode end of the body and the front-stage two. The cathode terminal phase of the pole body_he = page 472451 6. Among the diodes applied for patent application, the first stage two phases are coupled, and the string I > _ & _ T 4% extremes and the higher order voltage The source outputs this middle-order voltage level. Set the cathode of the -stage diode 52. As the first reference position m & / & level transfer method described in the scope of the patent application, wherein the upward shift device is generated, the first f is a first The level shifts to the first differential pair transistor of the first level, and has a source, the first stage, the first electrode, a drain, and a signal for the first stage. The pole corresponds to the input; the source and the source of the -differential pair transistor are combined, the source and the source of the signal are produced by the source and the source of the signal. The gate and the second differential pair transistor of the power transistor have a gate and a first phase second differential pair electric inversion signal 'for the reference level of the 5th generation and the reference voltage A source is coupled to a load transistor, the gate has a first load transistor, a first gate, a second drain, a first drain, and a pole corresponding to two differential pairs of the input differential pair transistor. The drain of the crystal body is coupled, and the first-stage second differential pair of the first-stage second load transistor has a pole and the first-moving pair. A transistor, a gate, a drain, and a gate of the first transistor, a drain of the first transistor, and a drain of a source transistor, and a drain; One source: the drain of the first-stage second-differential first-load first transistor and the non-pole of the ^ body, the first-stage second-load; page 47472t 6. Application for a patented differential pair The transistor combination of the transistor, in which the first stage of the _th load of the transistor combination, and the intermediate order is set = the intermediate order voltage level is biased (Biased). And the 5: The voltage level transfer method as described in Item 42 of the Second Special Diley Range, which makes the first '. And the first-the differential pair transistor and the NMOS transistor of the system. Gu ^ sucks a differential pair of transistor -U ^^ f -th stage-load transistor and the first stage first load transistor system pMOS transistor. , ', And 54. If the voltage level transfer method of the 46th scope of the patent application is applied, the signal is generated by a second-level level transfer device, and the upper-level level transfer device includes at least: The dynamic pair transistor has an idler, a drain and a source, the first level and the second source of the reference second level, and the second level and the second difference The gate of the second first-stage first differential pair transistor corresponds to the first reference level generated by the first-shift device, and is used to generate the drain of the second movable pair transistor. The reference level of the second-stage. Level-shifting device, the source voltage source coupling of the second-stage first differential pair transistor; two differential pair transistors having a gate, a drain, and- The gate of the second differential pair transistor corresponds to the second reference level generated by the first shifting device, and is used to generate the second stage at the drain of the second differential pair transistor. Level transfer Pei reference level The source of the second stage second differential pair transistor 47245f The patent range is coupled to the reference voltage source; the second-stage first load transistor has a gate, a drain, and a source; the second-stage first load transistor has the drain and the second stage The drain of the first differential pair transistor is coupled, the gate of the second-stage first load transistor is combined with the non-polarity of the second-stage second differential pair transistor; and brother. A first-stage first load transistor, which has a pole, a light pole, and a source, the drain of the second-stage second load transistor and the second-stage second differential pair transistor. The poles are in phase, the gate of the second-stage second load transistor is coupled to the drain of the second-stage first differential pair transistor, and the source of the first-stage first-load transistor is The pole is coupled to the source of the second-stage second-load transistor, and is used to be consumed by the high-order voltage source and biased by the south-order voltage source (Biased). 5 5. The voltage level transfer method according to item 54 of the scope of patent application, wherein the second-stage first differential pair transistor and the second-stage second differential pair system NMOS transistor, and the The second-stage first load transistor and the second-stage second load transistor PMOS transistor. 5. If the voltage level in the 46th scope of the patent application is quoted, each of the-reference level or the second reference level in the second voltage level is referred to-go to two * L α ^ _ thousand you should respond to It is generated for the middle I5 white first old man. The first reference level of the mother level or the reference level of the reference level should be lower than the lower reference level of the mother level: the pressure level is smaller. Heiji the younger brother ^ Can the early-stage response to the intermediate-level electricity