CN102208910A - Level shift circuit - Google Patents
Level shift circuit Download PDFInfo
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- CN102208910A CN102208910A CN201010144073XA CN201010144073A CN102208910A CN 102208910 A CN102208910 A CN 102208910A CN 201010144073X A CN201010144073X A CN 201010144073XA CN 201010144073 A CN201010144073 A CN 201010144073A CN 102208910 A CN102208910 A CN 102208910A
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Abstract
The invention provides a level shift circuit, which is used for converting an input signal with a high level into an output signal with a low level. The level shift circuit is characterized by comprising a high level line, a low level line, a ground wire, a shaping circuit and an output circuit, wherein the shaping circuit is coupled between the high level line and the ground wire, and comprises an even number of stages of series-wound inverter units; the output circuit is coupled between the low level line and the ground wire, and comprises an even number of stages of series-wound inverter units; the inverter unit of the first stage comprises a first N-channel metal oxide semiconductor (NMOS) and a second NMOS; the drain of the first NMOS is connected to the low level line, and the gate of the first NMOS is connected to the input end of the inverter unit of the last stage of the shaping circuit; the source of the second NMOS is connected to the ground wire, and the gate of the second NMOS is connected to the output end of the inverter unit of the last stage of the shaping circuit; and the source of the first NMOS and the drain of the second NMOS are connected to the input end of the inverter unit of the next stage of the output circuit. The level shift circuit has quick response and low circuit delay.
Description
Technical field
The present invention relates to level shifting circuit (Level shift circuit), relate in particular to the level shifting circuit that a kind of high level signal converts low level signal to.
Background technology
In composite power source circuit especially SOC system, the supply power voltage of each circuit unit is also not quite identical, is difficult to unification, and the signal transmission between each circuit unit needs just can link up through conversion; In order to save energy consumption, need to reduce the operating voltage (for example 1.2V) of chip internal usually in addition, but between chip and the chip during transmission signals, still need (for example carry out under the 3.3V～5V) in higher voltage.Therefore, must use the input of level shifting circuit, to realize the level conversion of above-mentioned signal as chip, circuit unit.
In digital circuit, often utilize the CMOS inverter to form level shifting circuit.For example Fig. 1 provides a kind of existing level shifting circuit, comprising: shaping circuit 100, in order to receive the input signal of higher level, described input signal is put in order ripple; Output circuit 200 converts more low level output signal in order to the input signal that will put in order behind the ripple.Wherein shaping circuit 100 comprises the two-stage inverter module of serial connection, and the high order end of each inverter module is connected to high level line VDDH, and low order end is connected to ground wire; Output circuit 200 also comprises the two-stage inverter module of serial connection, and the high order end of each inverter module is connected to low level line VDDL, and low order end is connected to ground wire.Above-mentioned each inverter module is the CMOS inverter, wherein the MOS transistor in the first order inverter module of the inverter module of shaping circuit 100 and output circuit 200 is thick gate transistor, withstand voltage height, threshold voltage are also higher, but open, response speed is slower.MOS transistor in the second level inverter module of output circuit 200 then is thin gate transistor, and resistance to pressure is poor, and threshold voltage is relatively low, opens, response speed is very fast relatively.
The operation principle of the described circuit of Fig. 1 is as follows: suppose that input signal is a square wave, behind the then described input signal process shaping circuit two-stage inverter module, exporting a high bit level is VDDH, and low bit level is 0 square wave.Behind the two-stage inverter module via output circuit 200, export a high bit level is VDDL to described square wave again, and low bit level is 0 square wave.It is that the high level signal of VDDH has changed into the low level signal that high bit level is VDDL that said process is about to high bit level.If ignore the delay of inverter module circuit, final output signal should with the input signal homophase.
There are the following problems for existing level shifting circuit: in order to bear the high voltage signal that shaping circuit 100 is exported, the first order inverter module of output circuit 200 has all adopted high voltage bearing thick gate transistor.For ease of explanation, suppose in the first order inverter module of output circuit 200 that PMOS is that current potential pulls up transistor and is M0, then M0 source electrode and substrate all are connected to low level power line VDDL, and grid then is connected to the output O of shaping circuit 100.When the signal of the output O of shaping circuit 100 was in low level 0, then the electrical potential difference of the grid of M0 and substrate was VDDL.Above-mentioned electrical potential difference may will cause M0 to open less than the turn-on threshold voltage of thick gate transistor M0, make this grade inverter module produce logic error, and can not export high level, and then cause whole level shifting circuit to lose efficacy.Even M0 can open, its opening speed is also slower, causes circuit delay excessive.
Summary of the invention
The problem that the present invention solves provides a kind of level shifting circuit, and response speed is fast, and circuit delay is little, and output circuit first order inverter module is easy to generate logic error and the bigger problem of circuit delay in the existing level shifting circuit of solution.
Level shifting circuit provided by the invention is used for converting the input signal of high level to low level output signal, it is characterized in that, comprising:
High level line, low level line and ground wire;
Shaping circuit is coupled between high level line and the ground wire, comprises the inverter module of even level serial connection;
Output circuit is coupled between low level line and the ground wire, comprises the inverter module of even level serial connection, and wherein first order inverter module comprises a NMOS and the 2nd NMOS; The drain electrode of a described NMOS is connected to the low level line, and grid is connected to the input of the last level inverter module of shaping circuit; The source electrode of described the 2nd NMOS is connected to ground wire, and grid is connected to the output of the last level inverter module of shaping circuit; The drain electrode of the source electrode of a described NMOS and the 2nd NMOS is connected to the input of output circuit next stage inverter module.
Optionally, the inverter module of described shaping circuit is the CMOS inverter, and high order end all is connected to the high level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thick gate type transistor.
Optionally, the inverter module of described output circuit except that the first order is the CMOS inverter, and high order end all is connected to the low level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thin gate type transistor.
Optionally, a described NMOS and the 2nd NMOS are thick gate type transistor, and a described NMOS is identical with the specification of the 2nd NMOS.
Compared with prior art, level shifting circuit provided by the invention has the following advantages: the current potential in the first order inverter module of output circuit pulls up transistor and selects NMOS for use, and its grid is connected to the input of the last level of shaping circuit inverter module, make the output signal of shaping circuit be in when hanging down bit level, easier unlatching conducting pulls up transistor, thereby the raising response speed reduces circuit delay.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 is the circuit diagram of existing a kind of level shifting circuit;
Fig. 2 is the circuit diagram of level shifting circuit of the present invention;
Fig. 3 is the functional simulation figure of level shifting circuit shown in Figure 2.
Embodiment
In the prior art, the first order inverter module of output circuit is the CMOS inverter, and its current potential pulls up transistor and is PMOS.When the signal of shaping circuit output was positioned at the low level level, described current potential pulled up transistor because grid voltage is not enough, has the problem that is difficult to open conducting.The present invention pulls up transistor the current potential of the first order inverter module of output circuit and selects NMOS for use, and its grid is connected to the input of shaping circuit afterbody inverter module, thereby avoids above-mentioned because the grid voltage deficiency, and the problem that is difficult to conducting.
Level shifting circuit of the present invention comprises:
High level line, low level line and ground wire;
Shaping circuit is coupled between high level line and the ground wire, comprises the inverter module of even level serial connection;
Output circuit is coupled between low level line and the ground wire, comprises the inverter module of even level serial connection, and wherein first order inverter module comprises a NMOS and the 2nd NMOS; The drain electrode of a described NMOS is connected to the low level line, and grid is connected to the input of the last level inverter module of shaping circuit; The source electrode of described the 2nd NMOS is connected to ground wire, and grid is connected to the output of the last level inverter module of shaping circuit; The drain electrode of the source electrode of a described NMOS and the 2nd NMOS is connected to the input of output circuit next stage inverter module.
Optionally, the inverter module of described shaping circuit is the CMOS inverter, and high order end all is connected to the high level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thick gate type transistor.
Optionally, the inverter module of described output circuit except that the first order is the CMOS inverter, and high order end all is connected to the low level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thin gate type transistor.
Optionally, a described NMOS and the 2nd NMOS are thick gate type transistor, and a described NMOS is identical with the specification of the 2nd NMOS.
Below in conjunction with specific embodiment the concrete connection and the operation principle of circuit of the present invention are set forth.
Fig. 2 is a specific embodiment of the described level shifting circuit of real name, and Fig. 3 is the functional simulation figure of node signal in the circuit shown in Figure 2.In conjunction with Fig. 2 and Fig. 3 present embodiment is described.
At first as shown in Figure 2, the level shifting circuit in the present embodiment uses the inverter module of minimum progression for simplifying circuit structure.Described level shifting circuit comprises:
High level line VDDH, low level line VDDL, ground wire GND;
Generally, PMOS or NMOS all are connected substrate in order to eliminate substrate bias effect with its source electrode.Therefore each transistor also links to each other according to above-mentioned connected mode lining source in the foregoing circuit.
Pre-conditioned following, the described circuit of Fig. 2 is carried out functional simulation below.Fig. 3 then is the analogous diagram of specific node signal wherein.
The current potential of supposing high level line VDDH is that the current potential of 5V, low level line VDDH is 1V, and the threshold voltage of thick gate type transistor is 1.8V, and the threshold voltage of thin gate type transistor is 0.7V.At the input Input of the circuit of present embodiment level conversion, the input signal of input square wave type.The high bit level of described input signal is that 3.3V hangs down bit level and is-3.3V.
Above-mentioned input signal will be spacing by shaping behind the process first order inverter module 101 of shaping circuit 100.Because the high order end of first order inverter module 101 is connected in the high level line, low order end is connected in the low level line.When input signal is in high bit level 3.3V, current potential pull up transistor grid and the substrate reverse bias of PMOS, thereby close.The grid of current potential pull-down transistor NMOS and substrate potential difference are that 3.3V surpasses its threshold voltage, thereby conducting.First order inverter module 101 output levels are the level 0 of ground wire.And when input signal was in low bit level-3.3V, pull up transistor grid and the substrate potential difference of PMOS of current potential was that 3.3V surpasses its threshold voltage, thereby conducting.The grid of current potential pull-down transistor NMOS and substrate reverse bias, thereby close.First order inverter module 101 output levels are the level 5V of high level line VDDH.After also promptly passing through first order inverter module 101, be shaped to high bit level 5V, low bit level 0V, and the square wave anti-phase with input signal.After above-mentioned square wave passes through the second level inverter module 102 of shaping circuit 100 again, keep the current potential amplitude constant, obtain the square wave anti-phase with input at its output O point, but this square wave and aforementioned input signal homophase.
In the first order inverter module 201 of described output circuit 200, the grid of a NMOS M1 is connected with the input of drive end second level inverter module 102, and the grid of the 2nd NMOS M2 then is connected with the output of described second level inverter module 102.Make win NMOS M1 and the 2nd NMOSM2 have only one to be in conducting state all the time, another is in closed condition.When for example the current potential of shaping circuit output O was high potential 5V, its input current potential was 0V.This moment the grid of the 2nd NMOS M2 and substrate potential difference be 5V greater than its threshold voltage, thereby conducting; And the grid of a NMOS M1 and substrate potential difference are 0V, thereby close.Make the first order inverter module 201 of input circuit 200 export electronegative potentials.Otherwise when the current potential of shaping circuit output O was electronegative potential 0V, its input current potential must be high potential 5V.The grid of a NMOS M1 and the electrical potential difference of substrate are 5V at this moment, thereby conducting, and the grid of the 2nd NMOS M2 and the electrical potential difference of substrate are 0V, thereby close.Make the first order inverter module 201 of input circuit 200 export high potentials.Because above-mentioned first order inverter module 201 is coupled between low level line VDDL and the ground wire GND, therefore through behind this grade inverter module, the high bit level of output square wave is 1V, and low bit level is 0V, and square wave phase is opposite with aforementioned input signal.
It is pointed out that the first order inverter module 201 of above-mentioned input circuit 200, needing to receive maximum level is the square-wave signal of 5V, and therefore a NMOS M1 and the 2nd NMOS M2 need be thick gate type transistors.The one NMOS M1 pulls up transistor as current potential, the condition of its unlatching is that current potential is a high level on the grid, therefore avoided in the common CMOS inverter, adopt PMOS as crystal pulling brake tube PMOS on the current potential, grid is minimum can only to arrive 0V, and cause grid and substrate potential difference deficiency, the problem that is difficult to open.
Second level inverter module 202 for described output circuit 200, because the maximum level of the square wave that its input receives is 1V, requirement of withstand voltage is low, so this grade inverter module can adopt the CMOS inverter of thin gate type transistor formation, open response speed to improve, reduce circuit delay.
The output Output end that final output at second level inverter module 202 also is whole level shifting circuit obtains and the input signal homophase, but high bit level is 1V, and low bit level is the output signal of 0V.Thereby finish the level conversion of input/output signal.
The foregoing description, the inverter module level number average of shaping circuit and output circuit only is example with the two-stage, when reality is used, inverter module through odd level, the opposite signal of phase place will be obtained, and inverter module progression is many more, and the delay of circuit is just big more, but waveform quality also can correspondingly improve.Therefore should select according to concrete needs.Its operation principle and invention essence should be identical with present embodiment.Repeat no more.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (7)
1. a level shifting circuit is used for converting the input signal of high level to low level output signal, it is characterized in that, comprising:
High level line, low level line and ground wire;
Shaping circuit is coupled between high level line and the ground wire, comprises the inverter module of even level serial connection;
Output circuit is coupled between low level line and the ground wire, comprises the inverter module of even level serial connection, and wherein first order inverter module comprises a NMOS and the 2nd NMOS; The drain electrode of a described NMOS is connected to the low level line, and grid is connected to the input of the last level inverter module of shaping circuit; The source electrode of described the 2nd NMOS is connected to ground wire, and grid is connected to the output of the last level inverter module of shaping circuit; The drain electrode of the source electrode of a described NMOS and the 2nd NMOS is connected to the input of output circuit next stage inverter module.
2. level shifting circuit as claimed in claim 1 is characterized in that the inverter module of described shaping circuit is the CMOS inverter, and high order end all is connected to the high level line, and low order end all is connected to ground wire.
3. level shifting circuit as claimed in claim 2 is characterized in that, the MOS transistor in the described CMOS inverter is thick gate type transistor.
4. level shifting circuit as claimed in claim 1 is characterized in that, the inverter module of described output circuit except that the first order is the CMOS inverter, and high order end all is connected to the low level line, and low order end all is connected to ground wire.
5. level shifting circuit as claimed in claim 4 is characterized in that, the MOS transistor in the described CMOS inverter is thin gate type transistor.
6. level shifting circuit as claimed in claim 1 is characterized in that, a described NMOS and the 2nd NMOS are thick gate type transistor.
7. level shifting circuit as claimed in claim 6 is characterized in that, a described NMOS is identical with the specification of the 2nd NMOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010144073XA CN102208910A (en) | 2010-03-31 | 2010-03-31 | Level shift circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010144073XA CN102208910A (en) | 2010-03-31 | 2010-03-31 | Level shift circuit |
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| CN102208910A true CN102208910A (en) | 2011-10-05 |
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| CN201010144073XA Pending CN102208910A (en) | 2010-03-31 | 2010-03-31 | Level shift circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104506180A (en) * | 2014-12-12 | 2015-04-08 | 长沙景嘉微电子股份有限公司 | High-speed level transformation circuit |
| CN109245757A (en) * | 2018-11-08 | 2019-01-18 | 苏州云芯微电子科技有限公司 | One kind being based on capacity coupled common mode electrical level conversion circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1351421A (en) * | 2000-10-30 | 2002-05-29 | 株式会社日立制作所 | Level shift circuit and semiconductor integrated circuits |
| US20050231260A1 (en) * | 2004-04-14 | 2005-10-20 | Vaishnav Srinivas | Break before make predriver and level-shifter |
| CN1764069A (en) * | 2005-09-30 | 2006-04-26 | 威盛电子股份有限公司 | Voltage level converter |
-
2010
- 2010-03-31 CN CN201010144073XA patent/CN102208910A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1351421A (en) * | 2000-10-30 | 2002-05-29 | 株式会社日立制作所 | Level shift circuit and semiconductor integrated circuits |
| US20050231260A1 (en) * | 2004-04-14 | 2005-10-20 | Vaishnav Srinivas | Break before make predriver and level-shifter |
| CN1764069A (en) * | 2005-09-30 | 2006-04-26 | 威盛电子股份有限公司 | Voltage level converter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104506180A (en) * | 2014-12-12 | 2015-04-08 | 长沙景嘉微电子股份有限公司 | High-speed level transformation circuit |
| CN109245757A (en) * | 2018-11-08 | 2019-01-18 | 苏州云芯微电子科技有限公司 | One kind being based on capacity coupled common mode electrical level conversion circuit |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20131128 |
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Effective date of registration: 20131128 Address after: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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Application publication date: 20111005 |